JP2001186206A - Synchronizing circuit and method for following synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronizing circuit whose circuit scale is made small and which can operate with small power consumption and perform phase control with high accuracy without increasing the frequency of a reference clock. SOLUTION: When a reception timing detector 10 detects the phase shift of a receiving operation clock, a phase controlling part 12 temporarily changes the frequency division ratio of a frequency divider 14. A frequency controlling part 20 compares the output frequency of the divider 14 with that of a frequency divider 18 and controls the output frequency of an operation clock generating part 22 so as to make the frequencies coincide. According to the above procedures, the output frequency from the part 22 is changed and the phase of the receiving operation clock is also changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit in communication, and more particularly to an operation timing (phase) of the receiving circuit.
Is related to a synchronization circuit that synchronizes the
More specifically, the present invention relates to a synchronization tracking circuit that tracks the synchronization once captured.

[0002]

2. Description of the Related Art Conventionally, as a method of synchronizing the operation timing (phase) of a receiving circuit with a received signal, for example, a clock phase control circuit disclosed in Japanese Patent Application Laid-Open Nos. 4-172732 and 6-6397 is known. Have been.

For example, in Japanese Patent Laid-Open Publication No. Hei 6-6397, the clock phase control circuit includes a shift register 401 for delaying a reference clock which is m times the data clock and a frequency division of the shift register output as shown in FIG. Phase error correction circuit 4 for generating the operation clock of the receiving circuit
02.

Then, the timing error detection circuit 400 recognizes the delay or advance of the timing of the sampling clock having the same frequency as the operation clock, and detects the direction in which the sampling point is shifted.

On the other hand, the shift register 401 divides the frequency of a reference clock having a high frequency (m × f) such that the jitter is negligible with respect to the data clock frequency f, and the frequency of the reference clock is twice as high as the data clock frequency (2f). Generate an operation clock. Next, the clock phase error correction circuit 402 corrects the phase of the clock output from the shift register 401 according to the output signal of the timing error detection circuit 400.

It should be noted that substantially the same technique is used in the above-mentioned Japanese Patent Application Laid-Open No. 4-172834.

[0007]

However, in the technique described in the above publication, the shift register needs to operate at a frequency which is m times the data clock, and therefore consumes a large amount of power. In addition, since the phase correction accuracy is determined by the magnitude of the magnification m, it is necessary to increase the magnification m in order to increase the accuracy. However, as described above, in view of the power consumption, the value is set to be too large. It is difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is a synchronous circuit that can operate with reduced power consumption by reducing the circuit scale, and raises the frequency of a reference clock. It is an object of the present invention to provide a synchronous circuit capable of performing high-accuracy phase control without using a synchronous circuit.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems. First, a receiving operation clock which is a reference of an operation timing when receiving a reception signal is provided. A synchronization circuit for synchronizing the reception signal, a first clock generation unit for generating a reference clock, a first frequency divider for dividing the reference clock generated by the first clock generation unit, and a reception timing A second clock generation unit for generating a reception operation clock serving as a reference, a second frequency divider for dividing the reception operation clock generated by the second clock generation unit, and a frequency division by the first frequency divider A frequency control unit that controls the generated clock frequency of the second clock generation unit in accordance with the comparison result, and the reception operation clock A reception timing detecting section for detecting a phase shift between the reception signal and the reception operation clock, and a frequency divider of a second frequency divider for compensating for the phase shift detected by the reception timing detection section. And a phase control unit for controlling the ratio.

In the synchronous circuit having the first configuration, the first clock generator generates a reference clock, and the first frequency divider divides the frequency of the reference clock. In addition, the second
The clock generation unit generates a reception operation clock serving as a reference for reception timing, and the second frequency divider divides the generated reception operation clock. At this time, the reception timing detection section detects a phase shift between the reception signal and the reception operation clock, and the phase control section adjusts the frequency division ratio of the second frequency divider so as to compensate for the detected phase shift. As a result, the second frequency divider is controlled according to the controlled frequency division ratio.
Then, the frequency control unit compares the clock frequency-divided by the first frequency divider with the clock frequency-divided by the second frequency divider.
The generated clock frequency of the clock generation unit is controlled. Therefore, according to the synchronization circuit of the present invention, the reception operation clock m
Since it is not necessary to use a double reference clock, power consumption can be reduced.

Secondly, in the above-mentioned first configuration, the phase control section performs a control to return to an original value after changing a frequency dividing ratio for a predetermined time. Therefore, the influence of the correction operation is completed and does not remain in time, so that highly stable phase control can be performed.

Third, in the first or second configuration, the frequency control unit may be configured to divide the frequency of the clock divided by the second frequency divider by the first frequency divider. When the frequency is lower than the frequency of the circulated clock, control is performed to increase the generated clock frequency of the second clock generation unit,
On the other hand, if the frequency of the clock divided by the second frequency divider is higher than the frequency of the clock divided by the first frequency divider, the generated clock frequency of the second clock generator is decreased. It is characterized by performing the control to make it.

Fourthly, in any one of the first to third configurations, the frequency controlled by the frequency control unit is raised or lowered at a constant frequency.

Fifth, in any one of the first to fourth configurations, the time during which the phase control unit changes the frequency division ratio is variable. Therefore, by making the time during which the frequency division ratio is changed variable, fine-grained phase shift correction can be performed, and correction accuracy can be improved.

Sixth, in the fifth configuration, the phase control unit may increase the time during which the frequency division ratio is changed as the phase shift detected by the reception timing detection unit increases. It is characterized by. Therefore, by increasing the time during which the frequency division ratio is changed as the phase shift increases, quick phase shift correction can be performed, and the phase synchronization acquisition time can be shortened.

A seventh feature is that, in any one of the first to sixth configurations, the frequency division ratio changed by the phase control unit is variable. Therefore, by making the frequency division ratio changed by the phase control unit variable, fine phase shift correction can be performed.

Eighth, in the seventh configuration, the frequency control unit is increased according to a difference between the output frequency of the first frequency divider and the output frequency of the second frequency divider. Alternatively, the frequency to be lowered is made variable.
Therefore, by increasing the fluctuating frequency as the difference increases, quick phase shift correction can be performed, and the phase synchronization acquisition time can be shortened.

Ninth, in any one of the first to eighth configurations, when the value of the S / N ratio is smaller than a predetermined value, the frequency division ratio of the second frequency divider may be increased. Is fixed. Therefore, when the S / N ratio is deteriorated due to an increase in fading or the like, by fixing the frequency division ratio, it is possible to reduce the influence of the deterioration of the S / N ratio.

A tenth aspect is a synchronization tracking method for synchronizing a reception operation clock serving as a reference of an operation timing when a reception signal is received with the reception signal, wherein a first clock generation method for generating a reference clock is provided. And a first step of dividing the reference clock generated in the first clock generating step.
A frequency dividing step, a second clock generating step for generating a receiving operation clock serving as a reference for receiving timing, a second frequency dividing step for dividing the receiving operation clock generated in the second clock generating step, A frequency control step of comparing the clock divided by the 1 division step with the clock divided by the second division step, and controlling the generated clock frequency of the second clock generation step according to the comparison result A reception timing detecting step of operating with the reception operation clock and detecting a phase shift between the reception signal and the reception operation clock; and a second step of compensating for the phase shift detected by the reception timing detection step. A phase control step of controlling the frequency division ratio of the frequency divider.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a clock phase control circuit A as a synchronization circuit according to the present invention includes a reception timing detection unit 10, a phase control unit 12, a frequency divider (second frequency divider) 14, and a reference clock generation unit. (First clock generation unit) 16, a frequency divider (first frequency divider) 18,
A frequency control unit 20 and an operation clock generation unit (second clock generation unit) 22 are provided.

Here, the reception timing detector 10
Is for detecting the reception timing of the reception signal,
The timing information is extracted from the received signal, and a phase shift between the received signal and a reception operation clock (hereinafter, simply referred to as “operation clock”) from the operation clock generation unit 20 is detected.

The reception timing detector 10 includes:
For example, a DLL (Delay Locked Loop) in spread spectrum communication can be used. This DL
As an example using L, the reception timing detection unit 10
The correlators 100a, 100 are configured as shown in FIG.
b, 100c, squaring circuits 101a, 101b, subtractor 102, loop filter 103, delay circuit 105
a and 105b.

The correlators 100a and 100b are correlators for determining a phase shift, while the correlator 100c is a correlator for demodulating received data. Here, the correlator 100a,
As 100b, when one symbol (data modulation unit) is spread-modulated by m chips (m> 0: integer) on the transmitting side (not shown), the phase of the despreading spreading code is shifted by one chip. Two correlators are used. When the output of the correlator with the advanced phase is set to Early and the output of the correlator with the delayed phase is set to Late, the received signal is calculated based on a value P ("phase difference value") obtained by the following equation. Can be detected whether the phase of the operation clock is advanced or delayed.

P = Early ² -Late ² That is, since the correlator 100a outputs the Early and the correlator 100b outputs the Late, the Early is squared by the squaring circuit 101a, and the Late is squared. Squared by the squaring circuit 101b,
The phase difference value P is calculated by subtracting the output of the squaring circuit 101b from the output of 1a. The calculation of the phase difference value P is performed at predetermined intervals. Note that the loop filter 103 smoothes the output of the subtractor 102. FIG. 3 shows an S-curve in the DLL.

The operation clock output from the operation clock generator 22 is input to the spread code generator 104 of the reception timing detector 10, and the reception timing detector 10 operates according to the operation clock.

The phase control unit 12 controls the frequency division ratio of the frequency divider 14 in accordance with the detection result of the reception timing detection unit 10. If the phase is delayed, the phase control unit 12 When the phase is advanced, the frequency division ratio of the frequency divider 14 is temporarily lowered. Note that the case where the phase is delayed means that the phase is early.
It means that it is shifted toward y, and it means that P> 0. In addition, the case where the phase is advanced means that the phase is shifted toward Late, and that P <0.

The frequency divider 14 divides the frequency of the operation clock output from the operation clock generator 22, and the frequency division ratio can be changed by a control signal from the phase controller 12. When there is no control from the phase control unit 12, that is, when the frequency division ratio in the initial state is 1/40
96. Since the frequency of the operation clock generation unit 22 in the initial state is 32.768 MHz, the frequency after the frequency division in the frequency divider 14 in the initial state is 8 kHz.
Becomes

The reference clock generator 16 generates a stable and stable reference clock with high accuracy. In the present embodiment, the generated frequency is 12.6 MHz. Also,
The frequency divider 18 divides the reference clock to generate a clock for phase comparison, and in this embodiment, sets the frequency division ratio to 1/157.
5 is assumed. Then, the frequency after division is 12600/1.
It becomes 8 kHz at 575.

Further, the frequency control unit 20 controls the frequency generated by the frequency divider 14 and the frequency divider 18 (8 kHz in the embodiment).
z) is compared, and based on the result, a frequency control voltage of the operation clock generator 22 is generated.

The operation clock generator 22 generates an operation clock of the receiving circuit. In the present embodiment, the operation clock in the initial state is 32.768 MHz. That is, the reference frequency is 32.768 MHz. Further, the operation clock generation unit 22 can change the generation frequency by the control voltage from the outside, that is, the frequency control unit 20.

Next, the operation of the clock phase control circuit configured as described above will be described. First, when a reception signal is input to the reception timing detection unit 10, the reception timing detection unit 10 calculates and outputs the phase difference value P. The calculation of the phase difference value is the reception timing detection step. That is, the correlator 100a and the correlator 100b calculate the correlation value with the spread code whose phase is shifted by one chip from each other, the respective correlation values are squared by the squaring circuits 101a and 101b, and the subtractor At 102, the difference is calculated. The phase difference value P is output from the reception timing detection unit 10 in a form smoothed by the loop filter 103. The calculation and output of the phase difference value P are performed at every predetermined detection cycle. The output information of the phase difference value P is sent to the phase control unit 12. The phase controller 12 determines whether the phase difference value P is P> 0 or P <
It is determined whether it is 0.

If P> 0, the phase of the operation clock is delayed with respect to the received signal. Therefore, the phase control unit 12 temporarily sets the frequency division ratio of the frequency divider 14 to a predetermined time ( The frequency divider 14 is controlled to increase by a certain time (50 μs in the example of FIG. 4). This is the phase control step. For example, 1 is added to the value of the denominator in the frequency division ratio, and the value is changed from 1/4096 to 1/4097. As a result, the output frequency of the frequency divider 14 is about 7.998 kHz.
Becomes The frequency division of the frequency divider 14 is the second frequency dividing step. The predetermined time is a time shorter than the detection cycle of the reception timing detection unit 10.

On the other hand, the reference clock generation unit 16 generates a reference clock (first clock generation step), and
Divides the reference clock (first frequency dividing step).

Then, the frequency controller 20 compares the output frequency of the frequency divider 18 with the output frequency of the frequency divider 14 to generate a control voltage for the operation clock generator 22. This is the frequency control step. In this case, since the output frequency of the frequency divider 18 is 8 kHz and the output frequency of the frequency divider 14 is about 7.998 kHz, the output frequency of the operation clock generator 22 is higher than the output frequency of the reference clock generator. Is also determined to be low. Therefore, the frequency control unit 20 generates a control voltage for the operation clock generation unit 22 so as to increase the output frequency of the operation clock generation unit 22.
That is, control for increasing the control voltage is performed. The increasing range of the control voltage is constant.

Then, the output frequency of the operation clock generation unit 22 is set to the reference frequency of 32.768 kHz for a predetermined time.
Since the frequency becomes higher than z, the reception operation clock changes in the direction in which the phase advances.

After the lapse of a predetermined time, the frequency division ratio of the frequency divider 14 is set to 1/4096 of its original value, so that the output frequency of the operation clock generation unit 22 returns to 32.768 MHz and the phase change of the operation clock Will stop.

The above processing is repeated until the phase shift is eliminated. That is, the reception timing detector 10
In the subsequent detection timings, if P> 0, the frequency division ratio of the frequency divider 14 is set to 1/4097 again, and the output voltage of the operation clock generation unit 22 is increased by increasing the control voltage for a predetermined time. To raise.

When the phase shift is eliminated and P = 0, the phase controller 12 keeps the frequency division ratio of the frequency divider 14 at 1/4096.

For example, in the above example of spread spectrum communication, the chip rate is set to の of the reception operation clock.
(Ie, 16.384 MHz), and when the initial phase shift is 0.5 chip delay, the phase control unit 12
Consider a case where the frequency division ratio of the frequency divider 14 is changed to 1/4097 during the period s.

For the sake of simplicity, when the frequency division ratio is changed to 1/4097, the output frequency from the operation clock generator 22 is changed from 32.768 MHz to 3 as shown in FIG.
Assume a change to 2.776 MHz. Then, 32.776 MHz−32.768 MHz = 8 kHz, and the phase advances by one period of the receiving operation clock in 125 μs. When converted to a chip rate, 1 in 250 μs
The phase of the chip advances. Accordingly, the phase control unit 12
When the frequency division ratio of the frequency divider 14 is changed to 1/4097 during the period of μs, correction is performed to advance the phase by 0.2 chips. FIG. 4B shows the relationship between the time and the phase shift at this time.

On the other hand, if the phase difference value P calculated by the reception timing detection unit 10 is P <0, it means that the phase of the operation clock is behind the reception signal. In contrast, the phase can be corrected in the same procedure as described above by reducing the frequency division ratio of the frequency divider 14 in reverse.

That is, the frequency divider 14 is controlled so as to temporarily lower the frequency division ratio of the frequency divider 14 for a predetermined time. This is the phase control step. For example, the value of the denominator in the frequency division ratio is subtracted by 1, and 1/4096 to 1/4095
Change to The frequency divider 14 performs frequency division according to the frequency division ratio (second frequency division step).

Then, the frequency control section 20 compares the output frequency of the frequency divider 18 with the output frequency of the frequency divider 14 to generate a control voltage for the operation clock generation section 22 (frequency control step). In this case, the output frequency of the frequency divider 18 is 8 kHz, and the output frequency of the frequency divider 14 is 8 kHz.
Therefore, it is determined that the output frequency of the operation clock generator 22 is higher than the output frequency of the reference clock generator. Therefore, the frequency control unit 20 generates a control voltage for the operation clock generation unit 22 so as to reduce the output frequency of the operation clock generation unit 22. That is, control for decreasing the control voltage is performed. The decrease width of the control voltage is constant.

Then, the output frequency of the operation clock generation unit 22 is changed to the reference frequency of 32.768 kHz for a predetermined time.
Since the frequency is lower than z, the receiving operation clock changes in the direction in which the phase is delayed.

After the elapse of the predetermined time, the frequency division ratio of the frequency divider 14 is set to 1/4096 of the original, so that the output frequency of the operation clock generation unit 22 returns to 32.768 MHz, and the phase change of the operation clock Will stop.

The above processing is repeated until the phase shift is eliminated. That is, the reception timing detector 10
In the subsequent detection timings, if P <0, the frequency division ratio of the frequency divider 14 is set to 1/4095 again, and the control voltage is lowered for a predetermined time, so that the output frequency of the operation clock generator 22 is reduced. Lower it.

For example, in the example of FIG. 4, the phase shift may be corrected beyond the center point (zero cross point) by correcting the phase shift by 0.2 chips. In this case, the polarity of P is reversed, so that the reverse process is performed.

In the above description, the frequency divider 14
Has been described as being a fixed time, but is not limited thereto, and may be variable. For example, when the absolute value of the phase difference value P is large, the time is lengthened, and when the absolute value is small, the time is shortened, such that the time is shortened. You may do so. By doing so, when there is a large phase shift, phase correction can be performed quickly, and when there is a small phase shift, excessive phase correction can be prevented.

In the above description, the division ratio is set to +
Although described as being changed by 1 or −1, this may be made variable. For example, when the absolute value of the phase difference value P is large, the change amount of the frequency division ratio is increased, and when the absolute value is small, the change amount of the frequency division ratio is reduced. You may make it change according to the value of P. By doing so, when there is a large phase shift, phase correction can be performed quickly, and when there is a small phase shift, excessive phase correction can be prevented. When the frequency division ratio is made variable, the rising width and the falling width of the control voltage are made variable according to the difference between the output frequency of the frequency divider 14 and the output frequency from the frequency divider 18. I do. As a result, the control voltage is made variable according to the value of the phase difference value P. When the polarity of the phase difference value P is positive, the control voltage is increased by a value corresponding to the value of the phase difference value P. When the polarity of the phase difference value P is negative, the control voltage is decreased by a value corresponding to the magnitude of the absolute value of the phase difference value P. For example, when the operation clock is significantly delayed from the received signal, the frequency divider 1
The frequency division ratio of 4 is also greatly changed. For example, 1/4096
To 1/4100. Then, the difference between the output frequency of the frequency divider 14 and the output frequency of the frequency divider 18 increases, so that the increase in the control voltage also increases. Further, the number of times the frequency division ratio is changed may be determined each time the correction is performed, that is, for each detection cycle of the reception timing detection unit 10, or may be set to 1
A plurality of correction times may be performed.

When the S / N ratio is lowered due to an increase in fading or the like, the phase shift correction is not performed by setting α of the frequency division ratio 1/4096 ± α in the frequency divider 14 to 0. Good. Further, instead of setting α to 0, α may be fixed.

In this embodiment, the frequency generated by the reference clock generator 16 is 12.6 MHz, and the frequency generated by the operation clock generator 22 in the initial state is 3 MHz.
Although the output frequency in the initial state of 2.768 MHz and the frequency divider 14 and the frequency divider 18 is set to 8 kHz, similar results can be obtained by using other combinations of frequencies. That is, it is sufficient that the same comparison frequency is obtained by appropriately adjusting the frequency division ratio of the frequency divider 14 and the frequency divider 18.

In this embodiment, the case of spread spectrum communication has been described as an example. However, similar functions can be realized in other communication systems.

In this embodiment, the case where the DLL is used as the means for detecting the phase difference between the reception signal and the reception operation clock has been described as an example. However, another method capable of detecting the phase difference is used. Is also good. For example, a method of detecting the direction of the phase shift by monitoring the temporal movement of the phase component obtained from the demodulated signal may be used.

In the present embodiment, the phase difference between the despread codes input to the two correlators used in the DLL is set to one chip.
For example, the phase difference may be 0.5 chip. In the present embodiment, the two correlator outputs used in the DLL are squared and used, but the absolute value of the correlation output may be simply used.

In the example of the spread spectrum communication of the present embodiment, the chip rate is set to １ ／ of the reception operation clock.
(Ie, 16.384 MHZ), but may be 1 / N (N: a positive integer).

[0056]

According to the synchronization circuit and the synchronization tracking method according to the present invention, it is not necessary to use a reference clock which is m times as large as the reception operation clock, so that power consumption can be reduced without greatly increasing the operation clock of the entire receiver. It is possible to perform highly accurate phase correction with a small amount.

Further, when the time during which the frequency division ratio is changed is made variable or when the frequency division ratio to be changed is made variable, fine phase shift correction can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock phase control circuit based on an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a reception timing detection unit.

FIG. 3 is an explanatory diagram showing an S curve in a DLL.

FIG. 4 is an explanatory diagram illustrating an operation in the clock phase control circuit according to the embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a clock phase control circuit according to the related art.

[Explanation of symbols]

 A clock phase control circuit 10 reception timing detection unit 12 phase control unit 14, 18 frequency divider 16 reference clock generation unit 20 frequency control unit 22 operation clock generation unit

Claims (10)

[Claims] 1. A synchronizing circuit for synchronizing a reception operation clock serving as a reference of an operation timing when a reception signal is received with the reception signal, wherein the first clock generation unit generates a reference clock; A first frequency divider for dividing the reference clock generated by the clock generation unit, a second clock generation unit for generating a reception operation clock serving as a reference for reception timing, and a reception generated by the second clock generation unit A second frequency divider for dividing the operation clock; a clock divided by the first frequency divider;
A frequency controller that compares the clock divided by the frequency divider and controls a generated clock frequency of the second clock generator in accordance with a result of the comparison. A reception timing detection unit that detects a phase deviation from the reception operation clock; a phase control unit that controls a frequency division ratio of the second frequency divider so as to compensate for the phase deviation detected by the reception timing detection unit; A synchronization circuit, comprising: 2. The synchronizing circuit according to claim 1, wherein the phase control unit performs control to return to an original value after changing a frequency dividing ratio for a predetermined time. 3. The frequency controller according to claim 2, wherein the frequency of the clock divided by the second frequency divider is lower than the frequency of the clock divided by the first frequency divider. When the frequency of the clock divided by the second frequency divider is higher than the frequency of the clock divided by the first frequency divider, control is performed to increase the clock frequency generated by the clock generator. 3. The synchronous circuit according to claim 1, wherein control is performed to lower a generated clock frequency of the second clock generating unit. 4. The frequency control unit according to claim 1, wherein the frequency raised or lowered by said frequency control unit is constant.
Or the synchronous circuit according to 3. 5. The synchronizing circuit according to claim 1, wherein the time during which the phase control unit changes the frequency division ratio is variable. 6. The synchronizing circuit according to claim 5, wherein the phase control unit increases the time during which the frequency division ratio is changed as the phase shift detected by the reception timing detection unit increases. . 7. A frequency division ratio to be varied by said phase control section is variable.
Or the synchronous circuit according to 5 or 6. 8. The frequency control unit according to claim 1, wherein the frequency control unit raises or lowers the frequency according to a difference between the output frequency of the first frequency divider and the output frequency of the second frequency divider. The synchronization circuit according to claim 7, wherein: 9. The frequency divider according to claim 1, wherein the frequency division ratio of the second frequency divider is fixed when the value of the S / N ratio is smaller than a predetermined value. 5 or 6 or 7
Or the synchronous circuit according to 8. 10. A synchronization tracking method for synchronizing a reception operation clock serving as a reference of an operation timing when a reception signal is received with the reception signal, wherein: a first clock generation step of generating a reference clock; A first frequency dividing step for dividing the reference clock generated in the one clock generating step, a second clock generating step for generating a receiving operation clock serving as a reference of the receiving timing, A second frequency dividing step for dividing the receiving operation clock; a clock divided by the first frequency dividing step; and a clock divided by the second frequency dividing step. A frequency control step of controlling a generated clock frequency in the second clock generation step; and operating by the reception operation clock, wherein a phase of the reception signal and a phase of the reception operation clock are different. And a phase control step of controlling the frequency division ratio of the second frequency divider so as to compensate for the phase shift detected by the reception timing detection step. Synchronous tracking method.