JP2001186199A - Circuit for detecting transmission speed and optical receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission speed detection circuit and an optical receiver, whose circuit and device can be made inexpensive and small-sized, concerning a transmission speed detection circuit and the optical receiver applying the transmission speed detection circuit. SOLUTION: This transmission speed detection circuit calculates the average value of digital outputs identifying a received signal, outputs a pulse when the average value exists in a prescribed level range, detects the average value level of a signal including the pulse, and performs digital conversion of the average value level to detect the transmission speed, and the optical receiver supplies the identified digital output to the transmission speed detection circuit, detects the transmission speed of the received signal, and selects a clock corresponding to the detected transmission speed, so as to reproduce the identified received signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transmission rate detection circuit and an optical receiver to which the transmission rate detection circuit is applied.
In particular, the present invention relates to a transmission speed detection circuit and an optical receiving device that can reduce the cost and size of circuits and devices.

[0002] It has been a long time since optical transmission technology was put into practical use. Initially, optical transmission technology was used on relatively low-speed lines, but soon it was applied to high-speed lines.
Nowadays, it is applied to digital transmission backbones of Gb / s (10 ⁹ bits / sec) class to 10 Gb / s class regardless of domestic and overseas, and is a fundamental technology of transmission technology.

Further, the cost of the entire optical transmission system including the cost of the optical fiber transmission line has been rapidly reduced, and the optical transmission technology has been applied not only to the backbone line but also to the subscriber line region. .

[0004] With the rapid spread of the Internet, which started around the same time, the demand for information transmission by the Internet protocol has increased rapidly, and an increase in the transmission capacity of the optical transmission system has been strongly demanded.

[0005] In order to meet the above demand, construction of a photonic network using a wavelength division multiplexing transmission system has been promoted.

In such a photonic network, a plurality of optical signals having different transmission speeds are often transmitted by light having a plurality of different wavelengths. It is also necessary to consider that there is a need to change the capacity of information transmitted by light of a specific wavelength.

Therefore, in an optical receiving apparatus in a photonic network, a transmission rate is detected from a received signal, a clock that matches the transmission rate is autonomously selected to reproduce the received signal, and digital processing at a subsequent stage is performed. It is desired to provide a device with a so-called bit-free function capable of supplying a clock corresponding to the transmission speed.

[0008] This is because, by making the bit free, it becomes possible to adapt to any one of a plurality of transmission rates, so that it is not necessary to adjust the transmission rate at the time of installation of the optical receiver. In addition, when the transmission speed changes after the start of operation, readjustment of the optical receiving device is not required, and it is not necessary to design and manufacture a different optical receiving device for each transmission speed.

[0009] Since this allows a photonic network to be configured with an optical receiver of a single specification, it is not only an advantage for a manufacturer but also a communication business operator operating the photonic network. It also offers significant benefits.

[0010]

FIG. 8 shows an optical receiving apparatus to which a conventional transmission rate detecting circuit is applied.

In FIG. 8, reference numeral 1 denotes an optical-to-electrical conversion circuit having a photodiode for converting a received optical signal into an electric signal, and 2 denotes a pre-amplifier for amplifying the output of the optical-to-electrical conversion circuit 1 with low noise. The main amplifier circuit 3 amplifies the amplitude of the output of the preamplifier circuit 2 to an amplitude sufficient for the discrimination operation in the subsequent stage, and the main amplifier circuit 3 based on a predetermined threshold value.
Is a discriminating circuit that discriminates the logical level of the output of the above and outputs digital signal levels of “0” and “1”.

Incidentally, in order to simplify the circuit configuration, the identification circuit 4 can be configured by a limiter amplifier.
In addition, when the main amplifier is used as a limiter amplifier, the identification circuit can be omitted.

Reference numeral 5c denotes a transmission speed detection circuit for detecting a transmission speed from the output of the identification circuit 4, a counter 58 for counting pulses output from the identification circuit, and a multi-bit signal for recognizing the count value output by the counter 58. Is output from the logical comparison circuit 59.

Reference numeral 6 denotes a clock selection circuit for selecting a clock frequency matched to the transmission speed based on a signal output from the logic comparison circuit 59, and decodes a plurality of bits output from the logic comparison circuit 59 constituting the transmission speed detection circuit 5c. The decoder (denoted as “DEC” in the figure.
corder ". ) 60, a first frequency dividing circuit 61 and a second frequency dividing circuit 62 for dividing the output of a phase locked loop circuit to be described later at different frequency division ratios, and one output of the decoder 60 as one input terminal. And an AND circuit 63 for receiving the output of a phase locked loop circuit described later to the other input terminal, and receiving one output different from the above output of the decoder 60 at one input terminal, 6
AND circuit 64 receiving the output of 1 at the other input terminal
And an AND circuit 65 that receives one output different from the above two outputs of the decoder 60 at one input terminal and receives the output of the second frequency divider 62 at the other input terminal, and AND circuits 63 to 65 OR circuit 66 that performs a logical OR operation on the output of
It is constituted by and. Here, three clocks,
That is, an example is shown in which one clock is selected from the output of the phase locked loop circuit, the output of the first frequency divider 61, and the output of the second frequency divider 62. The number is not limited to three.

Numeral 7 denotes a phase locked loop circuit which is a clock source whose frequency and phase are stabilized. The phase lock loop circuit compares the output of the discriminating circuit 4 with the output of the OR circuit 66 constituting the clock selecting circuit 6. A low-pass filter (abbreviated as “LPF” in the figure, which extracts the DC component of the output of the comparison circuit 70 and the phase comparison circuit 70 and defines the loop characteristics of the phase-locked loop circuit 7. , “LPF” is “Lo
This is an abbreviation that takes the initials of "w Pass Filter." ) 71
And a voltage-controlled oscillator circuit that controls the oscillation frequency according to the DC level output from the low-pass filter 71 (“VC
O ". “VCO” stands for “Voltage Cont.
Rolled Oscillator is an abbreviation that takes the initials. )
72.

Reference numeral 8 denotes an output of the discrimination circuit 4 which is received at a data terminal (abbreviated as "D" in the figure. "D" is an acronym of "Data"), and The output is a clock terminal (abbreviated as “C” in the figure.
Is an acronym for "Clock". ), The identification circuit 4
This is a flip-flop that reproduces the digital output of.

From the output terminal of the flip-flop 8 (abbreviated as “Q” in the figure), data reproduced from the received signal is supplied to a digital processing circuit at the subsequent stage, and the output of the clock selection circuit 6 is output. Is supplied to the subsequent digital processing circuit as a clock signal.

The format of the main code to be transmitted is R
Z (Return to Zero) code and NRZ (Non-Return to Ze
ro) There are codes, but in each case, the mark ratio and the number of consecutive identical codes are defined by the coding rules. Therefore,
If the number of pulses in the digital output of the discriminating circuit 4 is counted over a period in which the mark rate and the number of consecutive identical codes are specified, the counted value of the pulses of the discriminated digital signal is almost proportional to the transmission speed.

That is, in the transmission rate detecting circuit, the count value of a plurality of bits of the counter 58 is compared with the logical comparison circuit 59.
In the clock selection circuit 6, when the decoder 60 decodes the output of a plurality of bits of the logical comparison circuit 59, a signal for selecting a clock frequency corresponding to the transmission speed is output to different output terminals of the decoder 60. Is done.

In the case of FIG. 8, the clock selection circuit 6 outputs a clock which is the output of the phase locked loop circuit 7 itself, a clock which has been frequency-divided by the first frequency dividing circuit 61,
One of three clocks divided by the second frequency dividing circuit 62 at a frequency division ratio different from that of the first frequency dividing circuit 61 is 1
Since three different clocks are selected from the decoder 60, if the decoder 60 supplies three different selection signals corresponding to the transmission speed, the AND circuits 63 to 65 select one of the three clocks. can do. An OR circuit 66 is provided so that a clock selected from any of the AND circuits can be output.

The selected clock is supplied to one input terminal of the phase comparison circuit 70 of the phase locked loop circuit 7, and a phase difference from the output of the identification circuit 4 is detected. As a result, a pulse having a unique relationship with the variation of the phase difference between the selected clock and the output of the discrimination circuit 4 is generated, and changes in the low-pass filter 71 in accordance with the variation of the phase difference. Since the oscillation frequency and phase of the voltage controlled oscillation circuit 72 are controlled by the direct current, the frequency and phase of the clock output from the OR circuit 66 are both stabilized.

Then, by the flip flop 8,
Since the output of the discrimination circuit 4 is reproduced by the selected clock, the reproduced data can be supplied as correct data to a digital processing circuit at the subsequent stage, and the output of the OR circuit 66 is adapted to the transmission speed. The clock can be supplied to a digital processing circuit at a subsequent stage.

[0023]

In the configuration shown in FIG. 8, however, the clock frequency is recognized based on the value obtained by counting the pulses output from the identification circuit 4 for a predetermined time, and the clock is selected. The number of bits of the count value will be different.

Since the configuration of FIG. 8 is configured to select one clock from clocks of three frequencies, the following description does not exactly match the configuration of FIG.
Transmission speeds that can be used are 150 Mb / s, 600 Mb / s
s, 2.4 Gb / s, and 10 Gb / s. When any of these is selected, it is necessary to count at the same gate time for any transmission speed. Accordingly, the ratio of the count values is as high as about 60: 1 during the above transmission speed.

In addition, since the transmission rate is estimated based on the number of pulses output from the discriminating circuit 4, the gate time of the counter 58 needs to be increased to some extent so that a count value proportional to the transmission rate can always be obtained. There is.

Therefore, the count value of the counter 58 has a large number of bits from the beginning, and is 1 at the maximum speed of 10 Gb / s.
Since the count value becomes approximately 60 times as large as 50 Mb / s, the number of bits of the count value is increased by 5 bits to 150 mb / s in the case of 10 Gb / s.

For this reason, the scale of the counter 58 is increased, and the number of bits to be recognized by the logical comparison circuit 59 is increased. As a result, the circuit scale of the logical comparison circuit 59 is disadvantageously increased.

The counter 58 has a maximum transmission speed of 10G.
It must be able to operate at b / s, and it is necessary to select an expensive high-speed process for the process of forming a semiconductor integrated circuit.

Furthermore, in order to operate the counter 58 at high speed, the operating current of the elements constituting the counter 58 must be increased, and the power consumption is increased in addition to the disadvantage that the circuit scale is increased. The other disadvantage of becoming

For this reason, the junction temperature of the semiconductor integrated circuit rises, and if left unattended, the reliability of the semiconductor integrated circuit is reduced. To avoid this, a heat radiating mechanism is required, which further increases the price of the semiconductor integrated circuit and increases the size of the device.

The present invention has been made in view of the above problems, and has as its object to provide a transmission speed detection circuit which can be reduced in size at a low cost, and an optical receiving apparatus to which the transmission speed detection circuit which can be reduced in size at a lower cost. Aim.

[0032]

The first means of the present invention is as follows.
Applying a digital output identifying the received signal to a low-pass filter, outputting a pulse when the level of the output waveform of the low-pass filter is within a predetermined level range, and averaging the signal including the pulse. This is a configuration of a transmission rate detection circuit that detects a value level and converts the average value level into a digital signal.

According to the first aspect of the present invention, the number of pulses generated when the level of the output waveform of the low-pass filter is within a predetermined level range is proportional to the transmission rate and includes the pulses. Since the average value level of the signal is also proportional to the transmission speed, it becomes possible to select a clock having a frequency corresponding to the transmission speed by a signal obtained by digitally converting the average value level of the signal including the pulse.

In addition, since the pulse is output when the average value of the digital signal identifying the received signal is within a predetermined level range, the transmission rate detecting circuit can be constituted by a circuit which cannot necessarily cope with the maximum transmission rate. Become.

The second means of the present invention is to output a pulse corresponding to a phase difference between a digital output identifying a received signal and a signal obtained by delaying and digitally inverting the digital output, and outputting a signal including the pulse. This is a configuration of a transmission rate detection circuit that detects an average value level and converts the average value level into a digital signal.

According to the second aspect of the present invention, the number of pulses corresponding to the phase difference between the digital signal obtained by discriminating the received signal and the signal obtained by delaying and inverting the digital signal is proportional to the transmission speed. Since the average value level of the signal including the pulse is also proportional to the transmission speed, a clock having a frequency corresponding to the transmission speed of the received signal is selected by a signal obtained by digitally converting the average value level of the signal including the pulse. Becomes possible.

In addition, since a pulse corresponding to the phase difference between the digital signal that has identified the received signal and the signal obtained by delaying and logically inverting the digital signal is generated, even if the circuit cannot always support the maximum transmission speed, the transmission speed detection circuit can be used. Can be configured.

[0038] A third means of the present invention is the transmission rate detecting circuit according to any one of the first means of the present invention and the second means of the present invention, wherein after detecting the average value level of the signal including said pulse. , A transmission rate detection circuit for digitally converting a signal obtained by logarithmically amplifying the average level.

According to the third means of the present invention, since the average value of the signal including the pulse is logarithmically converted, the change in the output level of the logarithmic amplifier with respect to the change in the transmission rate is made constant over a wide range of the transmission rate. This can facilitate the digital conversion of the output level of the logarithmic amplifier.

Further, the transmission rate detecting circuit can be constituted by a circuit which cannot necessarily cope with the maximum transmission rate, as in the first means of the present invention and the second means of the present invention.

According to a fourth aspect of the present invention, a received optical signal is converted into an electric signal, a received signal after a predetermined amplification is identified,
In an optical receiving device that reproduces and outputs the identified digital output by a clock, the identified digital output is supplied to any one of the first to third transmission rate detection circuits of the present invention. This is a configuration of an optical receiver that detects a transmission speed of a received signal, selects a clock having a frequency corresponding to the detected transmission speed, and reproduces the identified received signal.

According to the fourth means of the present invention, a transmission rate detecting circuit which is formed by an inexpensive process and can detect the transmission rate even if it cannot respond to the maximum transmission rate is applied. Thus, it is possible to reduce the cost of the optical receiver and to reduce the power consumption.

[0043]

FIG. 1 shows a first embodiment of a transmission rate detecting circuit according to the present invention.

In FIG. 1, reference numeral 50 denotes a low-pass filter that passes the output of the identification circuit.

Reference numeral 51 denotes a window comparator which detects that the output waveform of the low-pass filter 50 passes through a predetermined threshold range and outputs a pulse;
A power supply -12 sets a predetermined threshold value in the window comparator. Here, the voltage of the power supply 51-11 is set to V
_1, the voltage of the power supply 51 - 12 and V _2, for convenience V _1> V
_Leave it as ₂ .

Reference numeral 52 denotes an average value detection circuit for detecting an average value of a signal including a pulse output from the window comparator 51. This is constituted by an integrating circuit composed of a resistor and a capacitor.

Reference numeral 53-1 denotes a first comparator for judging the level of the DC output from the average value detection circuit 52 with a predetermined threshold value and converting it into digital values "0" and "1".
2 is a second comparator that determines the level of the DC output from the average value detection circuit 52 with a threshold different from that of the first comparator 53-1 and converts it into digital values “0” and “1”;
53-11 is a power supply for supplying a threshold voltage to the first comparator 53-1, and 53-21 is a power supply for supplying the second comparator 53-1.
Power supply for supplying a threshold voltage to the first comparator 5
3-1, second comparator 53-2, power supply 53-11
And a power supply 53-21 to form a window comparator. Here, the voltage of the power supply 53-11 is set to V ₃ ,
The voltage of the power supply 53-21 and V _4, keep the convenience V _3> V _4.

The transmission speed detecting circuit 5 of the present invention is constituted by the above-mentioned components.

FIG. 2 is a diagram for explaining the operation of the configuration of FIG. Hereinafter, the first embodiment of the transmission rate detecting circuit of the present invention will be described in detail with reference to FIG.

In FIG. 2, (1) is the output of the identification circuit. Here, a signal whose logic level alternates between "0" and "1" (a code of logic level "1" for an RZ signal, a code of logic level "0" for an NRZ code). This signal is a signal that alternately repeats the sign of “1”), but this is merely an example for explanation, and in actuality, the sign of the logic level is “0” and the sign of “1” is
Appears arbitrarily within the range of the sign rule.

The output of the identification circuit is the low-pass filter 5 of FIG.
After passing through 0, the high-frequency components at the rising and falling portions of the pulse are attenuated, resulting in a pulse having a blunt waveform. This is shown in (2).

The window comparator 51 shown in FIG.
It is easy to voltage of the output waveform of the low-pass filtering unit 50 is set so as to output a pulse when V ₂ or V ₁ or less. Therefore, window comparator when the voltage is in the range of V ₂ or V ₁ or less at the rising portion and the falling portion of the output waveform of the low-pass filtering unit 50 outputs a pulse.

Naturally, the number of rising portions and falling portions in the output waveform of the discriminating circuit is proportional to the transmission speed. Therefore, the number of pulses output by the window comparator is higher when the transmission speed is higher than when the transmission speed is lower. Increase. This is shown in (3).

Therefore, the average voltage of the output of the window comparator 51 is higher when the transmission speed is high than when the transmission speed is low. This is shown in (4). In this case, the average value voltage when the transmission speed is faster is higher than the threshold voltage V _3, the average value voltage when the transmission speed is slow and ones that are set higher than the threshold voltage V ₄ are lower than the threshold voltage V ₃ I do. Of course, setting as described above is easy.

Therefore, when the transmission speed is high, there is a range in which both the first comparator 53-1 and the second comparator 53-2 output the logical level "1". On the other hand, when the transmission speed decreases, there is a range where the first comparator outputs a logical level “0” and the second comparator outputs a logical level “1”. Although not shown in FIG. 2, there is a range in which both the first comparator and the second comparator output a logical level “0” when the transmission speed further decreases.

That is, the transmission rate detecting circuit having the configuration shown in FIG. 1 makes it possible to distinguish and detect three transmission rates.

Then, the transmission speed detection circuit 5 having the configuration of FIG.
Is used in place of the transmission speed detection circuit 5c having the configuration of FIG. 8, the output of the voltage controlled oscillation circuit 72, the output of the first frequency divider 61, and the output of the second frequency divider 62 shown in FIG. Either can be selected.

In FIG. 2, the output waveform of the low-pass filter is drawn to reach the logical level "1", but the output waveform of the low-pass filter is not necessarily the logical level "1". , The above operation can be realized.

That is, even if the output waveform of the low-pass filter does not reach the logic level “1”, the threshold voltages V ₁ and V ₂ are set within the level of the output waveform of the low-pass filter. If the output waveform of the low-pass filter is equal to the threshold voltages V ₁ and V ₂
Because the window comparator can output a pulse when it is between

That is, with the configuration of FIG. 1, it is possible to realize a transmission rate detection circuit capable of detecting the transmission rate corresponding to the maximum transmission rate even if the element cannot adapt to the maximum transmission rate.

Therefore, the transmission speed detection circuit can be realized by an inexpensive process, and the bias current of the elements constituting the transmission speed detection circuit can be suppressed to a small value. Can be.

The output level of the low-pass filter is low,
When the setting of the threshold voltage V ₁ and the threshold voltage V ₂ is difficult,
An amplifier may be inserted between the low-pass filter and the window comparator.

FIG. 3 shows a second embodiment of the transmission rate detecting circuit according to the present invention.

In FIG. 3, reference numeral 54 denotes a delay circuit for giving a predetermined delay to the output of the identification circuit; 55, an inverter for inverting the logic level of the output of the delay circuit 54; An AND circuit 52 for generating a pulse having a width corresponding to the output phase difference, and an average value detection circuit 52 for detecting an average value of a signal including a pulse output from the AND circuit 56.

Reference numeral 53-1 denotes a first comparator for judging a DC level output from the average value detection circuit 52 with a predetermined threshold value and converting the DC level into digital values "0" and "1".
2 is a second comparator that determines the level of the DC output from the average value detection circuit 52 with a threshold different from that of the first comparator 53-1 and converts it into digital values “0” and “1”;
53-11 is a power supply for supplying a threshold voltage to the first comparator 53-1, and 53-21 is a power supply for supplying the second comparator 53-1.
Power supply for supplying a threshold voltage to the first comparator 5
3-1, second comparator 53-2, power supply 53-11
And a power supply 53-21 to form a window comparator. Here, the voltage of the power supply 53-11 is set to V ₃ ,
The voltage of the power supply 53-21 and V _4, keep the convenience V _3> V _4.

The transmission speed detecting circuit 5a of the present invention is constituted by the above-mentioned components.

FIG. 4 is a diagram for explaining the operation of the configuration of FIG. Hereinafter, the first embodiment of the transmission rate detection circuit of the present invention will be described in detail with reference to FIG. 4 while also referring to FIG.

In FIG. 4, (1) is the output of the identification circuit. Also here, a signal whose logic level alternates between "0" and "1" (a code of logic level "1" in the case of an RZ signal, and a code of logic level "0" in the case of an NRZ code). (This is a signal that alternately repeats the sign of “1.”), but this is merely an example for explanation.

When the output of the discriminating circuit passes through the delay circuit 54 and the inverter 55 in FIG. 3, the logic level is inverted by the delay of the delay circuit. This is shown in (2).

Since the AND circuit 56 performs an AND operation on the output of the identification circuit and the output of the inverter 55, a pulse is output from the AND circuit 56 when both waveforms are at the logical level "1". It is output at the rising edge of the output of the identification circuit.

Since the number of rising portions in the output of the identification circuit is proportional to the transmission speed, the number of pulses output from the AND circuit 56 is higher when the transmission speed is higher than when the transmission speed is lower. This is shown in (3).

Therefore, the average voltage of the output of the AND circuit 56 is higher when the transmission speed is high than when the transmission speed is low. This is shown in (4). In this case, the average value voltage when the transmission speed is faster is higher than V _3, the average value voltage when the transmission rate is slow is assumed higher than V ₄ lower than V _3.

Therefore, when the transmission speed is high, there is a range in which both the first comparator and the second comparator output the logical level "1". On the other hand, when the transmission speed decreases, the first comparator outputs a logical level “0”,
There is a range where the second comparator outputs a logic level “1”. Although not shown in FIG. 4, there is a range in which both the first comparator and the second comparator output a logical level “0” when the transmission speed further decreases.

That is, the transmission speed detection circuit 5a having the configuration shown in FIG.
This makes it possible to distinguish and detect the three transmission speeds.

Then, the transmission speed detecting circuit 5 having the configuration of FIG.
If a is used instead of the transmission speed detection circuit 5c having the configuration of FIG. 8, the output itself of the voltage controlled oscillation circuit 72 of FIG.
Either the output of the first frequency dividing circuit 61 or the output of the second frequency dividing circuit 62 can be selected.

In FIG. 4, the output waveform of the inverter is drawn so as not to be too sharp. However, in the configuration of FIG. 3, the output of the discrimination circuit and the signal of the logic inverted by delaying the output of the discrimination circuit are shown. If the threshold value of the AND circuit that generates a pulse indicating the phase difference between the two by the AND operation is designed to be lower than usual, even if the delay circuit, the inverter, and the AND circuit cannot support the maximum transmission rate, The above operation can be realized.

That is, with the configuration shown in FIG. 3, it is possible to realize a transmission rate detection circuit capable of detecting the transmission rate corresponding to the maximum transmission rate even if the element cannot adapt to the maximum transmission rate.

Therefore, the transmission speed detection circuit can be realized by an inexpensive process, and the bias current of the elements constituting the transmission speed detection circuit can be suppressed to a small value. Can be.

In FIG. 3, an example has been described in which an AND circuit is used to generate a pulse corresponding to the phase difference between the output of the identification circuit and the signal obtained by delaying and logically inverting the output of the identification circuit. A similar operation can be realized by using an exclusive OR circuit. However, it is necessary to design a circuit in consideration of the fact that the relationship between the phase difference and the pulse width is reversed between the case where an AND circuit is used and the case where an exclusive OR circuit is used.

FIG. 5 shows a third embodiment of the transmission rate detecting circuit according to the present invention. The average value detecting circuit and the first and second comparators in the second embodiment of the transmission rate detecting circuit according to the present invention. A logarithmic amplifier is inserted between the two.

In FIG. 5, reference numeral 54 denotes a delay circuit for giving a predetermined delay to the output of the identification circuit, 55 denotes an inverter for inverting the logic level of the output of the delay circuit 54, and 56 denotes an output of the identification circuit and the inverter 55. An AND circuit 52 for generating a pulse having a width corresponding to the phase difference of the output, an average value detecting circuit 52 for detecting an average value of a signal including a pulse output from the AND circuit 56, and an average value detecting circuit 57 52 is a logarithmic amplifier that performs logarithmic conversion of the DC voltage output from the power supply.

53-1 determines the level of the DC output from the logarithmic amplifier 57 with a predetermined threshold value to determine a digital value "0",
The first comparator 53-2, which converts the signal to "1", determines the DC level output from the logarithmic amplifier 57 with a threshold different from that of the first comparator 53-1 to obtain digital values "0" and "1". The second comparator for conversion, 53-
A power supply 11 supplies a threshold voltage to the first comparator 53-1. A power supply 53-21 supplies a threshold voltage to the second comparator 53-2.
A window comparator is constituted by the first and second comparators 53-2, the power supply 53-11, and the power supply 53-21. Here, the voltage of the power supply 53-11 V _3, the voltage of the power supply 53-21 and V _4, keep the convenience V _3> V _4.

The transmission speed detecting circuit 5b of the present invention is constituted by the above-mentioned components.

The configuration of FIG. 5 is characterized in that a logarithmic amplifier 57 is inserted in the configuration of FIG. 3, but the operation of detecting the transmission rate itself is essentially the same as that of FIG. Now, let us only describe the operation of the logarithmic amplifier 57 and the effect of inserting the logarithmic amplifier 57.

FIG. 6 shows an example of the configuration of a logarithmic amplifier.

In FIG. 6, 57-1 is a resistor, 57-2
Is an operational amplifier, 57-3 is a capacitor, 57-4 is a transistor, 57-5 is a transistor, 57-6 is a resistor,
57-7 is a resistor, 57-8 is a resistor, 57-9 is an operational amplifier, 57-10 is a capacitor, 57-11 is a resistor, 57
-12 is a power supply.

Then, one end of the resistor 57-1 is connected to a logarithmic amplifier.
Input voltage V_INAnd the operational amplifier 5
The output terminal 7-2 is used as the output terminal of the logarithmic amplifier.
Pressure V _OUTTake out.

The capacitors 57-3 and 57-10
Is for preventing oscillation of the operational amplifier 57-2 and the operational amplifier 57-9.

A normal operational amplifier is configured so that the input resistance is substantially infinite and the amplification is substantially infinite. Therefore, as shown in FIG.
If a ground potential is applied to the non-inverting input terminal of No. 2, the inverting input terminal becomes a virtual earth.

[0090] Since the inverted input terminal of the operational amplifier 57-2 is a virtual ground, the resistance value of the resistor 57-1 When R _1, flows V _IN / R ₁ becomes current in resistor 57-1.

Considering that the input resistance of the operational amplifier 57-2 is substantially infinite, the current flowing through the resistor 57-1 becomes equal to the collector current I _C4 of the transistor 57-4.

That is, I _C4 = V _IN / R ₁ (1) Similarly, the voltage of the power supply 57-12 is set to V _REF and the resistance 57
Assuming that the resistance value of −11 is R ₁₁ , the transistor 57-5
Of the collector current I _C5 becomes I _C5 = V _REF / R ₁₁ (2).

The base of the transistor 57-4 is connected to the ground.
The base of transistor 57-4.
Voltage between transmitters is V_BEAnd the base of the transistor 57-5.
The emitter-to-emitter voltage to V_BE5Then, transistor 5
The base voltage of 7-5 is (−V _BE4+ V_BE5).

[0094] The base voltage of the transistor 57-5 is a resistor 57-7 output voltage V _OUT (the resistance value is R _7.) And 57-8 to divided voltage in (a resistance value. And R ₈₎ Since they are equal, -V _BE4 + V _BE5 = V _OUT (R ₈ / (R ₇ + R ₈ )) (3) is obtained.

On the other hand, as is well known, the collector current I _{C of the} transistor and the base-emitter voltage V _BE
Is given by: I _C = C · e ((q / kT) V _BE ) (4) Where C is a constant specific to the transistor,
q is the charge of the electron, k is the Boltzmann constant, T is the absolute temperature, e is a number called the base or base of the natural logarithm, and e ≒
2.71828.

[0096] (4) is solved for V _BE of formula to obtain a _{V BE = (kT / q)} ln (I C / C) (5). Here, ln is a natural logarithm.

Applying the relationship of equation (5) to the left side of equation (3), assuming that the constant C unique to the transistor and the base-emitter voltage V _BE of the transistor are constant regardless of the transistor, kT / q = If the resistance values of the resistors 57-7 and 57-8 are selected so that (R ₇ + R ₈ ) / R ₈ (6), V _OUT = −ln (V _IN / V _REF ) (7) It can be seen that the configuration of No. 6 is a logarithmic amplifier.

It should be noted that, although different from the essence of the present invention,
Note that the configuration of the logarithmic amplifier is not limited to that shown in FIG.

FIG. 7 is a diagram for explaining the effect of using a logarithmic amplifier.

FIG. 7A is a diagram showing the output voltage of the average value detection circuit with respect to the transmission speed. As already described repeatedly, the output voltage of the average value detection circuit is proportional to the transmission speed, and therefore becomes linear with respect to the transmission speed.

FIG. 7B is a diagram showing the output voltage of the logarithmic amplifier with respect to the input voltage of the logarithmic amplifier. The output voltage of the average value detection circuit, which is the input voltage of the logarithmic amplifier, is proportional to the transmission speed. Considering this, FIG. 7B may be considered to be the output voltage of the logarithmic amplifier with respect to the transmission speed.

[0102] Now, the transmission rate output voltage of the logarithmic amplifier becomes 0 F ₀ (this point is that the voltage V _REF of the power supply 57-12 of Figure 6 is applied as an input voltage to the logarithmic amplifier.) When, (7) in the logarithmic amplifier having the characteristic, the output voltage is about 0.3 volts higher whenever the transmission rate is 1/2 of the F _0, every time the transmission rate is twice the F ₀ The output voltage is reduced by 0.3 volts.

That is, each time the transmission speed doubles, the output voltage of the logarithmic amplifier changes by a constant voltage.

On the other hand, the output voltage of the average value detection circuit is proportional to the transmission speed. Therefore, when the transmission speed is 4F ₀ and 2F ₀
Assuming that the difference between the output voltages of the average value detection circuit at the time of (3) is 0.3 volts, the average value detection at the transmission speed of (と) F ₀ and the transmission speed of (１ ／) F ₀ The difference between the output voltages of the circuit is (1/8) .times.0.3 volts, or about 38 millivolts.

That is, in order to detect the transmission speed by the output voltage itself of the average value detection circuit, the sensitivity of the comparator must be high and the threshold voltage supplied to the comparator must be controlled with high accuracy. I understand.

In practice, the transmission speed in a practical system is 15
0 Mb / s, 600 Mb / s, 2.4 Gb / s, 10 G
Like b / s, it changes in steps of about four times.

In this case, if a logarithmic amplifier having the characteristics shown in FIG. 7B is used, the threshold voltage may be set within a voltage width of about 0.6 volt.

On the other hand, in order to detect the transmission speed based on the output of the average value detection circuit, 10 Gb / s and 2.4 Gb / s
Assuming that the output voltage difference of the average value detection circuit at s is 0.6 volts, the output voltage difference of the average value detection circuit at 150 Mb / s and 600 Mb / s is 0.6 × (４) ³ volts, that is, about This is as low as 9 millivolts. It is not easy to stably detect the transmission speed by setting the threshold voltage between these 9 millivolts.

Conversely, when the output voltage difference between the average value detection circuit at 150 Mb / s and 600 Mb / s is set to 0.6 volt, the output of the average value detection circuit between 10 Gb / s and 2.4 Gb / s is set. The voltage difference is about 38 volts, which is not a voltage applicable to a normal semiconductor integrated circuit.

Therefore, the effect of providing the logarithmic amplifier on the output side of the average value detection circuit as in the configuration of FIG. 5 is very large.

In the configuration shown in FIG. 5, an example has been described in which a logarithmic amplifier is inserted in the transmission speed detection circuit having the configuration shown in FIG. 3. However, it is needless to say that the transmission speed detection circuit having the configuration shown in FIG. Even if an amplifier is inserted, exactly the same operation can be realized.

[0112]

According to the first means of the present invention, the average value of a digital signal that identifies a received signal is obtained, and the number of pulses generated when the average value is within a predetermined level range is determined by the transmission speed. , And the average value of the signal containing the pulse is also proportional to the transmission rate, so that the transmission rate can be detected.
Then, it becomes possible to select a clock having a frequency corresponding to the transmission speed by a signal obtained by digitally converting the average value of the signal including the pulse.

Further, since the pulse is output when the average value of the digital signal identifying the received signal is within the predetermined level range, the transmission rate detecting circuit can be constituted by a circuit which cannot necessarily cope with the maximum transmission rate. Become.

According to the second means of the present invention, the number of pulses corresponding to the phase difference between the digital signal obtained by discriminating the received signal and the signal obtained by delaying and logically inverting the digital signal is proportional to the transmission speed. However, since the average value of the signal including the pulse is also proportional to the transmission speed, the transmission speed can be detected. Then, it becomes possible to select a clock having a frequency corresponding to the transmission speed of the received signal by a signal obtained by digitally converting the average value of the signal including the pulse.

In addition, the phase of the digital signal obtained by identifying the received signal and the phase of the signal obtained by delaying and logically inverting the digital signal are compared, and the output of the identification circuit and the signal obtained by delaying the output of the identification circuit and inverting the logic are output. Since a pulse corresponding to the phase difference is generated, it is possible to configure a transmission rate detection circuit even with a circuit that cannot necessarily support the maximum transmission rate.

According to the third means of the present invention, since the average value of the signal including the pulse is logarithmically converted, the change in the output level of the logarithmic amplifier with respect to the change in the transmission rate is made constant over a wide range of the transmission rate. This can facilitate the digital conversion of the output level of the logarithmic amplifier.

Further, the transmission rate detecting circuit can be constituted by a circuit which cannot necessarily cope with the maximum transmission rate, similarly to the first means of the present invention and the second means of the present invention.

According to the fourth means of the present invention, a transmission rate detection circuit formed by an inexpensive process and capable of detecting the transmission rate even if it cannot handle the maximum transmission rate is applied. Thus, the cost of the optical receiver can be reduced and the power consumption can be reduced gradually.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a transmission rate detection circuit according to the present invention.

FIG. 2 is a view for explaining the operation of the configuration of FIG. 1;

FIG. 3 is a second embodiment of the transmission rate detection circuit of the present invention.

FIG. 4 is a view for explaining the operation of the configuration of FIG. 3;

FIG. 5 shows a third embodiment of the transmission rate detection circuit of the present invention.

FIG. 6 is a configuration example of a logarithmic amplifier.

FIG. 7 is a diagram illustrating the effect of using a logarithmic amplifier.

FIG. 8 shows an optical receiving apparatus to which a conventional transmission rate detecting circuit is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Optical-electrical conversion circuit 2 Preamplifier circuit 3 Main amplifier circuit 4 Identification circuit 5 Transmission speed detection circuit 5a Transmission speed detection circuit 5b Transmission speed detection circuit 5c Transmission speed detection circuit 6 Clock selection circuit 7 Phase lock loop circuit 8 Flip・ Flop 50 Low-pass filter 51 Window comparator 51-11 Power supply 51-12 Power supply 52 Average value detection circuit 53-1 First comparator 53-2 Second comparator 53-11 Power supply 53-21 Power supply 54 Delay Circuit 55 Inverter 56 Logical product circuit 57 Logarithmic amplifier 57-1 Resistance 57-2 Operational amplifier 57-3 Capacitor 57-4 Transistor 57-5 Transistor 57-6 Resistance 57-7 Resistance 57-8 Resistance 57-9 Operational amplifier 57- 10 Capacitor 57-11 Resistance 57-12 Power supply 58 Cow Counter 59 logic comparison circuit 60 decoder 61 first frequency divider circuit 62 second frequency divider circuit 63 logical product circuit 64 logical product circuit 65 logical product circuit 66 logical sum circuit 70 phase comparator circuit 71 low-pass filter 72 voltage Control oscillation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat 参考 (Reference) H04B 10/06 H04L 7/02 (72) Inventor Tetsuya Yamada 4-chome, Kita-Nanajo-Nishi 3-chome, Kita-ku, Sapporo, Hokkaido 1 F-term in Fujitsu Hokkaido Digital Technology Co., Ltd. (reference) 5K002 AA04 DA05 FA01 5K029 AA18 CC04 HH09 HH27 LL01 LL08 5K047 AA15 BB02 GG07 KK01 MM33 MM36 MM45

Claims (4)

[Claims] 1. A digital output that identifies a received signal is applied to a low-pass filter, and a pulse is output when an output level of the low-pass filter is within a predetermined level range. A transmission speed detecting circuit for detecting an average value level of a signal and digitally converting the average value level. 2. A pulse corresponding to a phase difference between a digital output that has identified a received signal and a signal obtained by delaying and logically inverting the digital output is output, and an average value level of a signal including the pulse is detected. A transmission speed detection circuit for converting the average value level into a digital signal. 3. The transmission rate detection circuit according to claim 1, wherein after detecting an average value level of the signal including the pulse,
A transmission rate detection circuit for converting a signal obtained by logarithmically amplifying the average level into a digital signal. 4. An optical receiving apparatus that converts a received optical signal into an electric signal, identifies a received signal after a predetermined amplification, and reproduces and outputs the identified digital output by a clock. The transmission rate detecting circuit according to any one of claims 1 to 3, detects the transmission rate of the received signal, selects a clock corresponding to the detected transmission rate, and reproduces the identified received signal. An optical receiving device, comprising: