JP2001186015A - Phase synchronization system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional phase synchronization system, that the output of a phase comparison section is not constant due to an initial unstable phase because a synchronization clock generating section 2 is not controlled resulting that a reference clock A of a reference clock generating section 1 and a synchronous clock E of the synchronous clock generating section 2 are asynchronous in operation at start of a power supply and at recovery of a defect of an input clock. SOLUTION: The phase synchronization system is provided with a power supply start detection section 7 that detects the start of a power supply, an input clock fault recovery detection section 6 that detects fault recovery of an input clock CK 1, and a change point detection section 8 that receives a control signal B from the power supply start detection section 7, a control signal C from the input clock fault recovery detection section 6 and a reference clock A to supply a timing signal D to the synchronization clock generating section 2 and phase-locks an output clock CK 2 to the input clock CK 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization system for synchronizing the phase of an output clock of a voltage controlled oscillator with the phase of an input clock. And a phase synchronization system for synchronizing with the phase of

[0002]

2. Description of the Related Art Conventionally, in a method of synchronizing a phase with an input clock, in order to generate a stable synchronized clock, a phase comparison result of an input / output clock is converted into a voltage, smoothed by a filter, and then subjected to voltage control. A method of controlling the crystal oscillator to establish frequency synchronization and phase synchronization has been adopted.

FIG. 3 shows a block diagram of a conventional phase synchronization system. 3, 1 is a reference clock generator, 2 is a synchronous clock generator, 3 is a phase comparator, 4 is a filter, 5
Is a voltage controlled crystal oscillator. Reference clock generator 1
Generates a reference clock A based on the input clock CK1. The reference clock A from the reference clock generation unit 1 is supplied to one input terminal of the phase comparison unit 3.
Is supplied with a synchronous clock E from a synchronous clock generator.

The phase comparator 3 outputs a phase error signal having a duty corresponding to the phase difference between the reference clock A and the synchronous clock E. This phase error signal is output to the filter 4. The filter 4 generates a voltage signal proportional to the phase difference between the reference clock A and the synchronization clock E by smoothing the phase error signal. This voltage signal is supplied to the voltage controlled crystal oscillator 5, which generates and sends out the output clock CK2. The output clock CK2 is also supplied to the synchronous clock generator 2, and a feedback control loop is formed. By forming this feedback control loop, the phase of the output clock CK2 can be synchronized with the phase of the input clock CK1.

[0005]

In the conventional system configured as described above, since the synchronous clock generating unit 2 is not controlled, the reference clock generating unit 1 and the synchronous clock are not connected when the power is turned on and when the input clock failure is recovered. Since the generator 2 operates asynchronously, the initial phase is indefinite and the output of the phase comparator 3 is not constant. Further, when the reference clock A and the synchronous clock E rise at the worst phase (the opposite phase or a phase close to the opposite phase), it takes time to establish the phase synchronization. However, there is a problem in that a communication device or the like adopting the method takes a long time until phase synchronization is established, and it has been a problem to shorten the time until phase synchronization is established.

[0006]

According to a first aspect of the present invention, there is provided a phase synchronization system, comprising: a reference clock generator for receiving an input clock and generating a reference clock; and comparing a phase between the reference clock and the synchronization clock. A phase comparison unit to perform,
A filter supplied with the output voltage of the phase comparison unit, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generation unit that receives the output clock and generates the synchronous clock. A phase synchronization system for synchronizing the input clock and the output clock, wherein the synchronous clock generation unit is controlled by a signal that detects power-on and a signal that detects failure recovery of the input clock. Detecting a change point of the reference clock, and matching the fall point of the synchronous clock with the change point, shortens the time for establishing phase synchronization at the time of power-on and recovery of an input clock failure. .

According to a second aspect of the present invention, there is provided a phase synchronization system, comprising: a reference clock generator for receiving an input clock and generating a reference clock; and a phase comparator for comparing the phase of the reference clock with the synchronization clock. A filter supplied with the output voltage of the phase comparator, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock A power-on detection section for detecting a start-up of a power supply, and an input-clock failure recovery detection for detecting a recovery of a failure of the input clock. A control signal from the power-on detection section, a control signal from the input clock failure recovery detection section, and the reference clock. Enter a change point detecting unit for supplying a timing signal to the synchronization clock generating unit, and characterized in that the phase synchronizing the output clock to the input clock.

Further, according to a third aspect of the present invention, in the phase synchronization system, a reference clock generator for receiving an input clock and generating a reference clock, and a phase comparator for comparing the phases of the reference clock and the synchronous clock are provided. A filter supplied with the output voltage of the phase comparator, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock And a phase synchronization system for phase-synchronizing the input clock and the output clock including a power-supply start detection unit that detects the start of power, a control signal from the power-supply start detection unit, and the reference clock. And a change point detection unit for supplying a timing signal to the synchronous clock generation unit, and the output clock is supplied to the input clock. The click, characterized in that to phase synchronization.

Further, in a phase synchronization system according to a fourth aspect of the present invention, a reference clock generator for receiving an input clock and generating a reference clock, and a phase comparator for comparing the phases of the reference clock and the synchronization clock. A filter supplied with the output voltage of the phase comparator, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock A phase synchronization system for synchronizing the input clock and the output clock, the input clock failure recovery detection unit branching the input clock and detecting the recovery of the input clock failure, and the input clock failure A control signal from a recovery detection unit and the reference clock are input and a timing signal is supplied to the synchronous clock generation unit. And a change point detecting unit for supplying, characterized in that for phase synchronizing the output clock to the input clock.

The phase synchronization system according to a fifth aspect of the present invention is the phase synchronization system according to the second, third, or fourth aspect, wherein the phase comparison section, the filter, the voltage controlled oscillator, and the synchronization clock are provided. A timing signal output from the change point detection unit is supplied to a feedback control loop formed by the generation unit.

Further, in the phase synchronization system according to the present invention, a reference clock generator for receiving an input clock and generating a reference clock, and a phase comparator for comparing the phase of the reference clock with the synchronization clock A filter supplied with the output voltage of the phase comparator, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock And a phase synchronization system for phase-synchronizing the input clock and the output clock including a power-supply start detection unit that detects the start of power, a control signal from the power-supply start detection unit, and the reference clock. And a change point detecting section for supplying a timing signal to the synchronous clock generating section for inputting the control signal. In accordance with the change point of the reference clock to generate the timing signal, and generates the synchronous clock in accordance with the said timing signal, characterized in that to the output clock phase-synchronized with the input clock.

Further, according to a seventh aspect of the present invention, in the phase synchronization system, a reference clock generator for receiving an input clock and generating a reference clock, and a phase comparator for comparing the phases of the reference clock and the synchronization clock. A filter supplied with the output voltage of the phase comparator, a voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock A phase synchronization system for synchronizing the input clock and the output clock, the input clock failure recovery detecting unit for branching the input clock and detecting the recovery of the input clock failure; A control signal from a recovery detection unit and the reference clock are input and a timing signal is supplied to the synchronous clock generation unit. A change point detection unit for supplying, and after the control signal rises, generates the timing signal in accordance with a change point of the reference clock, generates the synchronization clock in accordance with the timing signal, and The phase of the output clock is synchronized with a clock.

Further, in the phase synchronization system according to the present invention according to an eighth aspect of the present invention, the change point of the reference clock according to the first, sixth and seventh aspects is a falling point of the reference clock. I do.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an input clock CK1.
In the phase synchronization method for synchronizing the phases, the reference clock A and the synchronization clock E are likely to rise at the worst phase (the opposite phase or a phase close to the opposite phase) at the time of power supply startup and at the time of input clock failure recovery. This is a method of detecting the power-on and recovery of the input clock failure, and controlling the synchronous clock generation unit 2 that generates the synchronous clock E, thereby shortening the phase synchronization establishment time of the output clock CK2.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the present invention. In FIG. 1, the difference from FIG. 3 which is a block diagram of the conventional synchronous system is that an input clock failure recovery detecting unit 6, a power activation detecting unit 7, and a change point detecting unit 8 are additionally provided. .

The reference clock generator 1 receives the input clock CK
A reference clock A having a phase comparison frequency is generated from 1. The synchronous clock generator 2 is controlled by the timing signal D from the change point detector 8 so that the initial phase becomes constant. Based on the output clock CK2 from the voltage controlled crystal oscillator 5, the synchronous clock E of the phase comparison frequency is used. Generate

The phase comparator 3 inputs the reference clock A generated by the reference clock generator 1 to one input terminal, and inputs the synchronous clock E generated by the synchronous clock generator 2 to the other input terminal, The comparison is performed, and a phase error signal having a duty corresponding to the phase difference between the reference clock A and the synchronization clock E is output. This phase comparison unit 3 can be realized by an exclusive OR circuit or the like.

The filter 4 smoothes the phase error signal from the phase comparator 3 to generate a voltage signal proportional to the phase difference between the reference clock A and the synchronization clock E. The voltage controlled crystal oscillator 5 receives the voltage signal from the filter 4 and generates an output clock CK2. As the voltage controlled crystal oscillator 5, for example, a voltage controlled oscillator can be used instead of the voltage controlled crystal oscillator.

The input clock failure recovery detecting section 6 receives the input clock CK branched at the input terminal of the reference clock generating section 1.
1 to detect that the input clock CK1 has recovered from the fault, and output the control signal C. Power activation detection unit 7
Detects that the power supply has been started (power-on) and outputs a control signal B.

The change point detector 8 receives the control signal B from the power supply start detector 7 and the control signal C from the input clock failure recovery detector 6 and generates a reference clock when the power supply is started and when the input clock failure is recovered. A change point (a rising point and a falling point, in this case, a falling point) of the reference clock A from the unit 1 is detected, and a timing signal D is output. In addition, in the block diagram shown in FIG. 1, it functions even when there is no input clock failure recovery detecting unit 6, and functions even when there is no power-on detecting unit 7.

Next, regarding the operation of the embodiment of the present invention, a block diagram of the embodiment of the phase synchronization system according to the present invention shown in FIG. 1 and the operation of the embodiment of the phase synchronization system according to the present invention shown in FIG. This will be described with reference to a timing chart.

The timing charts (1) to (1) shown in FIG.
(4) is a timing chart showing the operation at power-on. Reference clock generator 1 based on input clock CK1
Generates the reference clock A (FIG. 2 (1)) before the control signal B (FIG. 2 (2)) rises at time t1.
The pattern shown in (1) is shown. Power activation detection unit 7
Outputs a control signal B (FIG. 2 (2)) which rises at time t1 upon detecting the activation of the power supply.

The change point detecting section 8 changes the point (rising point) of the reference clock A (FIG. 2 (1)) from the reference clock generating section 1 only while the control signal B from the power supply start detecting section 7 is being input. The falling point is detected at time t2, and the timing signal D (FIG.
(3)) is generated and sent to the synchronous clock generator 2.
The synchronous clock generator 2 makes the initial phase of the synchronous clock E (FIG. 2 (4)) constant by the timing signal D from the change point detector 8, and generates the reference clock A (FIG. 2) generated by the reference clock generator 1. (1)) with respect to time t3, t4
Synchronous clock E whose edge (falling point) matches
(FIG. 2 (4)) is sent to the phase comparator 3. Similarly, after time t4, the synchronous clock E whose edge (falling point) matches the reference clock A (FIG. 2 (1)).
(FIG. 2 (4)) is sent to the phase comparator 3.

The phase comparator 3 includes a reference clock generator 1
2 (1) is input to one input terminal, and a synchronous clock E (FIG. 2 (4)) from the synchronous clock generator 2 whose edge (falling point) matches the reference clock A (FIG. 2 (1)).
To the other input terminal. Since the phases of the reference clock A and the synchronous clock E are compared, the phase comparison result becomes a value close to the phase coincidence state, and the result is sent to the filter 4 as a phase error signal. The filter 4 sends a voltage signal proportional to the phase error signal to the voltage controlled crystal oscillator 5. The voltage controlled crystal oscillator 5 outputs an output clock CK2 according to the voltage signal from the filter 4. At the same time, the output clock CK2 is branched and supplied to the synchronous clock generator 2 to establish phase synchronization. Phase comparator 3 and filter 4
The voltage control crystal oscillator 5 and the synchronous clock generator 2 form a feedback control loop.

(5) to (5) of the timing chart shown in FIG.
(8) is a timing chart showing the operation at the time of recovery from the input clock failure. When the input clock CK1 recovers at time T1, the reference clock A generated by the reference clock generator 1 based on the input clock CK1 (FIG. 2 (5))
Also rises at time T1. When detecting that the input clock CK1 has recovered from the failure, the input clock failure recovery detector 6 detects a control signal C (FIG. 2) which rises at time T1.
(6)) is output.

The change point detector 8 receives the reference clock A from the reference clock generator 1 only while the control signal C (FIG. 2 (6)) from the input clock failure recovery detector 6 is being input.
((5)) change points (there is a rising point and a falling point, in this case, a falling point) are defined as times T2 and T2.
3, detected at T4, generates a timing signal D (FIG. 2 (7)), and sends it to the synchronous clock generator 2. The synchronous clock generator 2 receives the timing signal D from the change point detector 8
The initial phase of the synchronous clock E (FIG. 2 (8)) outputted by the reference clock A is constant, and the time T2, T3,
At T4, the synchronous clock E (FIG. 2 (8)) having the matching edge (falling point) is sent to the phase comparator 3. Time T4
At the subsequent falling points, the reference clock A
The synchronous clock E (FIG. 2 (8)) whose edge (falling point) matches (FIG. 2 (5)) is sent to the phase comparator 3.

The phase comparator 3 includes a reference clock generator 1
The reference clock A (FIG. 2 (1)) from the synchronous clock E (FIG. 2 (4)) from the synchronous clock generator 2 whose edge (falling point) matches the reference clock A (FIG. 2 (1)).
To the other input terminal. Since the phases of the reference clock A and the synchronous clock E are compared, the phase comparison result becomes a value close to the phase coincidence state, and the result is sent to the filter 4 as a phase error signal. The filter 4 sends a voltage signal proportional to the phase error signal to the voltage controlled crystal oscillator 5. The voltage controlled crystal oscillator 5 outputs an output clock CK2 according to the voltage signal from the filter 4. At the same time, the output clock CK2 is branched and supplied also to the synchronous clock generator 2, and phase synchronization is established. A feedback control loop is formed by the phase comparison unit 3, the filter 4, the voltage controlled crystal oscillator 5, and the synchronous clock generation unit 2.

[0028]

As described above, in the phase synchronization system according to the present invention, the initial phase of the synchronous clock is maintained at the reference clock even when the power is turned on and when the input clock failure is recovered by the configuration for controlling the synchronous clock generator. Rises at a constant phase, the time required to establish phase synchronization can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a phase synchronization system according to the present invention.

FIG. 2 is an operation timing chart showing the operation of the embodiment of the phase synchronization system according to the present invention. Fig. 2 (1)-
(4) is a timing chart when the power is turned on. FIG.
(5) to (8) are operation timing charts at the time of recovery from an input clock failure.

FIG. 3 is a block diagram showing a configuration of a conventional phase synchronization system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference clock generation part 2 Synchronous clock generation part 3 Phase comparison part 4 Filter 5 Voltage control crystal oscillator 6 Input clock failure recovery detection part 7 Power supply start detection part 8 Change point detection part CK1 Input clock CK2 Output clock A Reference clock B, C Control signal D Timing signal E Synchronous clock

Claims (8)

[Claims] 1. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phases of the reference clock and a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. A phase synchronization method for synchronizing, wherein the synchronous clock generation unit is controlled by a signal that detects the start of a power supply and a signal that detects failure recovery of the input clock, and detects a change point of the reference clock,
A phase synchronizing method characterized by shortening the time for establishing phase synchronization at the time of power-on and recovery from an input clock failure by adjusting the falling point of the synchronous clock to this change point. 2. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phase of the reference clock with a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. A phase synchronization method for synchronizing, comprising: a power-on detection section for detecting power-on activation; an input-clock failure recovery detection section for detecting recovery of the input clock failure; a control signal from the power-on detection section; A control signal from a clock failure recovery detection unit and the reference clock are input to provide a timing signal to the synchronous clock generation unit. And a change point detecting section for supplying the output clock, and the output clock is phase-synchronized with the input clock. 3. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phase of the reference clock with a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. A phase synchronization method for synchronizing, wherein a power activation detection unit for detecting activation of a power, a control signal from the power activation detection unit, and the reference clock are input and a timing signal is supplied to the synchronous clock generation unit. A phase synchronization system, comprising: a change point detection unit, wherein the output clock is phase-synchronized with the input clock. 4. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phase of the reference clock with a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. An input clock failure recovery detection unit that synchronizes with the phase synchronization system, and detects input clock failure recovery by branching the input clock.
A change point detector that inputs a control signal from the input clock failure recovery detector and the reference clock and supplies a timing signal to the synchronous clock generator, and synchronizes the output clock with the input clock in phase A phase synchronization system characterized by the above. 5. A timing signal output from the change point detection section is supplied to a feedback control loop formed by the phase comparison section, the filter, the voltage controlled oscillator, and the synchronous clock generation section. Item 2,
3. The phase synchronization method according to 3, 4. 6. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phase of the reference clock with a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. A phase synchronization method for synchronizing, wherein a power activation detection unit for detecting activation of a power, a control signal from the power activation detection unit, and the reference clock are input and a timing signal is supplied to the synchronous clock generation unit. A change point detection unit, wherein the timing signal is adjusted in accordance with a change point of the reference clock after the control signal rises. Wherein the synchronous clock is generated in accordance with the timing signal, and the output clock is phase-synchronized with the input clock. 7. A reference clock generator for receiving an input clock and generating a reference clock, a phase comparator for comparing the phase of the reference clock with a synchronous clock, and a filter supplied with an output voltage of the phase comparator. A voltage-controlled oscillator that generates an output clock using the output of the filter as a control voltage, and a synchronous clock generator that receives the output clock and generates the synchronous clock, and controls the phase of the input clock and the output clock. An input clock failure recovery detection unit that synchronizes with the phase synchronization system, and detects input clock failure recovery by branching the input clock.
A change point detection unit that receives a control signal from the input clock failure recovery detection unit and the reference clock and supplies a timing signal to the synchronous clock generation unit; Wherein the timing signal is generated in accordance with a change point of the first clock signal, the synchronization clock is generated in accordance with the timing signal, and the output clock is phase-synchronized with the input clock. 8. The phase synchronization method according to claim 1, wherein the changing point of the reference clock is a falling point of the reference clock.