JP2001185957A - Power amplifier, method for controlling power of power amplifier, and communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a power amplifier which does not become worse in efficiency even when a CDMA system is adopted. SOLUTION: The power amplifier is equipped with an input terminal 101, an output terminal 107, N amplifying circuits 1010 which are connected sequentially between the input terminal 101 and output terminal 107 and can be bypassed, an impedance converting circuit 106 which is connected between the amplifying circuit 1010 of the final stage and the output terminal 107, and a bias control circuit 100 which control the amplifying circuit 1010. The amplifying circuit 1010 is composed of high-frequency switch circuits 102 and 103 and amplifiers 103 and 105 connected thereto, and the bias control circuit 100 control the source voltage of the amplifiers 103 and 105 and also controls the high-frequency switch circuit 102 and 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier used mainly in mobile communication, a control method therefor, and a communication device.

[0002]

2. Description of the Related Art In recent years, digital mobile communication has been rapidly spread, and development of miniaturization and low power consumption of terminals has been progressing. In addition, following the current digital mobile phone, CDMA (Code Division M
The development of mobile phones that use the ultiple access method is also progressing. CDMA is described in “CDMA System and Next-Generation Mobile Communication System” (Trikes Series; Chapter 1), and therefore detailed description is omitted.

A conventional power amplifier will be described below with reference to FIGS. FIG. 13 is a block diagram of a conventional power amplifier. In FIG. 13, reference numeral 701 denotes an input terminal;
Denotes a front-stage amplifier, 703 denotes a rear-stage amplifier, and 704 denotes an output terminal.

FIG. 14 is a graph showing current consumption, distortion, and efficiency with respect to output power of a conventional power amplifier.
In FIG. 14, the solid line represents the change in the characteristics when the initial current is set to be equal to the set value of the power amplifier for the conventional TDMA digital mobile phone. This is the characteristic when set to.

In general, the power amplifier is adjusted so that the efficiency at the maximum output is maximized. However, in the CDMA system, the output power is controlled over a wide dynamic range exceeding 70 dB from the maximum output according to the distance from the base station. Therefore, it is required to increase the efficiency of all output powers.

However, as shown in FIG. 14, when the initial current is on the order of TDMA, the power consumption at the time of low output is large, and the efficiency is deteriorated. Conversely, when the initial current is halved, the amount of distortion near the maximum output deteriorates. Therefore, the power amplifier needs to be set to the initial current that is the smallest within a range where the amount of distortion is allowable.

[0007]

However, in such a configuration, when the output power of the power amplifier is reduced, the efficiency is deteriorated, and unnecessary current is actually consumed. In particular, in the CDMA system, when transmitting at a reduced output is longer than when transmitting at the maximum output power, the battery is drastically consumed and the telephone talk time is shortened. I will.

[0008] Further, when the initial current is brought close to the class B (when the initial current is reduced) in order to improve the efficiency when the output power is reduced, the distortion is deteriorated. There was a limit.

An object of the present invention is to provide a power amplifier in which the efficiency does not deteriorate even in the CDMA system and a control method therefor, in consideration of such problems of the conventional power amplifier.

[0010]

In order to solve the above-mentioned problems, the present invention provides an input terminal, an output terminal, and a direct or indirect connection between an input terminal and an output terminal. , N bypassable amplifier circuits, an impedance conversion circuit directly or indirectly connected between the final-stage amplifier circuit and the output terminal, and a bias control circuit for controlling the amplifier circuit. The amplification circuit is a circuit including a high-frequency switch circuit and an amplifier directly or indirectly connected thereto, the bias control circuit controls a power supply voltage of the amplifier, and the high-frequency switch circuit Has the configuration of a power amplifier that controls

Further, the present invention provides an input terminal, a first high-frequency switch circuit capable of outputting a signal input to the input terminal while switching the signal to two output terminals, and one output of the first high-frequency switch circuit. A first amplifier directly or indirectly connected to a terminal, an output terminal of the first amplifier and the other output terminal of the first high-frequency switch circuit directly or indirectly connected to each other, A second high-frequency switch circuit that can output two signals input from the second high-frequency switch circuit while independently switching to two output terminals, and a second high-frequency switch circuit directly or indirectly connected to one output terminal of the second high-frequency switch circuit. , An impedance conversion circuit directly or indirectly connected to the other output terminal of the second high-frequency switch circuit, and an output terminal of the second amplifier and the input terminal. An output terminal connected directly or indirectly to an output terminal of the inductance conversion circuit, a bias control circuit controlling a power supply voltage of the first amplifier and the second amplifier, and controlling the high-frequency switch circuit; A power amplifier comprising:

Also, the present invention provides an input terminal, a first high-frequency switch circuit capable of outputting a signal input to the input terminal while switching the signal to two output terminals, and one output of the first high-frequency switch circuit. A first amplifier directly or indirectly connected to a terminal, an output terminal of the first amplifier and the other output terminal of the first high-frequency switch circuit directly or indirectly connected to each other, A second high-frequency switch circuit that can output two signals input from the second high-frequency switch circuit while independently switching to two output terminals, and a second high-frequency switch circuit directly or indirectly connected to one output terminal of the second high-frequency switch circuit. And the output terminal of the second amplifier and the other output terminal of the second high-frequency switch circuit are directly or indirectly connected to each other and input from each output terminal. A third high-frequency switch circuit that can output while switching the signals independently to the two output terminals,
A third amplifier connected directly or indirectly to one output terminal of the third high-frequency switch circuit, and an impedance converter directly or indirectly connected to the other output terminal of the third high-frequency switch circuit A circuit, an output terminal of the third amplifier, an output terminal commonly or directly connected to an output terminal of the impedance conversion circuit, and the first amplifier, the second amplifier, and the third amplifier. And a bias control circuit for controlling the high-frequency switch circuit.

Further, the present invention provides an input terminal, a first high-frequency switch circuit capable of outputting a signal input to the input terminal while switching the signal to two output terminals, and one output terminal of the first high-frequency switch. A first amplifier directly or indirectly connected to the first amplifier, impedance switching means directly or indirectly connected to an output terminal of the first amplifier, and another output terminal of the first high-frequency switch circuit. A second high-frequency switch circuit that is directly or indirectly connected to the output terminal of the impedance switching means and that can output two signals input from the respective output terminals while independently switching to three output terminals; Connected directly or indirectly to the first output terminal of the high-frequency switch of
A second-stage amplifier connected directly or indirectly to a second output terminal of the second high-frequency switch, and a third-stage amplifier connected directly or indirectly to a third output terminal of the second high-frequency switch. An indirectly connected impedance conversion circuit, an output terminal directly or indirectly connected to the first and second final stage amplifiers and the impedance conversion circuit, and the first amplifier And the power supply voltages of the first and second final stage amplifiers, the on of the impedance switching means,
And a bias control circuit for controlling switching off and switching between the first and second high-frequency switch circuits.

The present invention also provides a power amplifier having at least two stages, a bypass circuit provided in parallel with the power amplifier, a high-frequency switch circuit connected to input / output terminals of the power amplifier and the bypass circuit, A power control method for a power amplifier including a bias control circuit,
The high-frequency switch circuit switches the power amplifier and the bypass circuit according to the output power of the entire amplifier,
A power control method for a power amplifier, wherein the bias control circuit shuts off a power supply of an unused power amplifier.

The present invention also provides any one of the above power amplifiers, an antenna, a receiving circuit, a signal processing circuit for processing a signal from the receiving circuit using the power amplifier, and a signal processing circuit. And a transmission circuit for transmitting a signal from the communication device.

With such a configuration, as the transmission power is reduced by the configuration of at least two stages of power amplifiers, the high power amplifier is bypassed by the high frequency switch, and the power supply of the bypassed amplifier is cut off to reduce the transmission power. When the transmission output is further reduced, the amplifier at the preceding stage is bypassed, and the power of the bypassed amplifier is cut off to improve the efficiency. By repeating this operation, it is possible to improve the efficiency over a wide dynamic range during transmission.

Thus, when the output power is reduced by the bypass circuit using the high-frequency switch, the final stage amplifier is bypassed, and the bias current of the final stage transistor is cut, so that the efficiency can be improved.

Further, the initial current of the amplifier itself at each stage can be reduced to improve the efficiency at the time of low output by operation close to class B. At that time, the distortion of the amplifier becomes large, by performing pre-distortion compensation using the transistor of the high-frequency switch in the bypass circuit, the initial current is small without increasing the circuit scale, and at the time of low output. It is possible to realize a power amplifier configured to cut off unnecessary current.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the power amplifier of the present invention will be described with reference to the drawings.

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a power amplifier according to the first embodiment. 100 is a bias control circuit, 101 is an input terminal, 102 is a first high-frequency switch circuit that switches one input to two outputs, 103 is a pre-amplifier, and 104 is a second high-frequency switch that switches two inputs independently to two outputs. High frequency switch circuit, 1
05 is a post-amplifier, 106 is a quarter wavelength line (impedance conversion circuit), and 107 is an output terminal. The amplifier circuit 1010 according to the present invention refers to a combination of the high-frequency switch circuit and an amplifier.

In the power amplifier of the present embodiment, when the maximum output power is required, the first high-frequency switch circuit 102 of FIG. 1 is connected from A to B, and the second switches C and D are connected. At this time, by making the impedance of the terminal E of the second switch short-circuited (low impedance), the impedance when the terminal E side is viewed from the output terminal of the post-stage amplifier 105 via the quarter wavelength line 106 is opened (high). Impedance). In FIG. 1, reference numeral 1000 denotes a switch for the short circuit.

As a result, the signal input from the input terminal 101 is amplified by the pre-amplifier 103 and
5, and the output signal is output to the output terminal 107.

When the output power decreases from the maximum point by the gain of the subsequent amplifier, the first high-frequency switch circuit 1 of FIG.
C and E of the second high-frequency switch circuit 104 are connected while 02 is connected from A to B. And the latter stage amplifier 1
The bias control circuit 100 cuts off the bias current 05.

At this time, the bias control circuit biases such that the impedance when the output of the post-amplifier 105 is viewed from the connection point between the quarter wavelength line 106 and the output terminal 107 becomes high.

As a result, the signal input from the input terminal 101 is amplified by the pre-amplifier 103, and
The signal is transmitted to the output terminal 107 via the quarter wavelength line 106, bypassing the signal line 05.

When the output signal further decreases by the gain of the pre-amplifier, the first high-frequency switch circuit 102 is connected from A to F, and the second high-frequency switch circuit is connected from G to E. Then, the bias control circuit 100 cuts off the bias currents of the amplifiers 103 and 105 in the preceding and succeeding stages. As a result, the signal input from the input terminal 101 is transmitted to the output terminal 107, bypassing the pre-amplifier 103 and the post-amplifier 105, respectively.

FIG. 2 shows a change in current consumption with respect to the output power of the power amplifier. It can be seen that the above operation has the current consumption characteristics shown by the thick line in FIG. 2A, and the current consumption can be greatly reduced as compared with the case where the amplifier is not bypassed.

Here, PMAX represents the maximum transmission power, PLEV1 represents the gain of PMAX-the post-amplifier, and PLEV2 represents the gain of PLEV1-the pre-amplifier.

At the boundary of whether to bypass the amplifiers in the preceding and succeeding stages, as shown in FIG. 2B, a power value at which the transmission power is reduced to start the bypass, and a power value at which the transmission power is increased to stop the bypass. By shifting the value, the frequency of bypass switching can be reduced.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram of a power amplifier according to the second embodiment. 300 is a bias control circuit, 301 is an input terminal, 302 is a first high-frequency switch circuit that switches one input to two outputs, 303 is a pre-amplifier, and 304 is a second switch that switches two inputs independently to two outputs. High frequency switch circuit, 3
05 is a middle-stage amplifier, 306 is a third high-frequency switch circuit that switches two inputs to two outputs independently, 307 is a post-amplifier, 308 is a quarter-wave line, and 309 is an output terminal.

The power amplifier according to the second embodiment of the present invention comprises an input terminal 301, a first high-frequency switch circuit 302 for switching a signal input to the input terminal 301 to two outputs, First amplifier (pre-amplifier) 303 connected to one output of high-frequency switch 302
A second high-frequency switch circuit 304 that independently switches two outputs connected to the output of the first amplifier 303 and the other output of the first high-frequency switch 302 to two outputs; Second amplifier (middle-stage amplifier) 30 connected to one output of high-frequency switch circuit 304
5, a third high-frequency switch circuit 306 for independently switching the two inputs connected to the output of the second amplifier 305 and the other output of the second high-frequency switch 304 to two outputs, Amplifier (post-stage amplifier) 3 connected to one output of the high-frequency switch circuit 306 of FIG.
07, a quarter-wave line 308 connected to the other output of the third high-frequency switch circuit 306,
Control circuit 3 for controlling the power supply voltage of the amplifier 303, the second amplifier 305, and the third amplifier 307.
00.

In this embodiment, the bypass circuit is extended to an amplifier having a lower transmission power in the first embodiment. By operating in the same manner as described in the first embodiment, the current consumption can be reduced as shown in FIG.

It is apparent that current consumption can be further reduced by providing a bypass circuit at a further previous stage in the same procedure when the transmission power is further reduced. That is, an arbitrary number of N stages of amplifier circuits 1010 (a set of a high-frequency switch circuit and an amplifier) can be connected.

(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a power amplifier according to the third embodiment. 400 is a bias control circuit, 401 is an input terminal, 402 is a first high-frequency switch circuit that switches one input to two outputs, 403 is a preamplifier, and 404 is a second high-frequency switch that switches two inputs independently to two outputs. High frequency switch circuit, 4
05 is a post-amplifier, 406 is a quarter wavelength line, 407
Is an output terminal, 408 is a first pre-distortion circuit for pre-compensating for distortion generated in the pre-amplifier, 40 is
Reference numeral 9 denotes a second pre-distortion circuit for compensating in advance for distortion generated in the post-stage amplifier.

The power amplifier according to the third embodiment of the present invention includes a first high-frequency switch circuit 402 and a first amplifier (pre-amplifier) 403 in addition to the configuration of the first embodiment.
, A first pre-distortion circuit (first pre-distortion compensation circuit) 408 is provided. Similarly, a second high-frequency switch circuit 404 and a second amplifier (post-stage amplifier) are provided.
A second predistortion circuit (second predistortion compensation circuit) 409 is provided between the second predistortion circuit 405 and the second predistortion circuit 405.

In FIG. 5, the first and second pre-distortion circuits correct the amplitude distortion or the phase distortion of the preceding and succeeding amplifiers in advance, or reduce the non-linear distortion of the entire amplifier by correcting either of them. It becomes possible.

At this time, it is possible to reduce the initial current of each amplifier corresponding to the distortion improvement amount. In this case, even if the bypass circuit is not switched, the current consumption can be reduced when the transmission power is reduced. Can be realized. Needless to say, unnecessary current can be further reduced by the bias control as described in the first embodiment.

Although the pre-distortion compensating circuit is used before the input of the first and second amplifiers, the nonlinear distortion of the whole amplifier can be reduced by using either one of them.

Although the example using the predistortion compensating circuit in the configuration of the power amplifier according to the first embodiment has been described, the same applies to the amplifier according to the second embodiment. Distortion can be reduced.

(Embodiment 4) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of a power amplifier according to the fourth embodiment. FIG. 6 shows the first
(A) is a block diagram, (b) is a circuit diagram, and (c) is a circuit diagram obtained by further improving the (b) circuit. AE
Indicates terminals of the high-frequency switch circuit. FIG.
Although the gate terminals of the transistors Q1 to Q8 in FIG. 6C and the transistors Q1 to Q12 in FIG. 6B are open for the sake of simplicity, actually, a series protective resistor and a parallel bypass capacitor for reducing noise components are used. Is connected to a bias control circuit via

Here, in the high-frequency switch circuit shown in (c), the number of transistors can be reduced by four compared to the switch configuration shown in (b), the circuit can be downsized, and the IC can be easily implemented. Can be.

The high-frequency switch circuit shown in FIG. 6C has a first input terminal A and a first input terminal A in which either one of a drain and a source is connected in series.
And a first output terminal B connected to the remaining one of the drain and the source of the first transistor Q2.
And the other of the drain or source of the second transistor Q1 whose drain or source is grounded at high frequency is connected to the first output terminal B, and either the drain or the source is connected to the first input terminal A. A third transistor Q3, one of which is connected in series, and a second output terminal E connected to the remaining one of the drain or source of the third transistor Q3, and a drain or source connected to the second output terminal E. High frequency grounded fourth transistor Q4
A fifth transistor Q5 having one of the drain or source connected to the second output terminal E and one of the drain or source connected in series to the second output terminal E;
The second input terminal C is connected to the remaining one of the drain and source of the transistor Q5 of the
The other of the drain or the source of the sixth transistor Q6 whose drain or source is grounded at a high frequency is connected to the seventh transistor Q7 having the drain or the source connected in series to the second input terminal C.
And a third output terminal D connected to the remaining one of the drain and the source of the seventh transistor Q7.
And the remaining one of the drain and the source of the eighth transistor Q8 whose drain or source is grounded at a high frequency is connected to the output terminal D.

In this circuit, by controlling the voltage applied to the gate terminal of each transistor as shown in Table 1, the effects described in the first embodiment can be obtained.

[0044]

[Table 1]

Further, by applying an appropriate bias to at least one of the transistors Q1 and Q2 to perform a pre-distortion operation, a special pre-distortion circuit is not added, and the third embodiment can be used. The effect can be obtained.

Similarly, by applying an appropriate bias to at least one of Q6, Q7, and Q8 to perform a predistortion operation, a special predistortion circuit is not required and the third embodiment is not required. The effect can be obtained.

(Embodiment 5) Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram of a power amplifier according to a fifth embodiment. FIG. 7 shows the second
(A) is a block diagram, and (b) is a circuit diagram in which the high-frequency switch circuit of the embodiment is extracted. A to K indicate each terminal of the switch circuit.

In FIG. 7B, transistors Q1 to Q
14 has an open gate terminal for convenience of explanation,
Actually, it is connected to a bias control circuit via a series protection resistor and a parallel bypass capacitor for reducing noise components. In this circuit, as in the fourth embodiment, the number of transistors can be reduced by six compared to the conventional configuration, the circuit can be downsized, and the IC can be easily implemented. The conventional example mentioned here is different from the circuit of FIG. 6B in that Q4 to Q11 in the circuit of FIG.
The above-described circuit parts are further added to the output terminal C. Therefore, the number of transistors is 20 in the conventional example, and 14 in the fifth embodiment, which can be reduced by 6.

The high-frequency switch circuit shown in FIG. 7B has a first input terminal A and a first input terminal A in which one of a drain and a source is connected in series.
And a first output terminal B connected to the remaining one of the drain and the source of the first transistor Q2.
And the other of the drain or source of the second transistor Q1 whose drain or source is grounded at high frequency is connected to the first output terminal B, and either the drain or the source is connected to the first input terminal A. A third transistor Q3 having one connected in series, and a fourth transistor Q3 having a drain or source grounded at a high frequency to one of the remaining drain or source of the third transistor Q3.
A fifth transistor Q5 in which one of the drain and the source of the third transistor Q3 is connected, and one of the drain and the source is connected in series to the remaining one of the drain and the source of the third transistor Q3; The drain or source of the transistor Q5
A sixth transistor Q having a high-frequency grounded drain or source connected to the second input terminal C
And a drain or source of the seventh transistor Q7, the drain or source of which is connected to the second input terminal C, and a drain or source connected to the second input terminal C. Is connected to the second output terminal D, and the remaining one of the drain or source of the eighth transistor Q8 whose drain or source is grounded at high frequency is connected to the second output terminal D; A ninth transistor Q9 in which either the drain or the source is connected in series to the remaining one of the drain or the source of the transistor Q3, and the third output to the remaining one of the drain or the source of the ninth transistor Q9 A tenth transistor Q10 having a terminal K connected thereto and a drain or a source connected to the third output terminal K by high-frequency grounding. An eleventh transistor Q11 in which one of a drain and a source is connected and one of a drain and a source is connected in series to the third output terminal K; and a remaining drain or source of the eleventh transistor Q11. The third input terminal H is connected to the other input terminal, and the remaining one of the drain and source of the twelfth transistor Q12 whose drain or source is grounded at high frequency is connected to the third input terminal H. A thirteenth transistor Q13 having one of a drain and a source connected in series to a terminal H, and a fourth output terminal I connected to the remaining one of the drain and the source of the thirteenth transistor Q13, Drain or source of a fourteenth transistor Q14 whose drain or source is grounded at high frequency to the output terminal I A remaining connecting one configuration.

In this circuit, the effect described in the third embodiment can be obtained by controlling the voltage applied to the gate terminal of each transistor as shown in Table 2.

[0051]

[Table 2]

Further, by applying an appropriate bias to at least one of the transistors Q1 and Q2 to perform a pre-distortion operation, the effect of the third embodiment can be obtained without a pre-distortion circuit. It becomes possible. Similarly, by applying an appropriate bias to at least one of Q6, Q7, and Q8 to perform a pre-distortion operation, the effect of the third embodiment can be obtained without a pre-distortion circuit. It becomes possible.

Similarly, by applying an appropriate bias to at least one of Q12, Q13, and Q14 and performing a pre-distortion operation, the effect of the third embodiment can be obtained without a preceding pre-distortion circuit. It becomes possible.

(Embodiment 6) Next, a sixth embodiment will be described with reference to FIGS. FIG. 8 is a block diagram of a power amplifier 600 according to the present invention. 601 is an input terminal, 602 is a first high-frequency switch for switching one input to two outputs, 603 is an amplifier, 604 is impedance switching means, 605 is a second high-frequency switch for switching two inputs to three outputs, 606 Is the first final stage amplifier,
607 is a second final stage amplifier, 608 is a transmission line, 609
Is an output terminal, and 610 is a bias control circuit.

When the power amplifier according to the sixth embodiment requires the maximum output power, the first high-frequency switch 6 shown in FIG.
01 from A to B, the second high-frequency switch 605
C and D and E are connected. At this time, the impedance of the terminal F of the second high-frequency switch 605 is short-circuited by closing the switch 1001 to make the impedance low, so that the impedance of the first and second final amplifiers 606 and 607 via the transmission line 608 is reduced. Convert the impedance from the output to the terminal side to open (high impedance).

As a result, the signal input from the input terminal 601 is amplified by the amplifier 603, and further amplified by the first and second signals.
Are amplified by the final-stage amplifiers 606 and 607, and the output signal is output to the output terminal 609. At this time, the first and second
Are configured in parallel with the final-stage amplifiers 606 and 607,
Since each circuit generally has the same characteristic impedance,
Matching is performed using the impedance switching means 604.

Here, when the transmission power is sufficient with the amplifier 603 and the first final-stage amplifier 606, the C of the second high-frequency switch 605 is maintained while the first high-frequency switch 602 is connected from A to B. And D are connected.

At this time, the control circuit 610 cuts off the bias current of the second final stage amplifier 607 and outputs the output of the second final stage amplifier 607 from the connection point between the first final stage amplifier 606 and the output terminal 609. A bias is applied so that the observed impedance becomes a high impedance, and the impedance switching means 604 is controlled to be turned off. As a result, the signal input from the input terminal 601 is amplified by the amplifier 603, further amplified by the first final-stage amplifier 606, and the output signal is output to the output terminal 609.

When the transmission power is sufficient with the amplifier 603 and the second final-stage amplifier 607, the first high-frequency switch 602 is connected from A to B while the C and the second high-frequency switch 605 are connected. Connect E.

At this time, the bias control circuit 610 cuts off the bias current of the second final stage amplifier 607 and outputs the output of the first final stage amplifier 606 from the connection point between the second final stage amplifier 607 and the output terminal 609. A bias is provided so that the impedance obtained from the above becomes high impedance, and the impedance switching means 604 is controlled to be turned off. As a result, the signal input from the input terminal 601 is
3 and further amplified by the second final stage amplifier 607, and the output signal is output to the output terminal 609.

When the output power further decreases by the gain of the final-stage amplifier, the C and F of the second high-frequency switch 605 are maintained while the first high-frequency switch 602 is connected from A to B.
Connect.

At this time, the control circuit 610 controls the first and second
Of the final stage amplifiers 606 and 607,
A bias is applied so that the impedance of the output of the first and second final stage amplifiers 606 and 607 from the connection point between the transmission line 608 and the output terminal 609 becomes high, and the impedance switching means 604 is controlled to be turned off. . As a result, the signal input from the input terminal 601 is amplified by the amplifier 603,
6 and 607 are bypassed and output to the output terminal 609 via the transmission line 608.

When the output power further decreases by the gain of the amplifier 603, the first switch 602 is connected from A to G, and H and F of the second switch 605 are connected. At this time, the bias control circuit 610 cuts off the bias currents of the amplifier 603 and the first and second final stage amplifiers 606 and 607, and connects the first and second final stage amplifiers from the connection point between the transmission line 608 and the output terminal 609. A bias is applied so that the impedances of the outputs of the amplifiers 606 and 607 become high impedances, and the impedance switching means 604 is controlled to be turned off. As a result, the signal input from the input terminal 601 bypasses the amplifier 603 and also the final stage amplifier, and is output to the output terminal 609 via the transmission line 608.

FIG. 9 shows the first and second final-stage amplifiers 60.
It shows changes in current consumption with respect to output power of the power amplifier according to the sixth embodiment when amplifiers 6 and 607 have different characteristics.

It can be seen that the above operation has current consumption characteristics as shown by the bold line in FIG. 9, and the current consumption can be greatly reduced as compared with the case where the amplifier is not bypassed.

The first and second final amplifiers 606, 6
If 07 is an amplifier having the same characteristics, it is possible to make the efficiency at the time of output 3 dB lower than the maximum output equal to the efficiency at the time of maximum output.

As shown by the broken line in FIG. 9, the frequency of bypass switching can be reduced by shifting the value of the transmission power at the time of switching the bypass between the case where the transmission power is increased and the case where the transmission power is decreased. is there.

(Embodiment 7) FIGS. 10A and 10B show the power amplifier of the sixth embodiment in which the switches in FIG. 8 are extracted. FIG. 10A is a block diagram, and FIG. 10B is a circuit diagram. The symbols of the terminals correspond to those in FIG. FIG. 10 (b)
Although the gate terminals of the transistors Q1 to Q10 are open for simplicity of description, they are actually connected to a control circuit via a series protection resistor and a parallel bypass capacitor for reducing noise components.

The high-frequency switch circuit shown in FIG. 10 (b) has a first input terminal A and a first transistor Q2 having one of a drain and a source connected in series to the first input terminal A. And the first transistor Q2
The first output terminal B is connected to the remaining one of the drain and the source of the second transistor Q1, and the remaining one of the drain and the source of the second transistor Q1 whose drain or the source is grounded at a high frequency is connected to the first output terminal B. A third transistor Q3 having one of a drain and a source connected in series to the first input terminal A, and a second transistor Q3 connected to the remaining one of the drain and the source of the third transistor Q3.
A fourth transistor Q having a high-frequency grounded drain or source connected to the second output terminal F
A fifth transistor Q5 in which one of the drain and the source of the fourth transistor Q4 is connected and one of the drain and the source is connected in series to the second output terminal F; and a drain or a source of the fifth transistor Q5. Is connected to a second input terminal C, and the remaining one of a drain and a source of a sixth transistor Q6 whose drain or source is grounded at a high frequency is connected to the second input terminal C. Transistor Q7 in which either the drain or the source is connected in series to the input terminal C
And a third output terminal D connected to the remaining one of the drain and the source of the seventh transistor Q7.
The other one of the drain or source of the eighth transistor Q8 whose drain or source is grounded at high frequency is connected to the output terminal D of the fifth transistor Q5, and the ninth transistor Q9 is connected to the remaining one of the drain or source of the fifth transistor Q5.
Is connected in series, and the other of the drain or source of the ninth transistor Q9 is connected to the other of the drain or source of the tenth transistor Q10 whose drain or source is grounded at high frequency. And the fourth output terminal E is connected to the remaining one of the drain and the source of the ninth transistor Q9.
Are connected.

In this circuit, by controlling the voltage applied to the gate terminal of each transistor as shown in Table 3, the effect described in the sixth embodiment can be obtained. By applying an appropriate bias to at least one of the transistors Q1 and Q2, similarly to at least one of the transistors Q6, Q7 and Q8, and at least one of the transistors Q6, Q9 and Q10, a pre-distortion circuit is provided. The pre-distortion operation can be performed without the need for the pre-distortion operation.

By performing the pre-distortion operation, the nonlinear distortion of the whole amplifier can be reduced, and the initial current corresponding to the distortion improvement amount can be reduced. In this case, current consumption can be reduced when the transmission power is reduced within a range where the bypass circuit is not switched.

[0072]

[Table 3]

It is clear that the bypass switching control described in the sixth embodiment can obtain the same effect in the seventh embodiment.

It is apparent that the same effects as described above can be obtained even if a part or all of the high-frequency switch circuit and the amplifier are formed on the same semiconductor substrate. In addition, when the high-frequency switch circuit and the amplifier are respectively formed on different semiconductor substrates, excellent performance can be achieved by using different materials (for example, gallium arsenide and silicon or silicon germanium) and different processes (for example, field-effect transistors and bipolar transistors). Since the same device can be shared, cost reduction and downsizing of the terminal by single power supply operation can be realized.

In FIG. 11, each of the above-described high-frequency switch circuits is formed on a first same semiconductor substrate 80, and each amplifier is formed on a second same semiconductor substrate 81. One semiconductor substrate 80 and the second semiconductor substrate 81 are mounted on the same dielectric substrate 82.

If the switching control at the bypass switching boundary mentioned only in the first embodiment is performed in accordance with the principle described in the first embodiment, the same applies to the second to seventh embodiments. It is clear that the effect can be obtained.

Further, as shown in FIG. 12, the communication device of the present invention comprises the above-described power amplifier 931 according to the present invention,
An antenna 90, a receiving circuit 91, a signal processing circuit 93 for processing a signal from the receiving circuit 91 using the power amplifier 931, and a transmitting circuit 92 for transmitting and processing a signal from the signal processing circuit 93; A communication device comprising:

[0078]

As described above, according to the power amplifier of the present invention, as the transmission power is reduced, the high-power amplifier is bypassed by the high-frequency switch, and the power supply of the bypassed amplifier is cut off to reduce the transmission power. It is possible to improve efficiency. By repeating this operation, it is possible to improve the efficiency over a wide dynamic range during transmission.

Further, the initial current of the amplifier itself in each stage can be reduced to improve the efficiency at the time of low output by operation close to the class B. At that time, the distortion of the amplifier becomes large, by performing pre-distortion compensation using the transistor of the high-frequency switch in the bypass circuit, the initial current is small without increasing the circuit scale, and at the time of low output. It is possible to realize a power amplifier configured to cut off unnecessary current.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power amplifier according to a first embodiment of the present invention.

FIGS. 2A and 2B are graphs for explaining the operation of the power amplifier according to the first embodiment;

FIG. 3 is a block diagram of a power amplifier according to a second embodiment;

FIG. 4 is a graph illustrating an operation of the power amplifier according to the second embodiment.

FIG. 5 is a block diagram of a power amplifier according to a third embodiment;

FIG. 6A is a block diagram of a high-frequency switch unit of a power amplifier according to a fourth embodiment. FIG. 6B is a circuit diagram of a high-frequency switch unit of the power amplifier according to the fourth embodiment. ) Is the circuit diagram of the improved high-frequency switch section

FIG. 7A is a block diagram of a high-frequency switch of a power amplifier according to a fifth embodiment; FIG. 7B is a circuit diagram of a high-frequency switch of the power amplifier according to the fifth embodiment;

FIG. 8 is a block diagram of a power amplifier according to a sixth embodiment.

FIG. 9 is a view for explaining the operation of a power amplifier according to a sixth embodiment;

FIG. 10A is a block diagram of a high-frequency switch unit of a power amplifier according to a seventh embodiment. FIG. 10B is a circuit diagram of a high-frequency switch unit of the power amplifier according to the seventh embodiment.

FIG. 11 is a side view of a substrate related to the embodiment of the present invention.

FIG. 12 is a configuration diagram showing an embodiment of a communication device according to the present invention.

FIG. 13 is a configuration diagram of a conventional power amplifier.

FIG. 14 is a diagram illustrating the operation of a conventional power amplifier.

[Explanation of symbols]

100, 300, 400, 610 Bias control circuit 101, 301, 401, 701, 601 Input terminal 102, 302, 402, 602 First high frequency switch circuit 103, 303, 403, 702 Preamplifier 104, 304, 404, 605 Second high-frequency switch circuit 105, 307, 405, 703 Post-amplifier 106, 308, 406 Quarter-wavelength line (impedance conversion circuit) 107, 309, 407, 609, 704 Output terminal 305 Middle-stage amplifier 306 Third high-frequency Switch circuit 408 First pre-distortion circuit 409 Second pre-distortion circuit 603 Amplifier 606 First final amplifier 607 Second final amplifier 608 Transmission line (impedance conversion circuit) 1010 Amplifier circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03G 3/02 H03G 3/02 Z (72) Inventor Hiroaki Kosugi 1006 Kazuma Kazuma, Kadoma, Osaka Matsushita Electric Industrial (72) Inventor Toshio Ohara 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa F-term (reference) 5J069 AA01 AA04 AA41 AA64 CA21 CA32 CA36 FA10 FA11 FA18 HA09 HA31 HA38 HA39 KA12 KA68 KC03 QA04 SA13 SA14 TA01 TA02 5J090 AA01 AA04 AA41 AA64 CA21 CA32. SA14 TA01 TA02 5J092 AA01 AA04 AA41 AA64 CA21 CA32 CA36 FA10 FA11 FA18 GR09 HA09 HA31 HA38 HA39 KA12 KA68 QA04 SA13 SA14 TA01 TA02 5J100 AA14 AA16 AA26 BA01 BB02 CA11 CA12 CA33 DA06 EA02 FA01

Claims (21)

[Claims] 1. An input terminal, an output terminal, N bypassable amplifier circuits connected directly or indirectly between the input terminal and the output terminal in sequence, and the last-stage amplifier circuit And an impedance conversion circuit connected directly or indirectly between the output terminal, and a bias control circuit for controlling the amplification circuit, the amplification circuit, a high-frequency switch circuit, and directly or indirectly to it A power amplifier, comprising a connected amplifier, wherein the bias control circuit controls a power supply voltage of the amplifier and controls the high-frequency switch circuit. 2. A first terminal capable of outputting an input terminal and a signal input to the input terminal while switching the signal to two output terminals.
And a first high-frequency switch circuit directly or indirectly connected to one output terminal of the first high-frequency switch circuit.
And an output terminal of the first amplifier and the other output terminal of the first high-frequency switch circuit are directly or indirectly connected to each other, and two signals input from each output terminal are independently converted into two signals. A second high-frequency switch circuit capable of outputting while switching to an output terminal, a second amplifier directly or indirectly connected to one output terminal of the second high-frequency switch circuit, and a second high-frequency switch circuit. An impedance conversion circuit directly or indirectly connected to the other output terminal; an output terminal of the second amplifier and an output terminal commonly or directly connected to an output terminal of the impedance conversion circuit; The first amplifier and the second amplifier
And a bias control circuit for controlling the power supply voltage of the amplifier and controlling the high-frequency switch circuit. 3. A first terminal capable of outputting a signal input to the input terminal and switching the signal input to the input terminal to two output terminals.
And a first high-frequency switch circuit directly or indirectly connected to one output terminal of the first high-frequency switch circuit.
And an output terminal of the first amplifier and the other output terminal of the first high-frequency switch circuit are directly or indirectly connected to each other, and two signals input from each output terminal are independently converted into two signals. A second high-frequency switch circuit capable of outputting while switching to an output terminal, a second amplifier directly or indirectly connected to one output terminal of the second high-frequency switch circuit, and an output terminal of the second amplifier And a third high-frequency switch connected directly or indirectly to the other output terminal of the second high-frequency switch circuit and capable of outputting two signals input from the respective output terminals while independently switching to the two output terminals. Circuit, a third amplifier connected directly or indirectly to one output terminal of the third high-frequency switch circuit, and another output terminal of the third high-frequency switch circuit An impedance conversion circuit directly or indirectly connected to the first amplifier; an output terminal of the third amplifier; an output terminal commonly or directly connected to an output terminal of the impedance conversion circuit; and the first amplifier. A power amplifier, comprising: a bias control circuit that controls a power supply voltage of the second amplifier and the third amplifier and controls the high-frequency switch circuit. 4. A first terminal capable of outputting a signal input to an input terminal and switching the signal input to the input terminal to two output terminals.
High-frequency switch circuit, a first amplifier directly or indirectly connected to one output terminal of the first high-frequency switch, and an impedance directly or indirectly connected to the output terminal of the first amplifier A switching unit, which is directly or indirectly connected to the other output terminal of the first high-frequency switch circuit and the output terminal of the impedance switching unit, and independently outputs two signals input from the respective output terminals.
A second high-frequency switch circuit capable of outputting while switching to two output terminals, a first final-stage amplifier connected directly or indirectly to a first output terminal of the second high-frequency switch,
A second final-stage amplifier connected directly or indirectly to a second output terminal of the second high-frequency switch; and a second final-stage amplifier directly or indirectly connected to a third output terminal of the second high-frequency switch. An impedance conversion circuit; an output terminal commonly or indirectly connected to the first and second final-stage amplifiers and the impedance conversion circuit; and the first amplifier and the first and second amplifiers. 2, the power supply voltage of the final stage amplifier,
A power amplifier, comprising: a bias control circuit that controls on / off of the impedance switching unit and switching of the first and second high-frequency switch circuits. 5. The power amplifier according to claim 4, wherein the first and second final-stage amplifiers are power amplifiers having the same characteristics. 6. The power amplifier according to claim 1, further comprising a predistortion compensation circuit at an input of at least one amplifier. 7. The power amplifier according to claim 1, wherein each of the high-frequency switch circuits is formed on the same semiconductor substrate. 8. The power amplifier according to claim 1, wherein each amplifier is formed on the same semiconductor substrate. 9. The power amplifier according to claim 1, wherein each high-frequency switch circuit and each amplifier are formed on the same semiconductor substrate. 10. Each of the high-frequency switch circuits is formed on a first same semiconductor substrate, each amplifier is formed on a second same semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are connected to each other. 6. The power amplifier according to claim 1, wherein said semiconductor substrate is mounted on the same dielectric substrate. 11. The first amplifier and the first and second high-frequency switch circuits are formed on a first semiconductor substrate, and the first and second final-stage amplifiers and the impedance conversion circuit are formed on a first semiconductor substrate. 5. The power amplifier according to claim 4, wherein the power amplifier is configured on two identical semiconductor substrates, and the first semiconductor substrate and the second semiconductor substrate are mounted on a same dielectric substrate. 12. A power amplifier having at least two stages, a bypass circuit provided in parallel with the power amplifier, a high-frequency switch circuit connected to input / output terminals of the power amplifier and the bypass circuit, and a bias control circuit. A power control method for a power amplifier comprising: the high-frequency switch circuit switches the power amplifier and the bypass circuit according to the output power of the entire amplifier,
A power control method for a power amplifier, wherein the bias control circuit shuts off a power supply of an unused power amplifier. 13. The power control method for a power amplifier according to claim 2, wherein at a maximum transmission power, the bias control circuit switches and connects the first high-frequency switch circuit to the first amplifier. An input (C) of the second high-frequency switch circuit on the output side of the first amplifier is connected to a second amplifier (D), and a power supply voltage is applied to both the first amplifier and the second amplifier. And the impedance of the second high-frequency switch circuit at a point connected to the input of the impedance conversion circuit is reduced to a low impedance,
When controlling the impedance obtained by looking at the impedance conversion circuit from the output of the second amplifier to be a high impedance, and when lowering the transmission power by the gain of the second amplifier, the bias control circuit: The first high-frequency switch circuit is switched and connected to the first amplifier side, and the input (C) of the second high-frequency switch circuit on the output side of the first amplifier is connected to the impedance conversion circuit (E). Connected to supply the power supply voltage only to the first amplifier, cut off the power supply voltage of the second amplifier, and increase the impedance of the second amplifier from the output of the impedance conversion circuit to the high impedance. When the transmission power is further reduced by an amount corresponding to the gain of the first amplifier, the bias control circuit sets the first high-frequency switch circuit in front of the first high-frequency switch circuit. The second high-frequency switch circuit is switched to the input terminal (G) side and connected to the second high-frequency switch circuit.
The high frequency switch circuit is switched to the impedance conversion circuit side, the power supply voltage of both the first amplifier and the second amplifier is cut off, and the impedance of the second amplifier is viewed from the output of the impedance conversion circuit. A power control method for a power amplifier, comprising: 14. The power control method for a power amplifier according to claim 3, wherein at the time of maximum transmission power, the bias control circuit switches and connects the first high-frequency switch circuit to the first amplifier. An input (C) of a second high-frequency switch circuit on the output side of the first amplifier is connected to the second amplifier (D), and an output of the second amplifier of the third high-frequency switch circuit is connected. Side input (H) is connected to the third amplifier (I), and a power supply voltage is supplied to all of the first amplifier, the second amplifier, and the third amplifier,
The impedance of the third high-frequency switch circuit at a point connected to the input of the impedance conversion circuit is set to low impedance, and the impedance obtained by viewing the impedance conversion circuit from the output of the third amplifier becomes high. When the transmission power is reduced by the gain of the third amplifier, the bias control circuit connects the first high-frequency switch circuit to the first amplifier and switches the second high-frequency switch circuit to the first amplifier. The input (C) on the output side of the first amplifier of the high-frequency switch circuit is connected to the second amplifier (D), and the output (C) of the third high-frequency switch circuit is connected to the output side of the second amplifier. An input (H) is connected to the impedance conversion circuit side (K), a power supply voltage is supplied only to the first amplifier and the second amplifier, and a power supply voltage of the third amplifier is provided. Is controlled so that the impedance of the third amplifier viewed from the output of the impedance conversion circuit becomes high impedance. Further, when the transmission power is reduced by the gain of the second amplifier, the bias A control circuit switches and connects the first high-frequency switch circuit to the first amplifier, and connects an input (C) of the second high-frequency switch circuit on the output side of the first amplifier to the third amplifier. An output terminal (E) to the high-frequency switch circuit, and an input terminal (J) of the third high-frequency switch circuit on the second high-frequency switch circuit side is connected to the impedance conversion circuit side (K). , A power supply voltage is supplied only to the first amplifier, a power supply voltage of the second amplifier and the third amplifier is cut off, and the third voltage is increased from an output of the impedance conversion circuit. When the transmission power is reduced by the gain of the first amplifier, the bias control circuit controls the first high frequency switch circuit to 2 and connected to the output terminal (F) of the second high-frequency switch circuit, and the input terminal (G) of the second high-frequency switch circuit on the side of the first high-frequency switch circuit is connected to the third high-frequency switch circuit. Of the third terminal.
The input terminal (J) on the side of the second high-frequency switch circuit of the high-frequency switch circuit is connected to the output terminal (K) to the impedance conversion circuit, and the first amplifier, the second amplifier, and the A power control method for a power amplifier, comprising shutting off any power supply voltage of a third amplifier and controlling the impedance of the third amplifier from the output of the impedance conversion circuit to a high impedance. 15. The power control method for a power amplifier according to claim 4, wherein at the time of maximum power transmission, the bias control circuit switches and connects the first high-frequency switch circuit to the first amplifier. The input terminal of the second high-frequency switch circuit on the impedance switching means side is connected to the first
And the second final amplifier, turning on the impedance switching means, supplying a power supply voltage to both the first amplifier and the first and second final amplifiers, The impedance of the impedance conversion circuit as seen from the point where the impedance of the second high-frequency switch circuit at the connected point is reduced to a low impedance and the output of the impedance conversion circuit is coupled with the first and second final stage amplifiers. When the transmission power is controlled to be high and only the first amplifier and the first final-stage amplifier are sufficient, the bias control circuit sets the first high-frequency switch circuit to the first high-frequency switch circuit. And the input terminal of the second high-frequency switch circuit on the side of the impedance switching means is connected only to the first final-stage amplifier. The impedance switching means is turned off, a power supply voltage is supplied to the first amplifier and the first final amplifier, a power supply voltage of the second final amplifier is cut off, and the power supply voltage is connected to an input of the impedance conversion circuit. The impedance of the impedance conversion circuit from the point where the impedance of the second high-frequency switch circuit is reduced to a low impedance and the output of the first and second final stage amplifiers and the impedance conversion circuit are coupled to each other. And controlling the impedance of the second final amplifier to be high from the point where the outputs of the first and second final amplifiers and the output of the impedance conversion circuit are coupled. When only the first amplifier and the second final-stage amplifier are sufficient, the bias control circuit A frequency switch circuit connected to the first amplifier side, and an input terminal of the second high frequency switch circuit on the impedance switching means side connected to only the second final stage amplifier; Is turned off, a power supply voltage is supplied to the amplifier and the second final-stage amplifier, a power supply voltage of the first final-stage amplifier is cut off, and the power supply voltage at the point connected to the input of the impedance conversion circuit is reduced. 2, the impedance of the high-frequency switch circuit is set to low impedance, and the impedance of the impedance conversion circuit as viewed from the point where the outputs of the first and second final-stage amplifiers and the impedance conversion circuit are coupled becomes high. The first final-stage amplifier is viewed from the point where the first and second final-stage amplifiers and the output of the impedance conversion circuit are coupled. When the transmission power is reduced by the gain of the first and second final-stage amplifiers, the bias control circuit controls the first high-frequency switch circuit to Connected to the driver amplifier side, the input terminal of the second high-frequency switch circuit on the impedance switching means side is connected to the impedance conversion circuit, the impedance switching means is turned off, and power is supplied only to the first amplifier. The first and second final amplifiers are supplied with a voltage, the power supply voltage of the first and second final amplifiers is cut off, and the first and second final amplifiers are coupled with the output of the impedance conversion circuit. When the transmission power is controlled so that the impedance seen by the final-stage amplifier becomes high, and the transmission power is reduced by the gain of the first amplifier, The bias control circuit switches the first high-frequency switch circuit to an output terminal (G) side to the second high-frequency switch circuit,
The input terminal (H) on the first high frequency switch circuit side of the high frequency switch circuit is connected to the impedance conversion circuit side (F), and the impedance switching means is turned off. The power supply voltage of each of the first and second final stage amplifiers is cut off, and the first and second
Controlling the impedance of the first and second final amplifiers from the point where the output of the final stage amplifier and the output of the impedance conversion circuit are coupled to each other to be high impedance. . 16. The method according to claim 16, wherein the bias control circuit is configured to control the first amplifier, the second amplifier,
When the third amplifier and any or any combination of the first and second final amplifiers are bypassed, the magnitude of the transmission power at the time of the bypass is determined by: The power control method for a power amplifier according to any one of claims 13 to 15, wherein the power control method is different from a case where the power amplifier is in a decreasing process. 17. The predistortion compensating operation is realized by a part of a high-frequency switch circuit connected to an input of at least one amplifier.
16. The power amplification method for a power amplifier according to any one of 15. 18. A first FET having an input terminal and a drain terminal connected to the input terminal.
(Q2), a second FET having a drain terminal connected to the input terminal
(Q3): a first amplifier having an input terminal connected to the source terminal of the first FET; and a second amplifier having a drain terminal connected to the source terminal of the first FET and having a source grounded at a high frequency. 3 FETs (Q1)
A fourth FET (Q4) having a drain terminal connected to a source terminal of the second FET and a source grounded at a high frequency.
A fifth FET (Q5) having a drain terminal connected to the source terminal of the second FET; an impedance conversion circuit having an input terminal connected to the source terminal of the second FET; A sixth FET (Q6) having an output of the first amplifier connected to a source terminal of the FET, a drain terminal connected to a source terminal of the fifth FET, and a source grounded at a high frequency;
A seventh FET (Q7) having a drain terminal connected to the source terminal of the fifth FET, and an eighth FET having a drain terminal connected to the source terminal of the seventh FET and having a source grounded at a high frequency. FET (Q8)
A second input having an input connected to the source terminal of the seventh FET.
And the output terminal of the impedance conversion circuit and the output terminal of the second amplifier are connected and connected, and the output terminal is connected to the output terminal of the second amplifier. amplifier. 19. An input terminal and a first FET having a drain terminal connected to the input terminal.
(Q2), a second FET having a drain terminal connected to the input terminal
(Q3): a first amplifier having an input terminal connected to a source terminal of the first FET; and a third amplifier having a drain terminal connected to a source terminal of the first FET and having a source grounded at high frequency. FET (Q1)
A fourth FET (Q4) having a drain terminal connected to a source terminal of the second FET and a source grounded at a high frequency.
A fifth FET (Q5) having a drain terminal connected to a source terminal of the second FET; an output terminal of the first amplifier connected to a source terminal of the fifth FET; A sixth FET (Q6) in which the drain terminal is connected to the source terminal of the FET and the source is grounded at a high frequency.
A seventh FET (Q7) having a drain terminal connected to the source terminal of the fifth FET, and an eighth FET having a drain terminal connected to the source terminal of the seventh FET and having a source grounded at a high frequency. FET (Q8)
A second amplifier having an input terminal connected to the source terminal of the seventh FET; a ninth FET (Q9) having a drain terminal connected to the source terminal of the second FET; A tenth FET (Q10) having a source grounded at a high frequency to a source terminal; an impedance conversion circuit having an input terminal connected to a source terminal of the ninth FET; and a drain connected to a source terminal of the ninth FET. And an eleventh FET (Q1) having a drain connected to the source terminal of the eleventh FET and having a source grounded at a high frequency.
2) an output terminal of the second amplifier is connected to a source terminal of the eleventh FET; a thirteenth FET (Q13) having a drain terminal connected to a source terminal of the eleventh FET; A drain terminal is connected to the source terminal of the thirteenth FET, and the source is grounded at high frequency.
4); a third amplifier having an input terminal connected to a source terminal of the fourteenth FET; an output terminal of the impedance conversion circuit and an output terminal of the third amplifier connected; And an output terminal connected to the output terminal of the power amplifier. 20. An input terminal and a first FET having a drain terminal connected to the input terminal.
(Q2), a second FET having a drain terminal connected to the input terminal
(Q3), a first FET having an input connected to a source terminal of the first FET.
An impedance switching circuit connected to the first amplifier; a third FET (Q1) having a source connected to a drain terminal of the first FET and a source grounded at a high frequency.
A fourth FET (Q4) having a drain terminal connected to a source terminal of the second FET and a source grounded at a high frequency.
A fifth FET (Q5) having a drain terminal connected to the source terminal of the second FET; an impedance conversion circuit having an input terminal connected to the source terminal of the second FET; A sixth FET (Q6) having a source terminal connected to the output terminal of the first amplifier, a drain terminal connected to a source terminal of the fifth FET, and a source grounded at a high frequency.
An output terminal of the impedance switching circuit is connected to a source terminal of the fifth FET; a seventh FET (Q7) having a drain terminal connected to the source terminal of the fifth FET; Eighth FET (Q8) having a drain terminal connected to the source terminal of the first FET and the source grounded at a high frequency
A second amplifier having an input terminal connected to the source terminal of the seventh FET; a ninth FET (Q9) having a drain terminal connected to the source terminal of the fifth FET; The tenth FET (Q1) having a drain terminal connected to the source terminal of the first FET and having the source grounded at high frequency.
0), a third amplifier having an input terminal connected to the source terminal of the ninth FET, an output terminal of the second amplifier, an output terminal of the third amplifier, and an output of the impedance conversion circuit. A power amplifier, comprising: an output terminal connected to the terminal; 21. A power amplifier according to any one of claims 1 to 11, or an antenna, a receiving circuit, and a signal from said receiving circuit, wherein said power amplifier is used. A communication device, comprising: a signal processing circuit for performing processing on the signal; and a transmission circuit for transmitting and processing a signal from the signal processing circuit.