JP2001185695A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify a memory cell position without lowering level of integration. SOLUTION: A mark 20 for specifying a memory cell position is formed on the memory cell arranged near an intersection point of a word line 9 and a bit line 11 arrayed into a matrix shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a memory cell near an intersection between a word line and a bit line arranged in a matrix. The present invention relates to a technology for simplifying a specific operation.

[0002]

2. Description of the Related Art FIG. 3 is a partial plan view showing a pattern arrangement of a conventional semiconductor memory device. On the main surface of the semiconductor chip 1, a peripheral circuit 3 and a plurality of memory cell array blocks 8 are formed. The memory cell block 8 has a structure in which the memory cell arrays 5 are arranged at both ends of the sense amplifier array 7. There are many memory cells in the memory cell array 5 and many sense amplifiers in the sense amplifier array 7.

FIG. 4 is a partial plan view showing the pattern arrangement of the memory cell array block 8. A plurality of word lines 9 are arranged in the X direction, and a plurality of bit lines 11 are arranged in the Y direction. Therefore, the word lines 9 and the bit lines 11 are arranged in a matrix. Then, by specifying the word line 9 and the bit line 11, the memory cell 19 is specified. Incidentally, reference numeral 17 denotes a sense amplifier.

For example, a bit line 11 indicated by 12 is a Y address 124, and a word line 9 indicated by 14 is an X address 6. There are 128 word lines 9 and X addresses 0 to 0 in order.
The X address is 127.

[0005] As a result of the test after the completion of the semiconductor chip, the memory cell 19 (shown by oblique lines) specified by the X address 6 and the Y address 124 is a defective cell.

When observing the memory cell 19 with an SEM or the like in order to investigate the cause of the failure of the defective memory cell 19, the bit lines corresponding to the Y address 124 in order from the bit line 11 which is the Y address. Then, the word line 9 as the X address is counted from the word line 9 corresponding to the X address 0 to the word line 9 corresponding to the X address 6 in order, and the defective memory cell 19 is visually determined. I was searching for it.

For this reason, it takes time to specify the defective cell.

Accordingly, the following technology has been developed. That is, as shown in FIG. 5, the Y address corresponding to each bit line 11 is represented by 126+, 127+... On the semiconductor chip, and the X address corresponding to each word line 9 is A0.
+, A02 +... On the semiconductor chip by numbers
The task of identifying defective cells is facilitated. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 5-335519.

[0009]

However, as shown in FIG. 5, the above-described structure requires a dedicated space around the memory cell for attaching the identification mark, which hinders high integration. . In addition, the reason why the number of the word line 9 is set to an even number as described above is because of space. As described above, in the conventional configuration, there is a limitation in facilitating the operation of specifying the defective cell.

Accordingly, it is an object of the present invention to provide a semiconductor memory device capable of specifying a memory cell position without lowering the degree of integration.

[0011]

In view of the above problem, a semiconductor memory device according to the present invention is arranged near the intersection of a word line 9 and a bit line 11 arranged in a matrix as shown in FIG. A mark 20 for specifying the position of the memory cell is formed on the memory cell.

The mark 20 corresponds to the word line 9.
(Or bit line 11) is characterized in that the shape of a specific portion is different from other portions.

As shown in FIG. 2, the mark 21 is formed so that the shape of a specific portion in the word line 9 (or bit line 11) is different from that of another portion, and the adjacent word lines (or bit lines ), The formation position is shifted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described below with reference to the drawings.
The same components as those of the conventional configuration are denoted by the same reference numerals, and description thereof will be simplified.

FIG. 1 is a partial plan view showing a pattern arrangement of a memory cell block constituting a semiconductor memory device of the present invention.

In FIG. 1, a plurality of word lines (WL) 9 are arranged in the Y direction, and a pair of bit lines (BL, / B) are arranged.
L) A plurality of 11 are arranged in the X direction to form a memory cell in a matrix.

Reference numeral 20 denotes a mark (notch pattern) for a mark formed at a desired portion of the word line 9 for specifying the position of the memory cell. The desired location of line 9 (eg,
The pair of bit lines (BL, BL,
/ BL) Mark 20 for each pair
Are formed. Thus, by counting the word lines 9 using the mark 20 as a mark, it is easy to specify a defective portion in the memory cell.

As described above, according to the present invention, by attaching the mark 20 to a desired portion of the word line 9, it is possible to specify a defective portion (defective bit or the like) more quickly than counting the bit lines 11 one by one. Work time.

FIG. 2 shows another embodiment of the present invention.
This will be described with reference to FIG. Note that the same components as those of the embodiment are denoted by the same reference numerals, and description thereof will be simplified.

The feature of the other embodiment is that, instead of the configuration of the mark 20 of the embodiment shown in FIG. 1, the adjacent word lines 9 are shifted from each other as shown in FIG. It is.

That is, as shown in FIG. 2, a plurality of word lines (WL) 9 arranged in the Y direction and a pair of bit lines (BL, / BL) 11 arranged in the X direction are arranged in a matrix. In the state where the memory cells are formed, marks 21 for marks are formed at desired locations of the word lines 9. The position of the mark 21 formed on the word line 9 is shifted for each adjacent word line 9 to reduce the total number of marks 21 formed per word line 9.

Thus, in the other embodiment, the influence of the parasitic resistance due to the addition of the mark is reduced as compared with the embodiment in which the mark 20 is formed at the position adjacent to all the word lines 9. Can be. In addition, as shown in FIG. 2, if the mark 21 is provided every other word line 9 (and also every predetermined number of word lines 9), the influence on the operation of identifying the defective portion is small.

As described above, in the present invention, the marks 20 and 21 formed by making the shape of the desired portion of the word line 9 different from those of other portions facilitate the specification of the memory cell position. In addition, since the marks 20 and 21 are formed on the memory cells, there is no need for a dedicated space around the memory cells for attaching the identification marks as in the conventional case, which is advantageous for high integration. is there.

In the above-described embodiment, an example in which the marks 20 and 21 are formed on the word line 9 is introduced. However, the present invention is not limited to this. For example, the marks may be formed on the bit line 11 side. Alternatively, a mark may be formed on both the word line 9 and the bit line 11 as a matter of course. It is not a good idea to put a mark on the bit line 11 because the operation speed becomes slow and the circuit driving capability is affected.

[0025]

According to the present invention, the position of the memory cell can be easily specified, and the operation time for specifying the defective portion can be greatly reduced as compared with the conventional case.

Moreover, since the marks are formed directly on the word lines or the bit lines, it is not necessary to secure a space dedicated to the marks around the memory cells as in the prior art, and the degree of integration does not decrease.

[Brief description of the drawings]

FIG. 1 is a main part plan view showing a pattern arrangement of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a main part plan view showing a pattern arrangement of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 3 is a main part plan view showing a pattern arrangement of a conventional semiconductor integrated circuit.

FIG. 4 is a main part plan view showing a pattern arrangement of a conventional semiconductor integrated circuit.

FIG. 5 is a main part plan view showing a pattern arrangement of a conventional semiconductor integrated circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yuji Goto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Yuichi Watanabe 2-5-1 Keihanhondori, Moriguchi-shi, Osaka No. 5 F term in Sanyo Electric Co., Ltd. (reference) 5F033 UU03 VV16 XX37 5F083 LA12 LA16 ZA20

Claims (4)

[Claims] 1. A semiconductor memory device having a memory cell near an intersection between a word line and a bit line arranged in a matrix, wherein a mark for specifying the position of the memory cell is formed on the memory cell. A semiconductor memory device characterized by the above-mentioned. 2. A semiconductor memory device having a memory cell near an intersection between a word line and a bit line arranged in a matrix, comprising: a mark for specifying a memory cell position on at least one of the word line and the bit line; A semiconductor memory device characterized by having a pattern formed thereon. 3. The semiconductor memory device according to claim 1, wherein the mark has a specific portion in the word line or the bit line having a different shape from other portions. 4. The mark is characterized in that the shape of a specific portion in the word line or bit line is different from that of another portion, and the formation position of the mark is shifted between adjacent word lines or bit lines. The semiconductor memory device according to claim 1 or 2, wherein: