JP2001185692A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

(57) Abstract: A semiconductor device having a multi-layer wiring and a method for manufacturing the same are provided. A first insulating layer is formed on a surface of a semiconductor substrate on which a semiconductor memory element having a connection terminal and a peripheral circuit element are formed, and a hole reaching the connection terminal from the surface is formed. A mask layer for forming a conductor in the hole, covering the conductor, a second insulating layer on the first insulating layer, an opening in a region including the semiconductor memory element thereon, and covering the peripheral circuit element To form Using the mask layer as a mask, the second and first insulating layers in the opening are etched to expose the side walls of the conductor. A capacitor dielectric film and a cell plate electrode layer are formed on the substrate so as to cover the exposed surface of the conductor, and the cell plate electrode layer on the insulating layer is removed. A wiring connected to the conductor on the second connection terminal is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-layer wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) usually includes one transistor and one capacitor in one memory cell. In order to increase the memory capacity, it is necessary to arrange as many memory cells as possible within a limited area. In order to operate the memory cell, a word line also serving as a gate electrode of a memory cell transistor, a charge is supplied to a capacitor, and a bit line for reading a charge from the capacitor is arranged to cross. In order to arrange word lines and bit lines crossing each other, two or more wiring layers are required.

In order to form a capacitor, a storage electrode connected to each memory transistor and a cell plate electrode facing the storage electrode via a capacitor dielectric film are required.

In order to improve the degree of integration of a DRAM, it is known to arrange a word line and a bit line on the surface of a semiconductor substrate and then arrange a capacitor further above the word line and the bit line. The storage electrodes of these capacitors need to be connected to one source / drain region of the memory cell transistor. In order to reliably form a connection opening in an insulating layer, a structure for a self-aligned contact has been proposed.

That is, the upper and side surfaces of the word line of the memory cell transistor are covered with a silicon nitride film, and have a role of an etch stopper. In forming an opening reaching the source / drain region of the transistor, the source / drain region is reliably exposed because the silicon nitride film functions as an etch stopper even if the opening position is slightly shifted. At this time, the word line also serving as the gate electrode is insulated and protected by the silicon nitride film.

The SAC structure is also used when embedding a word line with an insulating layer and forming a bit line on the surface of the insulating layer. The upper and side surfaces of the bit line are covered with a silicon nitride film, and when etching from above to form an opening, the bit line is insulated and protected, and an opening is reliably formed in the connection region.

[0007] In the DRAM, the degree of integration is further improved,
It is hoped that production prices will fall. In order to reliably manufacture a highly integrated DRAM, a highly reliable manufacturing process is desired. In order to manufacture low-cost DRAM, it is desired to simplify the manufacturing process.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost, highly reliable semiconductor device having a high degree of integration.

Another object of the present invention is to provide a method of manufacturing a highly integrated semiconductor device in which the manufacturing process is simplified.

[0010]

According to one aspect of the present invention, there is provided (a) a semiconductor memory device having a first connection terminal and a peripheral circuit device having a second connection terminal formed on a surface of a semiconductor substrate. (B) forming first and second holes reaching the first and second connection terminals from the surface of the insulating layer; and (c) forming the first and second holes. Forming a first and a second conductor in the second hole, and (d) forming a mask layer having an opening in a region including the semiconductor memory element and covering the peripheral circuit element on the insulating layer. Forming, and (e) using the mask layer as a mask, etching the first conductor in the first hole in the opening, and moving the top surface thereof below the surface of the insulating layer. (F) using the mask layer as a mask, etching the insulating layer in the opening to form a sidewall of the first conductor; A step of leaving, (g)
Forming a capacitor dielectric film on the substrate so as to cover the exposed surface of the first conductor; (h) forming a cell plate electrode layer on the capacitor dielectric film; A) removing the cell plate electrode layer on the insulating layer; and (j) forming a wiring connected to a second conductor on the second connection terminal. Provided.

According to another aspect of the present invention, (a) a first semiconductor memory device having a first connection terminal and a peripheral circuit device having a second connection terminal are formed on a semiconductor substrate surface.
(B) forming first and second holes reaching the first and second connection terminals from the surface of the first insulating layer; and (c) forming the first and second holes. Forming first and second conductors in the first and second holes, and (d) covering the first and second conductors and forming a second on the first insulating layer.
Forming an insulating layer on the second insulating layer, and (e) forming a mask layer on the second insulating layer having an opening in a region including the semiconductor memory element and covering the peripheral circuit element. Using the mask layer as a mask, etching the second and first insulating layers in the opening to expose sidewalls of the first conductor; and (g) removing the first conductor from the first conductor. Forming a capacitor dielectric film on the substrate so as to cover the exposed surface; (h) forming a cell plate electrode layer on the capacitor dielectric film; and (i) forming the second insulating layer. There is provided a method for manufacturing a semiconductor device, comprising: a step of removing the above cell plate electrode layer; and (j) a step of forming a wiring connected to a second conductor on the second connection terminal.

According to still another aspect of the present invention, (a) a semiconductor substrate having a plurality of semiconductor memory elements each having a first connection terminal and a peripheral circuit element having a second connection terminal formed on a surface of a semiconductor substrate; Forming an insulating layer; and (b) a first step reaching the first and second connection terminals from a surface of the insulating layer.
And forming a second hole; and (c) forming the first and second holes.
Forming a first and a second conductor in the hole of (d);
Forming a mask layer on the insulating layer that is in contact with at least a top surface of at least a part of the first and second conductors and that has an opening in a region including the semiconductor memory element; (e)
Using the mask layer as a mask, etching the insulating layer in the opening to expose sidewalls of the first conductor, and (f) covering the exposed surface of the first conductor. Forming a capacitor dielectric film on the substrate,
(g) forming a cell plate electrode layer on the capacitor dielectric film; and (h) removing the cell plate electrode layer on the insulating layer. .

According to still another aspect of the present invention, a semiconductor substrate, a gate insulating film disposed on the semiconductor substrate, a gate electrode on the gate insulating film, and a first etch stopper covering an upper surface and side surfaces of the gate electrode A gate electrode structure comprising:
A first insulating layer for embedding the gate electrode structure;
A wiring structure including a wiring disposed on the insulating layer, a second etch stopper layer covering the top and side surfaces of the wiring, a second insulating layer embedding the wiring structure, and a second insulating layer embedded in the second insulating layer. An opening including a portion reaching the wiring through an etch stopper layer, a portion reaching the gate electrode through the first insulating layer and the first etch stopper layer, and the gate electrode formed in the opening; And a conductive connection member connected to the wiring.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a proposal made by the present inventor will be described with reference to the drawings. 15 (A), (B), FIG.
(C), (D), and FIG. 17 (E) are schematic cross-sectional views of a semiconductor substrate showing manufacturing steps of a semiconductor memory device proposed by the inventor earlier.

As shown in FIG. 15A, an element isolation silicon oxide layer 102 is formed by LOCOS on the surface of a semiconductor substrate 101 having a p-type surface region. The silicon oxide layer 102 defines a plurality of active regions on a semiconductor substrate surface.

A gate oxide film 103 is formed on the surface of the semiconductor substrate in each active region, and a gate electrode (word line) 104 is formed thereon using polycrystalline silicon, polycide, metal, or the like. The upper surface of the gate electrode has a silicon nitride layer 1
05. The silicon nitride layer 105 is patterned together with the gate electrode 104 and has the same shape. Using the silicon nitride layer 105 and the gate electrode 104 as a mask, an n-type impurity is ion-implanted into the surface of the semiconductor substrate 101 to form a lightly doped source / drain region 106. Thereafter, a silicon nitride layer is deposited on the entire surface of the semiconductor substrate, and is subjected to anisotropic etching, so that silicon nitride side spacers 107 are formed only on the side surfaces of the gate electrode structure.

If necessary, ions are further implanted after the formation of the side spacers 107 to form high-concentration source / drain regions. The transistor that has been subjected to the ion implantation twice is a transistor having an LDD structure.

After the transistor having the SAC structure is formed as described above, the insulating layer 111 such as silicon oxide is formed on the surface of the semiconductor substrate. An opening reaching a desired source / drain region is formed by forming a resist pattern on the surface of the insulating layer 111 and etching the insulating layer 111. An opening is formed at a position (not shown) for the right source / drain region of the right transistor. At this time, the silicon nitride film on the upper surface and the side surface of the gate electrode functions as an etch stopper, and forms a contact opening in a self-aligned manner.

A conductive layer of polycrystalline silicon or the like is deposited so as to fill the opening, and the conductive layer on the upper surface of the insulating layer 111 is removed by chemical mechanical polishing (CMP) or the like. Thus, a flat surface in which the conductive plug 112 is embedded is formed. In the figure, gate electrodes 104 arranged in parallel on the left side constitute a word line (WL) in a memory cell region. The transistors shown on the right side of the figure are transistors of the peripheral circuit. After forming another insulating film as necessary on the insulating layer 111, the bit line BL is formed.

FIG. 13A shows an example of the arrangement of the active region AR, word lines WL, and bit lines BL in the memory cell region. Each active region AR is long in the lateral direction and has source / drain regions at both left and right ends to which storage capacitors are connected. Source / drain regions to which bit lines are connected are formed at the center. In a region between these two types of source / drain regions, word lines WL are arranged in the vertical direction in the figure. That is, two memory cell transistors are formed in one active region AR, and the bit line BL is connected to the central common source / drain region. The bit line BL and the word line WL are arranged crossing on the surface of the semiconductor substrate.

Referring back to FIG. 15A, an opening for bit line contact is formed through the insulating layer, and a bit line is formed. The top and side surfaces of the bit line are also covered with the silicon nitride layer for SAC. Another insulating layer 116 is formed covering the bit line, and the surface thereof is planarized.

If necessary, a contact opening is formed in another insulating layer 116, and a conductive layer such as W is formed by filling the opening. After the formation of the conductive layer, the conductive layer on the upper surface of the insulating layer 116 is removed, and a flat surface in which the conductive plug 117 is embedded is formed. A silicon nitride film 120 for an etch stopper is formed on the entire flattened surface, and a thick insulating layer 121 such as silicon oxide is formed thereon.

A resist pattern is formed on the upper surface of the insulating layer 121, and the openings AP1, LG, AP2 are formed by etching.
Is formed. The openings AP1 each define a region for forming a storage capacitor.

The opening LG is formed in a loop shape covering the memory cell region. This loop shape is also called a bathtub because it surrounds the memory cell region in a bathtub shape. Opening A
P2 is an opening for connection wiring of the peripheral circuit transistor.

As shown in FIG. 15B, the Ru layer 122 and the W layer 12 are formed on the surface of the insulating layer 121 by filling the opening.
3 are sequentially deposited, and the inside of each opening is backfilled. The Ru layer 122a in the memory cell region becomes an electrode layer that forms a storage electrode of the memory cell. W layer 123a temporarily occupies a region where a cell plate electrode is to be formed.

The Ru layers 122b and 122c and the W layers 123b and 123 are simultaneously placed in the loop groove LG and the peripheral circuit opening AP2 simultaneously with the filling of the opening in the memory cell region.
c is deposited. After that, the Ru layer 122 and the W layer 123 deposited on the upper surface of the insulating layer 121 are removed by CMP or the like.

As shown in FIG. 16C, a mask layer 125 having an opening in the memory cell region is formed on the surface of the insulating layer 121. The mask layer 125 is a mask for removing the insulating layer 121 in the memory cell region, and can be formed of a resist having different etching characteristics from silicon oxide, silicon nitride patterned using the resist, polycrystalline silicon, or the like. The mask layer 125 is formed so as to cover a region outside the loop-shaped opening LG.

Using the mask layer 125 as an etching mask,
The insulating layer 121 in the memory cell region is removed by reactive ion etching (RIE) or wet etching using hydrofluoric acid or the like. Note that, when the insulating film 121 in the memory cell region is etched using anisotropic reactive ion etching (RIE), there is no need to worry about the spread of etching in the lateral direction. It is also possible to use silicon oxide. or,
W layer 12 burying the inner region of storage electrode 122a
3a is also removed. Thus, the inner surface and the outer surface of the storage electrode are exposed. Note that the silicon nitride layer 120 on the surface of the insulating layer 116 serves as an etching stopper, and the insulating layer 116 is not etched. In the loop-shaped opening LG, the buried metal layer functions as an etch stopper. The inner space of the Ru layer 122b is
The shape embedded by 3b is maintained. Similarly, in the peripheral circuit contact region, the Ru layer 122c and the W layer 123c filling the internal space constitute a pillar-shaped electrode plug.

As shown in FIG. 16D, the mask layer 12
5 is removed, a capacitor dielectric layer 127 such as Ta ₂ O ₅ is deposited on the substrate surface, and a cell plate (counter electrode) layer 128 is formed of a conductive material such as Ru or TiON. Thereafter, a resist mask 130 is formed on the upper surface of the cell plate layer 128, and the cell plate layer 128 is patterned by etching or the like to form a cell plate electrode 128a.
Create

As shown in FIG. 17E, the insulating layer 1 covers the patterned cell plate electrode 128a.
31 is formed, and the surface is flattened by etch back, CMP, or the like. A resist pattern is formed on the surface of the insulating layer 131, and a connection opening 132 is formed on a peripheral circuit pillar electrode or the like.

Thereafter, a wiring layer of Al or the like is formed, and the wiring 13 is formed by patterning using photolithography.
3,134 are formed. The wiring 133 is a Ru layer 122c,
It is connected to the source / drain of the peripheral transistor via a pillar or the like of the W layer 123c.

According to such a manufacturing process, since each wiring layer is formed on a flat surface, each wiring layer can be formed with high reliability. Further, since the conductive regions are sequentially formed upward with plugs, pillar electrodes, and the like, the height of the opening to which the wiring is to be connected can be limited, and the wiring can be formed reliably.

However, in order to further simplify the manufacturing process and form a DRAM at a low cost, it is desired to further simplify the manufacturing process. In particular, it is desired to reduce the number of masks used.

For example, a mask process is used once to remove the insulating layer around the storage electrode in the memory cell region, and once to pattern the cell plate electrode. If these steps can be performed with one mask, the manufacturing steps can be simplified.

If an insulating layer is formed after the cell plate electrode is formed, a step of flattening the surface is required. It is necessary to form an opening in the insulating layer for connecting a peripheral circuit or the like. One mask is used for forming the opening. If this mask can be shared with other processes, the manufacturing process can be simplified.

Further, the bit lines in the memory cell area need to be connected to the gate electrodes of the transistors constituting the sense amplifier in the peripheral circuit area. Each of the bit line and the gate electrode (word line) has a structure for SAC, and is covered with an etch stopper layer such as silicon nitride. Since the step of forming the contact hole of the bit line with respect to the source / drain region of the memory cell transistor is performed by the SAC step, the etch stopper layer cannot be etched. In order to form an opening in the etch stopper layer covering the upper surface of the gate electrode, a unique mask process is required. If this mask process can be simplified, the manufacturing process can be simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A, 1B, 2C,
(D) and FIG. 3 (E) show a DRA according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a substrate schematically showing a manufacturing process of M.

As shown in FIG. 1A, a transistor structure is formed in the surface region of the semiconductor substrate 1. Semiconductor substrate 1
A shallow trench is formed on the surface of the substrate in a shape defining an active region. Shallow trench isolation (STI) by backfilling the inside of the shallow trench with an insulating layer such as silicon oxide and removing the insulating film on the active region by CMP.
Region 2 is formed. Before or after the formation of the element isolation region 2, ion implantation is performed on the semiconductor substrate 1 to form a necessary well region. In the region where the n-channel MOS transistor is formed, a p-type impurity is ion-implanted into the surface of the semiconductor substrate to form a p-type well.

As shown in FIG. 13A, each active region A
R is surrounded by the element isolation region 2 and arranged in the vertical and horizontal directions. Note that the active regions adjacent in the vertical direction are:
They are arranged with a half pitch shift in the horizontal direction, to make effective use of the substrate area. Each active region AR is a region for forming two MOS transistors, and two word lines WL are formed thereon. The active region AR is a substantially rectangular region. Impurity ions are implanted into regions that are not covered by the word lines WL at both ends and at the center, thereby forming source / drain regions. On the source / drain region, a contact region 12 such as a polysilicon plug is formed as shown by a hatched broken line. The contact region on the central source / drain region is drawn upward in the figure to secure a contact region with the bit line BL. Bit line BL is arranged to extend in the horizontal direction in the figure.

Returning to FIG. 1A, a gate insulating film 3 such as a silicon oxide film is formed on the surface of the active region of the semiconductor substrate 1. A gate electrode layer 4 and a silicon nitride layer 5 are formed on the gate insulating film 3, a resist pattern is formed thereon, and the silicon nitride layer 5, the gate electrode layer 4, and the gate insulating film 3 are patterned all together. Using this gate electrode (word line) structure as a mask, n-type impurities are ion-implanted to form source / drain regions 6.

After the ion implantation, a silicon nitride layer is deposited on the entire surface of the substrate and anisotropically etched, so that silicon nitride side spacers 7 are formed only on the side surfaces of the gate electrode structure. That is, the gate electrode (word line)
4 has its upper surface covered with a silicon nitride layer 5,
The side surface is also covered by a silicon nitride side spacer 7.

An insulating layer 11 of silicon oxide or the like is formed so as to cover the gate electrode structure of the SAC structure, and the surface thereof is planarized. FIG. 13B shows an enlarged view of the gate electrode structure on the surface of the semiconductor substrate. After the surface of the insulating layer 11 is flattened, openings as shown by broken lines are formed as necessary, and a conductive layer for forming a contact plug 12 or the like such as a polycrystalline silicon layer by filling the opening is formed. . Etch back the conductive layer on the surface of the insulating layer 11, CMP
Thus, a flat surface is formed and the surface of the insulating layer 11 is exposed. Thus, a conductive plug 12 penetrating through the insulating layer 11 is formed as shown in FIG. Further, an insulating layer or the like such as a nitride film for insulating the conductive plug 12 is formed.

Another insulating layer such as silicon oxide is formed on the surface of the insulating layer such as a nitride film (these insulating films are collectively indicated by 16). Note that a bit line is formed in the insulating layer 16 by being buried. An opening is formed through the insulating layer 16, and a plug 17 is formed of a conductive material such as W.

FIG. 13C schematically shows an example of a bit line structure. An opening is formed in the insulating layer 16a, and a wiring pattern 13 for filling the opening and forming the bit line BL is formed on the insulating layer 16a. Note that a silicon nitride layer 14 is formed on the wiring layer 13 so as to be overlapped, and is simultaneously patterned. Thereafter, a silicon nitride layer is deposited on the entire surface and anisotropically etched to form
The side spacer 15 is left on the side surface. In this way,
The bit line 13 formed on the insulating layer 11 has a structure for SAC. After the formation of the bit line structure, an insulating layer 16b is formed, and its surface is planarized.

Note that the bit line needs to be connected to the gate electrode of the sense amplifier transistor. Incidentally, the bit line contact hole forming step is performed by a SAC step. Therefore, in the step of forming a contact hole for a bit line, it is impossible to make contact with the gate electrode through the silicon nitride film above the gate electrode.

FIG. 13D is a cross-sectional view showing a method of making contact from the bit line to the gate electrode of the sense amplifier transistor.

On the surface of the silicon substrate 1, a gate insulating film 3a of the sense amplifier transistor, a gate electrode 4a, and an etch stopper layer 5a of silicon nitride on the gate electrode are laminated, and are patterned into the same shape by photolithography. A silicon nitride side spacer 7a is formed on the side wall. This gate electrode structure is covered with insulating films 11 and 16a. Insulating film 11,
A bit line 13 is formed on 16a.
Are covered with silicon nitride films 14 and 15. An insulating layer 16b of silicon oxide or the like is formed to cover the bit line structure. On the insulating layer 16, a resist pattern PR1 having an opening in a region including the connection region of the bit line 13 and the gate electrode 4a of the sense amplifier transistor is formed.

Using resist pattern PR1 as a mask, etching is performed under etching conditions that can etch an oxide film and a nitride film in common. When the bit line 13 is exposed after the silicon nitride film 14 on the bit line 13 is etched, the etching hardly proceeds. In the region without the bit line 13, the etching passes through the insulating layers 16 and 11, and etches the silicon nitride film 5a on the gate electrode 4a. When the gate electrode 4a is exposed after the etching of the silicon nitride film 5a, the etching hardly proceeds. At this time, the sidewall 15 exposed at the opening (PR1) may be removed by etching or may remain without being removed by etching.

Thereafter, the bit line 13 and the gate electrode 4a are connected by removing the resist pattern PR1 and forming a wiring for filling the inside of the opening.

It should be noted that this etching does not use a unique mask, but can use a common mask for forming contact openings in other wiring layers. Therefore, it is possible to connect the upper and lower wirings of the SAC structure without increasing the number of masks.

Returning to FIG. 1A, the planarized insulating layer 1
An etch stop layer 20 of silicon nitride or the like and an insulating layer 21 of thick silicon oxide or the like are formed on the six surfaces. Insulating layer 2
A resist pattern is formed on one surface, and an opening AP1 for a storage electrode and a contact opening AP2 for a peripheral circuit are patterned. The storage electrode opening AP1 is arranged on a plug 17 connected to one of the source / drain regions of the memory cell transistor. The contact opening AP2 of the peripheral circuit is arranged on the plug 17 connected to the source / drain region of the transistor of the peripheral circuit.

At this time, a hard mask patterned with a resist may be used. The hard mask may be a conductor film or an insulator film. The removal may be performed at the time of patterning turning of the opening AP1, or may be performed in an appropriate subsequent step.

As shown in FIG. 1B, a Ru film 22 as an outer metal layer is deposited so as to cover the inner walls of the openings AP1 and AP2 formed in the insulating layer 21, and further the inner metal layer is buried in the recess. A resist layer or an inner layer 23 of SiO ₂ , SOG (spin-on glass) or the like is formed as a W layer or a simple padding. Thus, the opening AP1,
Fill back in AP2.

The main purpose of the inner layer 23 is to protect the inner wall of the outer metal layer. Therefore, the openings AP1 and AP2 need not be completely backfilled. When the inner layer 23 is formed of a conductive material such as a metal, the outer metal layer and the inner metal layer can be used as a conductor in a region other than the memory region such as the opening AP2 in the peripheral circuit region. Hereinafter, a case where the inner layer 23 is formed of W will be described unless otherwise specified.

Along with these steps, a Ru layer 22 and a W or resist layer 23 are also formed on the surface of the insulating layer 21. The electrode layer and the like on the surface of the insulating layer 21 are removed by etch back, CMP, or the like. In the memory cell region, a storage electrode 22a whose inner wall is protected by an inner layer 23a is formed, and in a peripheral circuit, a contact electrode is formed. In the peripheral circuit region, a combination of the outer metal layer 22c and the inner metal layer 23c can be used as the conductive pillar. To make a cylindrical electrode, the inner layer 23c may be a resist,
An insulator such as SiO ₂ or SOG may be used.

As shown in FIG. 2C, after removing the Ru layer 22 and the W layer 23 on the surface of the insulating layer 21, a resist pattern 25 having an opening on the memory cell region is formed.
Using this resist pattern 25 as a mask, the Ru layer 22a and the W layer 23a in the memory cell region are further etched. The opening AP
1, the upper surface of the Ru layer 22a and the W layer 23a is gradually moved downward. An upper surface of the insulating layer 21, a Ru layer 22a,
The etching is stopped when a sufficient difference in height from the upper surface of the W layer 23a occurs.

As shown in FIG. 2D, the insulating layer 21 exposed in the memory cell region is removed using the resist pattern 25 as a mask. For example, by reactive ion etching (RIE) or wet etching,
The insulating layer 21 exposed from the resist pattern 25 is removed by etching. Further, the W layer 23a occupying the internal space of the Ru layer 22a is also removed. Thus, the surface of the storage electrode 22a is exposed. Then resist pattern 25
Is removed.

As shown in FIG. 3 (E), a capacitor dielectric layer 27 such as Ta ₂ O ₅ is deposited on the exposed surfaces of the storage electrode 22a and the insulating layers 20 and 21, followed by Au and Ti.
A cell plate electrode layer is deposited by CVD using a conductive material such as N, TiON, SRO, Ru, Pt, W, and WN. A sufficiently thick cell plate electrode layer 28 is formed on the storage electrode 22a.
Is deposited, the cell plate electrode layer and the capacitor dielectric layer deposited on the surface of the insulating layer 21 are removed, and the capacitor dielectric layer 27 and the cell plate electrode 28 in the memory cell region are removed.
a remains. In addition, in the case of the drawing, a common plane of the insulating layer 21 and the cell plate electrode 28a is formed.

In some cases, the capacitor dielectric film 27 may be left on the insulating layer 21. The cell plate electrode 28a is connected to the storage electrode 2 via the dielectric layer 27.
It is only necessary to cover the surface of 2a, and it is not necessary to form a completely flat upper surface. After the formation of the cell plate electrode and the insulating layer, the insulating layer on the upper surface of the insulating layer 21 and the cell plate electrode layer may be removed. The cell plate electrode may be formed by laminating two or more conductive layers.

As shown in FIG. 3F, an insulating layer 41 such as a silicon oxide layer is formed to cover the cell plate electrode 28a and the insulating layer 21. After forming necessary contact holes by photolithography and etching, an upper wiring layer is formed. The upper wiring layers are patterned to form wirings 42a, 42
Obtain b. In the configuration shown in the figure, the wiring 42a is formed on the insulating layer 41 on the cell plate electrode 28a.
b is connected to a transistor in the peripheral circuit region via a plug-like electrode.

According to the above steps, the removal of the insulating layer in the memory cell region and the patterning of the cell plate electrode can be performed by using one resist mask 25. One mask can be omitted, and the manufacturing process of the DRAM is simplified.

The mask pattern 25 having an opening in the memory region may be a resist pattern, but a hard mask patterned using the resist pattern as a mask may be used. The hard mask may be a conductor film or an insulator film (for example, polysilicon, amorphous silicon, BS).
T, Ta ₂ O ₅ , nitride film or Al ₂ O ₃ film). If the hard mask is a conductor, it may be removed in an appropriate step after etching the insulator films 21 and 20 and before forming the multilayer wiring. When the hard mask is an insulator film, the hard mask can be left without being removed.

In the above embodiment, the height of the storage electrode was changed below the surface of the peripheral insulating layer. A similar effect can be obtained by increasing the surface of the insulating layer 21 around the memory cell region.

FIGS. 4A and 4B show a method of obtaining a common plane between the cell plate electrode and the insulating layer by forming an additional insulating layer on the insulating layer in the peripheral region.

As shown in FIG. 4 (A), following the state of FIG. 1 (B), SiO ₂ , SiN, Al ₂
Another insulating layer 26 such as O ₃ , Ta ₂ O ₅ , BST is further formed, a resist pattern 25 is formed thereon, and the insulating layer 26 is patterned. Using the resist pattern 25 and the insulating layer 26 as a mask, the insulating layer 2 in the memory cell region is used.
1. The inner layer 23a of W or SiO ₂ and resist is removed. After that, the resist pattern 25 is removed.

As shown in FIG. 4B, a capacitor dielectric film 27 and a cell plate electrode layer are formed on the surface of the semiconductor substrate, and the cell plate electrode layer deposited on the surface of the insulating layer 26 is removed by CMP or the like. Then, the cell plate electrode 28a is patterned. At this time, the surface of the insulating layer 26 and the surface of the cell plate electrode 28a form the same plane.

As in the above-described embodiment, the entire surface of the cell plate electrode 28a does not need to be a flat surface, and an insulating layer may be laminated on the cell plate electrode 28 and then planarized. Alternatively, the cell plate electrode may be formed using a stacked conductive layer.

Further, similarly to the process of FIG. 3F, when the cell plate electrode 28a is exposed, an insulating layer is formed to cover the cell plate electrode 28a and the insulating layer 26, and the lower wiring (contact) is formed. An opening for exposing the plug is formed, and an upper layer wiring is formed. Further, the above-described embodiment and this embodiment may be combined. For example, after patterning the insulating layer 26, the storage electrode may be dug down.

According to the above-described method, the removal of the insulating layer 21 in the memory cell region and the patterning of the cell plate electrode can be performed by using one resist mask 25.

In the above embodiment, when removing the insulating layer in the memory cell region, the insulating layer 21 under the mask is removed.
The sides are exposed. When the etching is performed by wet etching using HF or the like, side etching occurs below the mask. A configuration that enables more accurate removal of the insulating layer in the memory cell region will be described below.

As shown in FIG. 5A, a storage electrode opening AP1 is formed in the insulating layer 21, and a loop-shaped groove LG surrounding the memory cell region is formed. The groove LG is for forming a so-called bathtub structure around the memory cell area.

As shown in FIG. 5B, the Ru layer 22 and the W layer 23 are deposited as in the above-described embodiment, and the W layer and the Ru layer on the upper surface of the insulating layer 21 are removed by CMP or the like.
Flatten the surface. Here, the Ru layer 22b and the W layer 23b filling the inside of the loop groove have a shape surrounding the memory cell region and forming an enclosure (hereinafter referred to as a bathtub).

As shown in FIG. 6C, S
An insulating layer 26 such as iN or SiO ₂ is formed, and a resist pattern 25 having an opening in a memory cell region is formed thereon. The resist pattern 25 is formed in a shape that covers the surface of the loop-shaped opening LG. Note that the resist pattern 25 can perform its function if it extends to the inside of the outer periphery of the outer metal layer 22b in the loop opening LG.

Using the resist pattern 25 as a mask, the insulating layer 26 is patterned. The patterned insulating layer 26 is provided with a bathtub (Ru layer 22b,
At least a part of the surface of the W layer 23b) is covered. Using the resist pattern 25 and the insulating layer 26 as a mask, the insulating layer 21 and the W layer 23a in the memory cell region are removed. This removal step may be performed by either wet etching or dry etching. Since the bathtub walls of the Ru layer 22b and the W layer 23b are formed in the loop groove area LG, the insulating layer 21 outside the memory cell area is protected from etching. Note that the W layer 23b may be exposed and removed by etching.

As shown in FIG. 6D, formation of a capacitor dielectric film 27 similar to that shown in FIG.
8a is formed. Thereafter, an interlayer insulating film is further formed by a well-known technique, a connection hole is opened, a plug is buried if necessary, and an upper layer wiring is formed.

According to the present embodiment, the outer periphery of the memory cell region is defined by the bathtub (loop-shaped groove region), and after the cell plate electrode 28a is formed, a flattened plane common to the memory cell region and the peripheral region is formed. Provided.

In the above embodiment, only one MOS transistor is shown outside the memory cell region. In practice, various peripheral circuits are formed around the memory cell area.

FIG. 7A shows a case in which a loop-shaped bathtub surrounding the memory cell region and pillar-shaped electrodes for peripheral circuit transistors are formed simultaneously with the storage capacitor.
An opening AP1 for forming a storage electrode, a loop-shaped groove LG surrounding a memory cell region, and an opening AP2 for forming a peripheral electrode of a peripheral circuit transistor are formed in the insulating layer 21.

The opening AP1 for forming the storage electrode, the loop-shaped groove LG surrounding the memory cell region, and the opening AP2 for the contact plug of the peripheral circuit are desirably formed by the same exposure, but are formed by different exposures. You may. Also in this case, since the etching and the burying of the conductor film can be performed at the same time, the effect of shortening the process is somewhat reduced, but the whole is not damaged. Similarly, in some cases, etching can be performed separately. Also in this case, since the conductor can be buried together, the effect of shortening the process remains.

As shown in FIG. 7B, as in the above-described embodiment, a Ru layer 22 as an outer metal layer
A W layer 23 as an inner metal layer is deposited, and flattened by CMP or the like.

As shown in FIG. 8C, Si
After depositing an insulating layer such as O ₂ or SiN, a resist mask 25 is formed on the periphery of the memory cell region, and the insulating layer is patterned using the resist mask 25 to form an insulating layer 26 on the peripheral region. After that, the insulating layer 21 and the W layer 23a as the inner metal layer in the memory cell region are removed. After that, the resist pattern 25 is removed.

As shown in FIG. 8D, the dielectric film 27 for the capacitor is formed by the same steps as those shown in FIG.
And a cell plate electrode 28a. Outside the memory cell region, the Ru layer 22b and the W layer 23b of the bathtub surrounding the memory cell region under the insulating layer 26, and the Ru layer 22c as the outer metal layer and the inner metal layer on the plug for connecting the peripheral circuit transistor. The pillar-shaped electrode formed of the W layer 23c is formed by the storage electrode forming step. Note that a cylindrical electrode may be formed while leaving only the outer metal layer 22c.

In the above-described embodiment, a cylindrical capacitor is formed as a memory cell capacitor. However, it will be apparent to those skilled in the art that a pillar-shaped capacitor can be formed in a similar process. In this case, the opening may be filled with one kind of conductive material.

In the process of forming a capacitor for a memory cell, a state appears in which the storage electrode is supported only on the lower surface. In this state, the storage electrode may fall down.

FIGS. 9A, 9B and 10C are schematic sectional views showing an embodiment capable of preventing the storage electrode from falling down.

As shown in FIG. 9A, an opening AP1 for forming a storage electrode, an opening LG for forming a groove for a loop,
An opening AP2 for the peripheral circuit transistor is formed. After that, a conductive layer such as a Ru layer is deposited on the insulating layer 21 to fill the opening. By removing the conductive layer deposited on the surface of the insulating layer 21 by etching, CMP, or the like, the configuration shown in the figure is obtained.

In this configuration, the storage electrode is constituted by the pillar-shaped electrode 31a. Bathtub area 31
b, The peripheral circuit electrode 31c is also formed of a pillar-shaped electrode.

As shown in FIG. 9B, an insulating layer 26 having etching resistance to the etching of the SiN insulating layer 21 is formed on the surface of the insulating layer 21, and a resist pattern 25 is formed thereon. The resist pattern 25 is
Outside the memory cell region, an opening is provided on the connection electrode 31c of the peripheral circuit transistor. In the memory cell area, the resist pattern 25 does not expose the insulating layer 21 in the whole area, but on a part of the surface of each storage electrode,
The pattern is formed such that a part of the continuous insulating layer 26 remains. Using the resist pattern 25 as a mask, the insulating layer 26 is etched. Since each storage electrode is supported up and down, the occurrence of falling can be prevented.

When there is no or little possibility of the storage electrode falling down, a pattern in which the insulating layer 26 does not remain on some of the storage electrodes may be used. For example, the insulating layer 26 may be left only in the area where the upper wiring is formed in the memory cell area.

FIG. 14A shows a schematic top view in this state. The insulating layer 26 has an opening 26c above the pillar-shaped electrode 31c of the peripheral circuit. In the memory cell region, the insulating layer 26 exists on a part of the upper surface of each storage electrode.
Are formed only on a part of the memory cell region.
However, since the storage electrodes 31a are dispersedly arranged in a matrix, the insulating layer 21 around the storage electrodes 31a is continuous.

In this state, the insulating layer 21 is removed from the opening of the insulating layer 26. This removal is preferably performed by wet etching, but may be performed by dry etching as long as etching can be performed to some extent isotropically. For example, the insulating layer 21 of silicon oxide is removed by wet etching using HF. The insulating layer 21 is removed by etching through the opening 26a. Since the insulating layer 21 is continuous surrounding the storage electrode 31a, all the insulating layers 21 in the memory cell region are removed. Since the bathtub Ru layer 31b filling the loop groove region exists outside the memory cell region, the etching does not reach the outside of the memory cell region. Further, since the SiN film 20 exists below the insulating layer 21, the etching does not reach below the surface of the SiN film 20. Thus, only the insulating layer 21 in the memory cell region is removed. After that, the resist mask 25 is removed.

As shown in FIG. 10C, deposition of a capacitor dielectric film and formation of a cell plate electrode are performed in the same manner as in the above-described embodiment. By using a process such as CVD, the source gas enters the space where the insulating layer 21 is removed from the opening of the insulating layer 26, and the capacitor dielectric film 27 and the cell plate electrode 28a are deposited on the storage electrode 31a. After the cell plate electrode is sufficiently formed, the cell plate electrode layer deposited on the surface of the insulating layer 26 is removed by etch back, CMP, or the like. At this stage, a flat surface is formed.

As shown in FIG. 10C, another insulating layer 30 is formed on the surface of the insulating layer 26 and is patterned by photolithography. In the peripheral circuit region, an opening 30c is formed to match the pillar-shaped electrode and the opening 26c in the insulating layer 26 thereon. In the memory cell region, an opening 30a for forming a desired wiring layer on the insulating layer 26 is formed.

At the stage when the opening is formed in the insulating layer 30, the opening 26c in the insulating layer 26 is filled with the capacitor dielectric layer and the cell plate electrode layer. In this state,
A wiring cannot be connected to the pillar-shaped electrode 31c in the peripheral circuit region from above. Therefore, etching for removing the cell plate electrode layer and the capacitor dielectric layer is performed through the opening 30c formed in the insulating layer 30.

At this stage, since the cell plate electrode in the memory cell region is substantially covered with the insulating layers 26 and 30, etching hardly proceeds in the memory cell region. On the other hand, in the peripheral circuit region, since the opening 30c opens the opening 26c of the insulating layer 26 widely, the cell plate electrode layer and the capacitor dielectric layer formed in the opening 26c of the insulating layer 26 are effectively etched. Removed.

Thereafter, a conductive layer of Al, copper, or the like is deposited, and the conductive layer on the insulating layer 30 is removed by etch back, CMP, or the like, thereby forming a damascene wiring 32.

In the embodiment shown in FIGS. 9 and 10, the storage electrode is formed by a pillar electrode. A similar process can be performed using a cylindrical electrode.

FIG. 11A shows the state of FIG. 9A in which the opening is not backfilled with a single conductive layer, and the two conductive layers 22 are not filled.
23 shows a backfilled state.

FIG. 11B shows a resist mask 2 having a partial opening above the memory cell region, as in FIG. 9B.
5 shows a state in which the insulating layer 26 is used to remove the W layer 23a occupying the internal space of the insulating layer 21 and the Ru layer 22a in the memory cell region. In the peripheral circuit region, an opening is formed above the pillar-shaped electrode, and the W layer 23c filling the internal space of the Ru layer 22c is removed. After that, the resist mask 25 is removed.

FIG. 14B schematically shows the plan shape of the mask. An opening 26a in the memory cell area and an opening 26c in the peripheral circuit area are shown. In the peripheral circuit region, the opening 26c may expose only the surface of the Ru layer 22c. By adjusting the planar shape of the opening AP2 shown in FIG. 9A and / or the opening shape of the insulating layer 26 shown in FIG. 11B, an opening can be formed only on the Ru layer 22c. The W layer 23c may not be provided, and may be covered with the insulating layer 26.

FIG. 12C shows a state corresponding to FIG. The capacitor dielectric film 27 and the cell plate electrode 28a are deposited through the openings in the insulating layer 26. The deposit on the insulating layer 26 is removed by etch back, CMP, or the like. Thereafter, another insulating layer 30 is formed on the insulating layer 26, and an opening similar to the embodiment of FIGS.

The opening 2 is formed through the opening 30c in the peripheral circuit region.
After removing the capacitor dielectric layer and the cell plate electrode layer once formed in 6c, a new conductive layer 32 is formed by CVD.
Then, the conductive layer on the insulating layer 30 is removed by CMP or the like to form a damascene wiring 32.

According to the embodiments of FIGS. 9, 10, 11 and 12, the opening of the insulating layer 26 is simultaneously exposed by the insulating layer 30 serving as a mask for forming a wiring layer, and the cell plate electrode layer and the capacitor are formed. By removing the dielectric film, it becomes possible to connect a newly formed wiring layer and pillar-shaped (cylindrical) electrodes in the peripheral circuit region. In this way, the number of masks can be reduced, and the manufacturing process of the DRAM device can be simplified.

In the above-described embodiment, a DRAM device is manufactured. However, an FRAM device can be manufactured by changing a capacitor dielectric layer to a ferroelectric film. The outer metal layer and the inner metal layer may be conductive materials having different etching characteristics. Ru, Ru as the outer conductive layer
O, W, WN, SRO single layer, W / Ru, WN / Ru,
TiN / Ru, Ti / Ru, Cu / Ru, W / WN, T
iN / W, Ti / W, Cu / W, TiN / WN, Ti /
WN, Cu / WN, W / SRO, WN / SRO, Ti /
SRO, TiN / SRO, Cu / SRO, W / RuO,
WN / RuO, TiN / RuO, Ti / RuO, Cu /
RuO two-layer structure, W, TiN,
TiON, SRO, Ru, RuO, T as dielectric film
a ₂ O ₅ , BST, STO or the like can be used.

An opening may be formed through the insulating layer 16 when forming the storage electrode without forming the plug 17. That is, the outer metal layer 22 may be connected to the upper surface of the plug 12.

It will be obvious to those skilled in the art that various other modifications, improvements, and combinations are possible.

[0108]

As described above, according to the present invention,
A semiconductor device that is easy to manufacture is provided.

Further, a reliable semiconductor device can be manufactured with a small number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor substrate showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor substrate illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the semi-invention.

FIG. 5 is a schematic cross-sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a conductive substrate illustrating a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

FIG. 7 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a schematic sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a semiconductor substrate showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a schematic plan view and a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 14 is a schematic plan view for explaining an embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view of a semiconductor substrate for describing a proposal made by the present inventors.

FIG. 16 is a schematic cross-sectional view of a semiconductor substrate for explaining a proposal made by the present inventors.

FIG. 17 is a schematic cross-sectional view of a semiconductor substrate for describing a proposal made by the present inventors.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation region 3 gate insulating film 4 gate electrode (word line) 5 silicon nitride layer 6 source / drain region 7 silicon nitride side spacer 11, 16, 21, 26, 30 insulating layer 12, 17 conductive plug Reference Signs List 20 silicon nitride layer 22 outer metal layer 23 inner layer AP opening BL bit line WL word line 25 resist layer 31 storage electrode 32 wiring

Claims (5)

[Claims] (A) forming an insulating layer on a surface of a semiconductor substrate on which a semiconductor memory device having a first connection terminal and a peripheral circuit device having a second connection terminal are formed; Forming first and second holes reaching the first and second connection terminals from the surface of the insulating layer; and (c) first and second conductors in the first and second holes. Forming a mask layer on the insulating layer having an opening in a region including the semiconductor memory element and covering the peripheral circuit element; and (e) masking the mask layer. Etching the first conductor in the first hole in the opening and moving the top surface thereof below the surface of the insulating layer; and (f) using the mask layer as a mask, (G) exposing the side wall of the first conductor by etching the insulating layer inside the first conductor; Forming a capacitor dielectric film on the substrate to cover the exposed surface; (h) forming a cell plate electrode layer on the capacitor dielectric film; (i) forming a cell plate electrode layer on the insulating layer. A method of manufacturing a semiconductor device, comprising: a step of removing a cell plate electrode layer; and (j) a step of forming a wiring connected to a second conductor on the second connection terminal. (A) forming a first insulating layer on a surface of a semiconductor substrate on which a semiconductor memory element having a first connection terminal and a peripheral circuit element having a second connection terminal are formed; b) forming first and second holes reaching the first and second connection terminals from the surface of the first insulating layer; and (c) forming a first hole in the first and second holes. And (d) covering the first and second conductors and forming a second insulating layer on the first insulating layer, and (e) forming a second insulating layer on the first insulating layer. Forming a mask layer on the second insulating layer having an opening in a region including the semiconductor memory element and covering the peripheral circuit element; (f) using the mask layer as a mask, Second
And a step of exposing a side wall of the first conductor by etching the first insulating layer; and (g) a capacitor dielectric film on the substrate so as to cover an exposed surface of the first conductor. (H) forming a cell plate electrode layer on the capacitor dielectric film, (i) removing the cell plate electrode layer on the second insulating layer, (j) Forming a wiring connected to the second conductor on the second connection terminal. 3. The step (b) further comprises forming a loop-shaped groove surrounding a region including the semiconductor memory element,
The step (c) forms an enclosure of a conductor in the loop-shaped groove, the mask layer covers a region outside the loop-shaped groove, and the step (f) etches the enclosure of the conductor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed using the stopper. (A) forming an insulating layer on a surface of a semiconductor substrate on which a plurality of semiconductor memory elements each having a first connection terminal and a peripheral circuit element having a second connection terminal are formed; b) forming first and second holes reaching the first and second connection terminals from the surface of the insulating layer; and (c) forming first and second holes in the first and second holes. (D) insulating the mask layer which is in contact with the top surface of at least a part of the first and second conductors and has an opening in a region including the semiconductor memory element; (E) using the mask layer as a mask, etching the insulating layer to expose sidewalls of the first conductor, and (f) forming the first conductor. Forming a capacitor dielectric film on the substrate so as to cover the exposed surface; and (g) forming the capacitor dielectric film. Forming a cell plate electrode layer to the body layer, a method of manufacturing a semiconductor device comprising the steps of removing the cell plate electrode layer on the insulating layer (h). 5. A gate electrode structure comprising: a semiconductor substrate; a gate insulating film disposed on the semiconductor substrate; a gate electrode on the gate insulating film; and a first etch stopper layer covering top and side surfaces of the gate electrode. A wiring structure including: a first insulating layer in which the gate electrode structure is embedded; a wiring disposed on the first insulating layer; a second etch stopper layer covering an upper surface and a side surface of the wiring; A portion reaching the wiring from the surface of the second insulating layer through the second etch stopper layer; and a portion reaching the gate electrode through the first insulating layer and the first etch stopper layer. And a conductive connection member formed in the opening and connected to the gate electrode and the wiring.