JP2001185611A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which resolves a problem that a side wall of a lower part of an STI roughens due to lithography, plasma CVD, etc., during formation of an STI and a clearance is generated, silicon enters the clearance when a silicon layer is formed thereafter in the clearance, and the device does not function as a semiconductor. SOLUTION: In this manufacturing method, a second silicon oxide film 5 and a forth silicon oxide film 7 cover a side wall region and an upper region of a third silicon oxide film 6 completely even if a clearance is generated due to roughening of a side wall in a periphery of the third silicon oxide film 6, and amorphous silicon does not enter the clearance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an isolation region, and more particularly to a shallow trench isolation (STI).

[0002]

2. Description of the Related Art A conventional STI forming method will be described below. First, as shown in FIG.
The first silicon oxide film 22 having a thickness of about 10 nm
A first amorphous silicon film 23 (amorphous silicon film), a silicon nitride film 24, and a second silicon oxide film 25 are deposited. Next, as shown in FIG. 10, a photoresist is formed by a normal optical contact method, and a second silicon oxide film 2 is formed so as to form an STI formation planned portion.
5 Perform pattern processing on the surface. Further, using the photoresist as a mask, the silicon nitride film 24 and the second silicon oxide film 25 are selectively removed by RIE (reactive ion etching). Thereafter, the photoresist is removed by exposing the silicon substrate 21 in an O2 plasma atmosphere, and the amorphous silicon film 23 and the first silicon film 21 are selectively etched by using the second silicon oxide film 25 as a mask. The oxide film 22 and the silicon substrate 21 are removed in this order. As a result, an opening to be an STI formation planned region is formed. After that, the second silicon oxide film 25 is removed. Next, as shown in FIG.
When heated at 1000 ° C. in an atmosphere, silicon nitride 2
A third silicon oxide film 26 is formed on the silicon substrate 21, the first silicon oxide film 22, and the amorphous silicon film 23, which are the surfaces of the openings other than 4.

[0003] Thereafter, HDP (high density) is used.
y silicon) method to form a fourth silicon oxide film 27.
Is deposited. Furthermore, CMP (Chemical mec)
The fourth silicon oxide film 27 is flattened by a mechanical polish method. Thereafter, heating is performed in a nitrogen atmosphere at about 900 ° C. Next, as shown in FIG.
Immerse in an H4F solution, and adjust the height of the fourth oxide film 27 to 1
The silicon nitride 24 is removed by a phosphoric acid treatment at 50 ° C. Next, as shown in FIG. 12, a second amorphous silicon film 28 to which phosphorus is added is deposited by a low pressure CVD method. In this manufacturing method, when the second silicon oxide film 25 and the silicon nitride film 24 are subjected to RIE with an NH4F solution or the like,
Although the side wall is roughened due to the standing wave of lithography, a dense film is less likely to be formed when the roughened side wall is buried. For this reason, in the subsequent treatment with the NH 4 solution, a gap may be formed in the third silicon oxide film 26 around the portion where the side wall is rough, and after the silicon nitride film 24 is removed, the gap is exposed. In some cases. When depositing the second amorphous silicon film 28 with this gap exposed, the second amorphous silicon film 28 penetrates into the gap around the third silicon oxide film 26 and extends to the silicon substrate 21. The second amorphous silicon film 28
, The device has malfunctioned.

[0004]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a first silicon film, and a step of forming a second insulating film. And removing the second insulating film, the first silicon film, the first insulating film, and the semiconductor substrate along a region where an element isolation region is to be formed to form an opening. Forming a third insulating film on the surface of the opening, forming a fourth insulating film over the entire surface at least exceeding the height of the opening, and forming the fourth insulating film at least A step of etching and removing the third insulating film to a predetermined height on condition that the third insulating film forming the opening remains; and a step of leaving at least the third insulating film forming the opening in the second insulating film. Etching to the expected height, subject to , Characterized by comprising the step of forming the element isolation region covering the periphery of the third insulating film.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a process according to a first embodiment of the present invention will be described. The completed drawing is finally shown in FIG.
First, as shown in FIG. 2, a first silicon oxide film 2 of about 10 nm and a first silicon oxide film 2 of about 60 nm are formed on a silicon substrate 1.
The amorphous silicon film 3 and the second silicon oxide film 5 are sequentially deposited. Next, as shown in FIG. 3, the second silicon oxide film 5 excluding the region where the STI is to be formed is formed.
A resist is deposited on the surface, and the second silicon oxide film 5 is etched and removed by RIE using the resist as a mask. After that, the resist is removed by exposing the silicon substrate 1 in an O2 plasma atmosphere, and the amorphous silicon film 3 and the first silicon oxide film 3 are selectively etched by using the second silicon oxide film 5 as a mask. The film 2 and the silicon substrate 1 are removed in this order. As a result, an opening to be an STI formation planned region is formed. Next, as shown in FIG. 4, after removing the second silicon oxide film 5, O2
In an (oxygen) atmosphere, heated at about 1000 ° C. to about 6 nm
The third silicon oxide film 6 is formed. The manufacturing method up to this point is almost the same as the conventional technique. When the second silicon oxide film 5 is subjected to RIE to form an opening, side wall roughness occurs due to a standing wave of lithography on the side wall. It is difficult to adhere, and during the subsequent etching process using an NH4F solution, side wall roughness occurs on the side wall portion due to a standing wave of lithography.

Thereafter, when the third silicon oxide film 6 is formed, the third silicon oxide film 6 around the portion where the side wall is roughened is formed.
A gap is formed in the gap. The state of this gap is shown in FIG. 5, which is a top view of FIG. This gap is formed on the entire side wall of the opening. Here, A and A1 in FIG. 4 correspond to A and A1 in FIG.
It corresponds to. Next, as shown in FIG.
By a method, a fourth silicon oxide film 7 is deposited so as to fill the third silicon oxide film 6 formed on the surface of the opening. The fourth silicon oxide film 7 is deposited only to the extent that it exceeds at least the height of the second silicon oxide film 5 forming the opening. Next, as shown in FIG. 7, a mask is formed on the fourth silicon oxide film 7 with a resist so as to cover at least the entire width of the third silicon oxide film 6. The fourth silicon oxide film 7 and the second silicon oxide film 5 are sequentially etched. For this reason, even if a gap is formed around the third silicon oxide film 6 due to the roughness of the side wall, the fourth silicon oxide film 7 and the second silicon oxide film 5 entirely cover the periphery of the third silicon oxide film 6. The element isolation region covers the gap due to the roughened side wall.

The manufacturing method of the present invention is characterized in that it fills the gap due to the roughness of the side wall. For example, it becomes a T-shaped shape in FIG. 7 but becomes a sidewall-shaped shape as shown in FIG. Alternatively, the shape need not be limited. Next, as shown in FIG. 1, a second amorphous silicon film 10 to which phosphorus is added is deposited from the state of FIG. 7 by a low pressure CVD method. In this case, even if a gap is formed around the third silicon oxide film 6 due to roughness of the side wall, the second silicon oxide film 5 and the fourth silicon oxide film 7 are formed in the side region of the third silicon oxide film 6 and Since the upper region is completely covered, amorphous silicon does not enter the gap. Furthermore, since the opening is deposited by the plasma CVD method, even if the side surface of the opening is not substantially vertical, this manufacturing method covers the entire periphery of the third silicon oxide film 6, so that the gap is similarly formed in the gap. An STI having a structure in which crystalline silicon does not enter can be formed.

[0008]

According to the manufacturing method of the present invention, even if a gap is formed around the third silicon oxide film 6 due to side wall roughness, the second silicon oxide film 5 and the fourth silicon oxide film 7 remain Since the side surface region and the upper region of the silicon oxide film 6 are completely covered, amorphous silicon does not enter the gap.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 5 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 6 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 7 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 8 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 9 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 10 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 11 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

FIG. 12 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 1st silicon oxide film 3 1st amorphous (amorphous) silicon film 5 2nd silicon oxide film 6 3rd silicon oxide film 7 4th silicon oxide film 10 2nd amorphous Silicon film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F004 DA26 DB01 DB03 DB26 DB30 EA03 EA06 EB04 FA01 5F032 AA34 AA35 DA03 DA23 DA25 DA34 DA53 5F043 BB22 CC16 DD15 FF01 GG05

Claims (1)

[Claims] A step of forming a first insulating film on a semiconductor substrate; a step of forming a first silicon film; a step of forming a second insulating film; Forming an opening by removing the first silicon film, the first insulating film, and the semiconductor substrate along a region where an element isolation region is to be formed; and forming a third insulating film on the surface of the opening. Forming a fourth insulating film over the entire surface so as to exceed at least the height of the opening; and leaving the third insulating film forming at least the opening of the fourth insulating film. Etching the second insulating film to a predetermined height, on condition that at least a third insulating film forming an opening remains, on the condition that: Isolation region covering the periphery of the insulating film Forming a semiconductor device.