JP2001184023A - Display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of performing address discharge stably with a low voltage and its driving method. SOLUTION: In this display device, the barrier potential difference between a scanning electrode 12 and a sustaining electrode 13 is adjusted and, also, the barrier potential difference between the scanning electrode 12 and an address electrode 11 is adjusted independently from this adjustment by applying a setup pulse SP to the scanning electrode 12 and by applying a setup pulse ST to the sustaining electrode 13 in a setup period prior to a first subfield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device for displaying an image by controlling discharge and a driving method thereof.

[0002]

2. Description of the Related Art PDP (Plasma Display Panel)
Is advantageous in that it can be made thinner and have a larger screen. In this plasma display device, an image is displayed by utilizing light emission at the time of gas discharge.

FIG. 16 is a schematic diagram mainly showing a configuration of a PDP of a conventional plasma display device.

As shown in FIG. 16, the PDP 1 includes a plurality of address electrodes 11, a plurality of scan electrodes 12, and a plurality of sustain electrodes 13. Multiple address electrodes 11
Are arranged in the vertical direction of the screen, and a plurality of scan electrodes 1
The two and a plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are commonly connected. Address electrode 11, scan electrode 12
A discharge cell is formed at each intersection of the sustain electrode 13. Each discharge cell forms a pixel on the screen.

[0005] An address driver 202 drives a plurality of address electrodes 11 according to image data. The scan driver 203 drives the plurality of scan electrodes 12 in order. The sustain driver 204 drives the plurality of sustain electrodes 13 in common.

FIG. 17 is a schematic sectional view of a three-electrode surface discharge cell in an AC type PDP. In the discharge cell 14 shown in FIG. 17, a pair of scan electrode 12 and sustain electrode 13 are formed on the front glass substrate 101 in the horizontal direction of the screen, and the scan electrode 12 and the sustain electrode 13 are formed of a transparent dielectric layer. 102 and protective layer 1
03. On the other hand, the surface glass substrate 101
The address electrode 1 is formed on the back glass substrate 104 facing the
1 is formed in the vertical direction of the screen, and a transparent dielectric layer 105 is formed on the address electrode 11. A phosphor 106 is applied on the transparent dielectric layer 105.

In the discharge cell 14, the address electrode 11
An address discharge is generated between the address electrode 11 and the scan electrode 12 by applying a write pulse between the address electrode 11 and the scan electrode 12. Then, the scan electrode 12
The sustain discharge is performed between the scan electrode 12 and the sustain electrode 13 by applying a periodic sustain pulse that is alternately inverted between the scan electrode 12 and the sustain electrode 13.

As a gradation display driving method in an AC type PDP, an ADS (Address and Display-period Separat) is used.
ed; address / display period separation) method is used.
FIG. 18 is a diagram for explaining the ADS method. FIG.
The vertical axis of 8 indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.

In the ADS system, one field (1/60)
(Seconds = 16.67 ms) is temporally divided into a plurality of subfields. For example, when performing 256 gradation display with 8 bits, one field is divided into eight subfields. Each subfield is divided into an address period in which an address discharge for selecting a lighting cell is performed and a sustain period in which a sustain discharge for display is performed.

In the example of FIG. 18, one field is temporally divided into four subfields SF1 to SF4. Subfield SF1 is divided into an address period AD1 and a sustain period SUS1, subfield SF2 is divided into an address period AD2 and a sustain period SUS2, and subfield SF3 is divided into an address period AD3 and a sustain period S1.
The subfield SF4 is divided into an address period AD4 and a sustain period SUS4.

[0011] In the ADS system, the first in each subfield
Scanning by address discharge is performed on the entire surface of the PDP from the line to the m-th line, and sustain discharge is performed at the end of the address discharge on the entire surface. That is, the sustain period is set to a period excluding the address period. Therefore, the ratio of the sustaining period in one field is as small as about 30%, and there is a limit to increasing the luminance.

In order to increase the brightness of the PDP,
Address and sustain simultaneous drive method (IEICE: TECHNI
CAL REPORT OF IEICE.EID96-71, ED96-149, SDM96-175 (19
97-01), pp-19-24) have been proposed. FIG. 19 is a diagram for explaining the address / sustain simultaneous driving method. The vertical axis in FIG. 19 indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.

In the address / sustain simultaneous driving method,
The sustain discharge is started after the address discharge for each line. In the example of FIG. 19, one field is temporally divided into four subfields SF1 to SF4, and each of the subfields SF1 to SF4 has an address period AD1 to AD4.
AD4 and sustain periods SUS1 to SUS4.

In each of the subfields SF1 to SF4, sustain periods SUS1 to SUS4 are set for each line following the address periods AD1 to AD4. Therefore, almost all of the fields are in the sustain period, and high luminance can be achieved.

FIG. 20 is a timing chart showing the drive voltage of each electrode according to the conventional simultaneous address and sustain drive method. In FIG. 20, the sustain electrode 13 and the n-th
The drive voltages of the scan electrode 12 and the address electrode 11 in the (line) to (n + 3) th lines are shown. Here, n is an arbitrary integer.

In FIG. 20, a sustain pulse Psu is applied to the sustain electrode 13 at a constant period.
During the address period, a write pulse Pw is applied to the scan electrode 12. A write pulse Pwa is applied to the address electrode 11 in synchronization with the write pulse Pw. Write pulse Pw applied to scan electrode 12
Changes from 210V to 0V and returns to 210V, and the write pulse Pwa applied to the address electrode 11 becomes 21V.
It changes from 0V to 340V and returns to 210V. As a result, a voltage of 340 V is applied between the scan electrode 12 and the address electrode 11 as an address discharge voltage.

The ON / OFF of the write pulse Pwa applied to the address electrode 11 is controlled according to each pixel of an image to be displayed. When the write pulse Pw and the write pulse Pwa are applied simultaneously, an address discharge occurs at a discharge cell at the intersection of the scan electrode 12 and the address electrode 11, and the discharge cell is turned on.

In the sustain period after the address period, a sustain pulse Psc is applied to the scan electrode 12 at a constant period.
The phase of the sustain pulse Psc applied to the scan electrode 12 is shifted from the phase of the sustain pulse Psu applied to the sustain electrode 13 by 180 degrees. in this case,
Sustain discharge occurs only in the discharge cells lit by the address discharge.

At the end of each subfield, an erase pulse Pe is applied to the scan electrode 12. Thereby,
The wall charge of each discharge cell disappears, and the sustain discharge ends. After application of the erasing pulse Pe, before the start of the next subfield, the pause pulse Pr is applied to the scan electrode 12 at a constant period.
Is applied. A period from the application of the erasing pulse Pe to the start of the next subfield is called a pause period.

[0020]

As described above, in the conventional PDP device, the scan electrode 12 is held at the ground potential by the write pulse Pw during the address period.
A positive write pulse Pwa is applied to the address electrode 11, and the voltage of the write pulse Pw and the write pulse Pw
The voltage obtained by adding the voltage of “a” is applied between the address electrode 11 and the scan electrode 12 as an address discharge voltage. For this reason, the voltage to be applied to the address electrode 11 becomes extremely large, and as the number of discharge cells constituting a pixel for displaying a high-definition image increases, a larger number of write pulses Pwa are applied. Increase the power consumption of the PDP device. In addition, it is difficult to integrate a driving circuit that can withstand such a high voltage by using a normal manufacturing process.

Also, "A New High Speed Driving Method"
for ac-PDP "(Technical Report of IEICE.
EID98-261 (1999-03), pp-147-150) includes a method for adjusting a wall potential difference between a scan electrode and a sustain electrode.
It is disclosed that a setup period is provided once in a field. However, such adjustment of the wall potential difference between the scan electrode and the sustain electrode alone cannot adjust the wall potential difference sufficiently suitable for the address discharge performed between the address electrode and the scan electrode. Address discharge cannot be performed stably with voltage.

An object of the present invention is to provide a display device capable of stably performing an address discharge at a low voltage and a driving method thereof.

[0023]

Means for Solving the Problems (1) First invention A display device according to a first invention has a plurality of first electrodes arranged in a first direction and a first electrode intersecting the first direction. A plurality of second electrodes arranged in two directions, a plurality of third electrodes arranged to be paired with the plurality of first electrodes, and a first electrode and a second electrode. Prior to the address discharge, the wall potential difference between the first electrode and the third electrode is adjusted, and the first potential is adjusted independently of the adjustment of the wall potential difference between the first electrode and the third electrode. Adjusting means for adjusting the wall potential difference between the electrode and the second electrode.

In the display device according to the present invention, the wall potential difference between the first electrode and the third electrode is adjusted before the address discharge, and the first electrode and the second electrode are adjusted independently of this adjustment. Since the wall potential difference between the first electrode and the second electrode is adjusted,
The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be adjusted to desired values with high accuracy. Therefore, the wall charges formed on the first to third electrodes can be adjusted to an optimum state for the address discharge, and the address discharge can be stably performed at a low voltage.

(2) Second invention In the display device according to the second invention, in the configuration of the display device according to the first invention, the adjusting means is arranged such that, in the setup period before the address period in which the address discharge is performed, First
The wall potential difference between the first electrode and the third electrode is adjusted, and the adjustment of the wall potential difference between the first electrode and the third electrode is performed independently of the adjustment of the wall potential difference between the first electrode and the second electrode. And setup adjustment means for adjusting the wall potential difference between the two.

In this case, the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode are adjusted during the setup period before the address period. Therefore, the address discharge can be performed immediately after the adjustment of the wall charge, and the address discharge can be performed in a state more suitable for the address discharge without being affected by disturbance or the like.

(3) Third invention In the display device according to the third invention, in the configuration of the display device according to the second invention, the setup adjusting means includes a device between the first electrode and the third electrode, and By causing the first and second weak discharges not to interfere with each other between the first electrode and the second electrode, respectively, the first and second weak discharges are performed between the first and third electrodes and between the first and second electrodes. A wall charge accumulating means for accumulating wall charges between the first and third electrodes, and a third weak discharge having a polarity opposite to that of the first weak discharge between the first electrode and the third electrode. The wall charge between the first electrode and the third electrode is reduced, and a second weak discharge having a polarity opposite to that of the second weak discharge is provided between the first electrode and the second electrode during a period different from the third weak discharge. Wall charge reduction means for reducing the wall charge between the first electrode and the second electrode by causing the weak discharge of (4). Is included.

In this case, the wall charges are gradually accumulated between the first electrode and the third electrode and between the first electrode and the second electrode by weak discharges that do not interfere with each other, and then the first discharge is performed. The wall charge between the first electrode and the third electrode can be gradually reduced, and separately from this, the wall charge between the first electrode and the second electrode can be gradually reduced. Therefore, the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be finely adjusted independently of each other. The wall potential difference between the electrodes can be set to a state suitable for address discharge. Further, since only weak light emission is generated in the weak discharge, the luminance level of black display does not increase and the contrast of the display screen does not deteriorate.

(4) Fourth Invention In a display device according to a fourth invention, in the configuration of the display device according to the first invention, the adjusting means is arranged such that the adjusting means is arranged so that, in a setup period before an address period in which an address discharge is performed, First
First adjusting means for adjusting a wall potential difference between the first electrode and the second electrode, and an erasing discharge for stopping a sustain discharge performed after the address period. Second adjusting means for adjusting the wall potential difference.

In this case, the adjustment of the wall potential difference between the first electrode and the second electrode is performed in the setup period before the address period, and the adjustment of the wall potential difference between the first electrode and the third electrode is performed. Since the adjustment can be performed by the erase discharge after the address period, each adjustment can be performed with high accuracy without being affected by the discharge by the other adjustment, and a state more suitable for the address discharge can be achieved with higher accuracy. can do.

(5) Fifth Invention A display device according to a fifth invention is the display device according to any one of the first to fourth inventions, wherein the first adjusting means comprises a first electrode and a first electrode. Wall charge accumulating means for accumulating wall charges between the first electrode and the second electrode by causing a weak discharge that does not interfere with the second electrode; A wall charge reduction means for reducing a wall charge between the first electrode and the second electrode by causing a weak discharge having a polarity opposite to that of the weak discharge between the first and second electrodes. The means includes an erase pulse applying means for changing an erase pulse applied to the first electrode to adjust a wall potential difference between the first electrode and the third electrode.

In this case, the wall charge is gradually accumulated between the first electrode and the second electrode by a weak discharge that does not interfere with the other, and then the wall charge between the first electrode and the second electrode is reduced. A method for gradually reducing the electric charge and finely adjusting the wall potential difference between the first electrode and the second electrode without affecting the other, and changing the erase pulse applied to the first electrode. Thereby, the wall potential difference between the first electrode and the third electrode can be adjusted. Therefore, the wall potential difference between the first electrode and the second electrode and the wall potential difference between the first electrode and the third electrode can be independently adjusted,
A state suitable for address discharge can be achieved with higher accuracy. In addition, since the adjustment of the wall potential difference between the first electrode and the third electrode is performed by changing the erase pulse applied to the first electrode, the first electrode and the third electrode have a simple configuration. Adjustment of the wall potential difference between the electrodes can be performed. Further, in the weak discharge in the adjustment of the wall potential difference between the first electrode and the second electrode, only a very weak light emission is generated, so that the brightness level of the black display does not increase and the contrast of the display screen is reduced. Does not worsen.

(6) Sixth invention A display device according to a sixth invention is the display device according to the third or fifth invention, wherein the wall charge accumulation means and the wall charge reduction means have a ramp waveform. First drive pulse
A weak discharge is generated by applying a voltage to the electrodes.

In this case, since the weak discharge can be stably performed by the ramp waveform changing at a constant speed, the adjustment of the wall potential difference can be performed more stably.

(7) Seventh Invention In the display device according to the seventh invention, in the configuration of the display device according to the third or fifth invention, the wall charge accumulating unit and the wall charge reducing unit are configured to set a discharge starting voltage. A weak discharge is generated by applying a drive pulse having a waveform that changes sharply within a range that does not exceed the range and thereafter changes gradually to the first electrode.

In this case, a weak discharge can be generated by abruptly changing the drive pulse within a range not exceeding the discharge start voltage, and then gradually changing the drive pulse. Can be reduced, and the adjustment of the wall potential difference can be stably performed in a shorter adjustment period.

(8) Eighth Invention In the display device according to the eighth invention, in the configuration of the display device according to the third or fifth invention, the wall charge accumulating means and the wall charge reducing means have an exponential function. A weak discharge is generated by applying a drive pulse having a waveform whose change amount decreases to the first electrode.

In this case, the waveform is reduced exponentially so that the time is reduced by sharply changing the time when no weak discharge is generated, and gradually changed during the weak discharge. Because it can be performed stably,
The wall potential difference can be stably adjusted in a shorter adjustment period, and a charge / discharge waveform using a capacitor, a resistor, or the like can be used, and the circuit configuration can be further simplified.

(9) Ninth Invention A display device according to a ninth invention is the display device according to any one of the first to eighth inventions, wherein each of the first electrodes is used to perform gradation display. Subfield dividing means for temporally dividing each of the fields set in the plurality of subfields into a plurality of subfields, wherein the adjusting means adjusts the distance between the first electrode and the third electrode by the adjusting means among the plurality of subfields. Wall potential difference between the first electrode and the third electrode and the first electrode at the beginning of the subfield immediately after the wall potential difference between the first electrode and the second electrode are adjusted. Potential difference between the first and third electrodes and the wall potential difference between the first and third electrodes and the wall between the first and second electrodes at the beginning of the other subfields The first electrode and the second electrode are set so that the potential difference is equal. It adjusts the wall potential difference between the first and second electrodes and the wall potential difference between the first electrode and the second electrode.

In this case, of the first electrode and the third electrode, the wall potential difference in the subfield immediately after the wall potential difference is adjusted among the plurality of subfields is equal to the wall potential difference in the other subfields. Since the wall potential difference between the electrodes and the wall potential difference between the first electrode and the second electrode are adjusted, the wall potential differences in all subfields can be made uniform. Accordingly, even if it is difficult to divide each field into a plurality of subfields for each first electrode and perform gradation display, and to provide a wall charge adjustment period for each subfield, it is difficult to provide a grayscale display for each subfield. The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be adjusted to an optimum state for the address discharge. It can be performed stably.

(10) Tenth invention A display device according to a tenth invention is the display device according to any one of the first to ninth inventions, wherein the first electrode is provided in an address period during which an address discharge is performed. First voltage applying means for applying a first pulse voltage of a predetermined polarity to
A second voltage application for applying a second pulse voltage having a polarity opposite to that of the first pulse voltage to the second electrode according to image data when the first pulse voltage is applied to the first electrode; Means, and third voltage applying means for applying a third voltage having a polarity opposite to the first pulse voltage to the third electrode during the address period, wherein the adjusting means comprises a first pulse voltage and a third voltage. No discharge occurs between the first electrode and the third electrode even when only the first voltage is applied, and the first electrode and the second electrode are applied by applying the first pulse voltage and the second pulse voltage.
Address discharge between the first electrode and the third electrode.
A wall potential difference between the first electrode and the third electrode and a wall potential difference between the first electrode and the second electrode so that a discharge is induced between the first electrode and the second electrode. is there.

In this case, even if only the first pulse voltage and the third voltage are applied, no discharge occurs between the first electrode and the third electrode, and the first pulse voltage and the third voltage are not applied. 2
The first electrode and the third electrode so that a discharge is induced between the first electrode and the third electrode only by an address discharge between the first electrode and the second electrode due to the application of the pulse voltage. Since the wall potential difference between the third and third electrodes and the wall potential difference between the first and second electrodes are adjusted, the minimum necessary wall charges suitable for address discharge can be stably formed. ,
The applied voltage required for the address discharge can be set to the minimum required. Also, since voltages having different polarities are applied to the first and second electrodes, the absolute value of the voltage of the first pulse voltage and the second voltage are applied between the first and second electrodes. A voltage obtained by adding the absolute value of the pulse voltage to the voltage is applied, and the voltage applied to the first and second electrodes can be further reduced. Therefore, discharge can be performed with a small voltage, so that power consumption can be reduced, and the withstand voltage of a circuit that generates the first and second pulse voltages can be reduced. It becomes possible to integrate.

(11) Eleventh Invention A method for driving a display device according to an eleventh invention is directed to a method of driving a display device, comprising: a plurality of first electrodes arranged in a first direction; and a second direction intersecting the first direction. And a plurality of third electrodes arranged to be paired with the plurality of first electrodes, respectively, comprising: a first electrode; Before the address discharge by the first and second electrodes, the wall potential difference between the first electrode and the third electrode is adjusted, and the wall potential difference between the first electrode and the third electrode is adjusted. Independently of the wall potential difference between the first electrode and the second electrode.

In the display device according to the present invention, the wall potential difference between the first electrode and the third electrode is adjusted before the address discharge, and the first electrode and the second electrode are independently controlled by this adjustment. Since the wall potential difference between the first electrode and the second electrode is adjusted,
The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be adjusted to desired values with high accuracy. Therefore, the wall charges formed on the first to third electrodes can be adjusted to an optimum state for the address discharge, and the address discharge can be stably performed at a low voltage.

(12) Twelfth Invention According to a twelfth invention, in a method for driving a display device according to the eleventh invention, in the method for driving a display device according to the twelfth invention, the adjusting step is performed before the address period in which the address discharge is performed. During the setup period, the wall potential difference between the first electrode and the third electrode is adjusted, and the wall potential difference between the first electrode and the third electrode is adjusted independently of the adjustment of the wall potential difference between the first electrode and the third electrode. Adjusting the wall potential difference between the second electrode and the second electrode.

In this case, the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode are adjusted during the setup period before the address period. Therefore, the address discharge can be performed immediately after the adjustment of the wall charge, and the address discharge can be performed in a state more suitable for the address discharge without being affected by disturbance or the like.

(13) Thirteenth Invention According to a thirteenth invention, in a method for driving a display device according to the twelfth invention, in the method for driving a display device according to the twelfth invention, the adjusting step in the setup period comprises the steps of: Between the first and third electrodes and between the first and third electrodes by causing first and second weak discharges not to interfere with each other between the first and third electrodes and between the first and second electrodes, respectively. Accumulating wall charge between the first electrode and the second electrode;
By causing a third weak discharge having a polarity opposite to that of the first weak discharge to be performed between the first electrode and the third electrode, a wall charge between the first electrode and the third electrode is reduced. The fourth weak discharge having a polarity opposite to that of the second weak discharge is performed between the first electrode and the second electrode during a period different from that of the third weak discharge, so that the first electrode and the second weak discharge are generated. Reducing wall charges between the electrodes.

In this case, the wall charges are gradually accumulated between the first electrode and the third electrode and between the first electrode and the second electrode by weak discharges that do not interfere with each other, and then the first discharge is performed. The wall charge between the first electrode and the third electrode can be gradually reduced, and separately from this, the wall charge between the first electrode and the second electrode can be gradually reduced. Therefore, the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be finely adjusted independently of each other. The wall potential difference between the electrodes can be set to a state suitable for address discharge. Further, since only weak light emission is generated in the weak discharge, the luminance level of black display does not increase and the contrast of the display screen does not deteriorate.

(14) Fourteenth Invention A method for driving a display device according to a fourteenth invention is directed to the method for driving a display device according to the eleventh invention, wherein the adjusting step is performed before the address period in which the address discharge is performed. Adjusting a wall potential difference between the first electrode and the second electrode during the setup period; and erasing the first electrode and the third electrode by an erasing discharge for stopping a sustain discharge performed after the address period. Adjusting the wall potential difference between them.

In this case, the adjustment of the wall potential difference between the first electrode and the second electrode is performed in the setup period before the address period, and the adjustment of the wall potential difference between the first electrode and the third electrode is performed. Since the adjustment can be performed by the erase discharge after the address period, each adjustment can be performed with high accuracy without being affected by the discharge by the other adjustment, and a state more suitable for the address discharge can be achieved with higher accuracy. can do.

(15) Fifteenth Invention A method for driving a display device according to a fifteenth invention is the same as the method for driving a display device according to the fourteenth invention, except that
The adjusting step of the first electrode is performed by causing a weak discharge that does not interfere with the other between the first electrode and the second electrode.
Accumulating wall charges between the first electrode and the second electrode; and causing the weak discharge having a polarity opposite to that of the weak discharge to occur between the first electrode and the second electrode. And the second
Reducing wall charge between the electrodes of
The step of adjusting the first and third electrodes includes adjusting the wall potential difference between the first electrode and the third electrode by changing an erase pulse applied to the first electrode.

In this case, the wall charge is gradually accumulated between the first electrode and the second electrode by a weak discharge that does not interfere with the other, and then the wall charge between the first electrode and the second electrode is reduced. A method for gradually reducing the electric charge and finely adjusting the wall potential difference between the first electrode and the second electrode without affecting the other, and changing the erase pulse applied to the first electrode. Thereby, the wall potential difference between the first electrode and the third electrode can be adjusted. Therefore, the wall potential difference between the first electrode and the second electrode and the wall potential difference between the first electrode and the third electrode can be independently adjusted,
A state suitable for address discharge can be achieved with higher accuracy. In addition, since the adjustment of the wall potential difference between the first electrode and the third electrode is performed by changing the erase pulse applied to the first electrode, the first electrode and the third electrode are adjusted in a simple manner. Adjustment of the wall potential difference between the electrodes can be performed. Further, in the weak discharge in the adjustment of the wall potential difference between the first electrode and the second electrode, only a very weak light emission is generated, so that the brightness level of the black display does not increase and the contrast of the display screen is reduced. Does not worsen.

(16) Sixteenth Invention A method for driving a display device according to a sixteenth aspect of the present invention is the method for driving a display device according to the thirteenth or fifteenth aspect, wherein the wall charge accumulating step and the wall charge decreasing step comprise: The method includes a step of generating a weak discharge by applying a drive pulse having a ramp waveform to the first electrode.

In this case, since the weak discharge can be stably performed by the ramp waveform, the wall potential difference can be adjusted more stably.

(17) Seventeenth Invention A method for driving a display device according to a seventeenth aspect of the present invention is the method for driving a display device according to the thirteenth or fifteenth aspect, wherein the wall charge accumulating step and the wall charge decreasing step comprise: The method includes a step of generating a weak discharge by applying a drive pulse having a waveform that changes steeply within a range not exceeding the discharge start voltage and then changes gradually to the first electrode.

In this case, a weak discharge can be generated by rapidly changing the drive pulse within a range not exceeding the discharge start voltage, and then gradually changing the drive pulse. Can be reduced, and the adjustment of the wall potential difference can be stably performed in a shorter adjustment period.

(18) Eighteenth Invention The display device driving method according to an eighteenth aspect of the present invention is the display device driving method according to the thirteenth or fifteenth aspect, wherein the wall charge accumulating step and the wall charge decreasing step comprise: A driving pulse having a waveform whose change amount decreases exponentially is set to a first pulse.
And generating a weak discharge by applying to the electrodes.

In this case, the waveform is reduced exponentially, so that the time is reduced by sharply changing the time when no weak discharge occurs, and gradually changed during the weak discharge. Because it can be performed stably,
Adjustment of the wall potential difference can be performed more stably in a shorter adjustment period.

(19) Nineteenth Invention A method for driving a display device according to the nineteenth invention is the same as the method for driving a display device according to any one of the eleventh to eighteenth inventions, except that the display device performs the grayscale display. The method further includes the step of temporally dividing each field set for each one electrode into a plurality of subfields, wherein the adjusting step includes a step of dividing a wall between the first electrode and the third electrode among the plurality of subfields. Immediately after the potential difference and the wall potential difference between the first electrode and the second electrode are adjusted, the wall potential difference between the first electrode and the third electrode and the first electrode and the third electrode at the beginning of the subfield immediately after the adjustment. The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the third electrode at the beginning of the other subfields. So that the first electrode and the Adjusting the wall potential difference between the third electrode and the first electrode and the second electrode.

In this case, of the first electrode and the third electrode, the wall potential difference in the subfield immediately after the wall potential difference is adjusted among the plurality of subfields is the same as the wall potential difference in the other subfields. Since the wall potential difference between the first and second electrodes and the wall potential difference between the first and second electrodes are adjusted, the wall potential difference in all subfields can be made uniform. Accordingly, even if it is difficult to divide each field into a plurality of subfields for each first electrode and perform gradation display, and to provide a wall charge adjustment period for each subfield, it is difficult to provide a grayscale display for each subfield. The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode can be adjusted to an optimum state for the address discharge. It can be performed stably.

(20) Twentieth invention The drive method of a display device according to the twentieth invention is the same as the drive method of the display device according to any one of the first to nineteenth inventions, except that the address period during which the address discharge is performed is performed. First
Applying a first pulse voltage having a predetermined polarity to the first electrode, and a second pulse voltage having a polarity opposite to the first pulse voltage when the first pulse voltage is being applied to the first electrode. To the second electrode according to the image data, and applying a third voltage having a polarity opposite to that of the first pulse voltage to the third electrode during the address period. Even if only the first pulse voltage and the third voltage are applied, no discharge occurs between the first electrode and the third electrode, and the first pulse voltage and the second
The first electrode and the third electrode are so generated that a discharge is induced between the first and third electrodes by an address discharge between the first and second electrodes due to the application of the pulse voltage. And a wall potential difference between the first electrode and the second electrode.

In this case, even if only the first pulse voltage and the third voltage are applied, no discharge occurs between the first electrode and the third electrode, and the first pulse voltage and the third voltage are not applied. 2
The first electrode and the third electrode so that a discharge is induced between the first electrode and the third electrode only by an address discharge between the first electrode and the second electrode due to the application of the pulse voltage. Since the wall potential difference between the third and third electrodes and the wall potential difference between the first and second electrodes are adjusted, the minimum necessary wall charges suitable for address discharge can be stably formed. ,
The applied voltage required for the address discharge can be set to the minimum required. Also, since voltages having different polarities are applied to the first and second electrodes, the absolute value of the voltage of the first pulse voltage and the second voltage are applied between the first and second electrodes. A voltage obtained by adding the absolute value of the pulse voltage to the voltage is applied, and the voltage applied to the first and second electrodes can be further reduced. Therefore, discharge can be performed with a small voltage, so that power consumption can be reduced, and the withstand voltage of a circuit that generates the first and second pulse voltages can be reduced. It becomes possible to integrate.

[0063]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an AC plasma display device will be described as an example of a display device according to the present invention. In the AC plasma display device described below, the address / sustain simultaneous driving method shown in FIG. 19 is used, but the present invention can be similarly applied to other display devices such as the ADS method.

(First Embodiment) First, a plasma display device according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the plasma display device according to the first embodiment of the present invention.

The plasma display device shown in FIG.
P (Plasma Display Panel) 1, Address Driver 2, Scan Driver 3, Sustain Driver 4, Discharge Control Circuit 5, A / D Converter (Analog / Digital Converter) 6, Scan Number Converter 7 and Subfield Converter 8 Prepare.

The video signal VD is input to the A / D converter 6. Further, a horizontal synchronization signal H and a vertical synchronization signal V are provided to the discharge control circuit 5, the A / D converter 6, the scanning number conversion unit 7, and the subfield conversion unit 8.

The A / D converter 6 converts the video signal VD into digital image data, and supplies the image data to the scan number conversion unit 7. The scanning number converter 7 converts the image data into P
The data is converted into image data of the number of lines corresponding to the number of pixels of DP1, and the image data of each line is provided to the subfield conversion unit 8. The image data for each line is composed of a plurality of pixel data respectively corresponding to a plurality of pixels of each line. The subfield conversion unit 8 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serially converts each bit of each pixel data to the address driver 2 for each subfield. Output.

The discharge control circuit 5 includes a sustain discharge generation circuit 5
1, 54, a setup circuit 52, 55 and a write / erase generation circuit 53. Sustain discharge generating circuits 51, 5
4. The horizontal synchronizing signal H and the vertical synchronizing signal V are input to the setup circuits 52 and 55 and the write / erase generating circuit 53, respectively.

Sustain discharge generating circuit 51 outputs horizontal synchronizing signal H
A sustain discharge signal necessary for sustain discharge is output to setup circuit 52 with reference to vertical synchronization signal V. The setup circuit 52 is a scan driver basic drive signal S in which a setup pulse is superimposed on the input sustain discharge signal.
C is output to the scan driver 3.

The write / erase generating circuit 53 outputs an individual write / erase signal SW for each line based on the horizontal synchronizing signal H and the vertical synchronizing signal V.
Output to

The sustain discharge generating circuit 54 outputs the horizontal synchronizing signal H
A sustain discharge signal required for sustain discharge is output to setup circuit 55 based on vertical synchronization signal V. The setup circuit 52 outputs a sustain driver basic drive signal SU in which a setup pulse is superimposed on the input sustain discharge signal to the sustain driver 4.

PDP 1 includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes (scan electrodes) 12, and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are commonly connected. A discharge cell 14 is formed at each intersection of the address electrode 11, the scan electrode 12, and the sustain electrode 13, and each discharge cell 14 forms a pixel on the screen.

The address driver 2 converts the data serially provided for each subfield from the subfield converter 8 to parallel data, outputs a write pulse Pwa based on the parallel data, and drives the plurality of address electrodes 11. Drive.

Scan driver 3 outputs scan driver basic drive signal SC output from setup circuit 52.
A setup pulse SP, a write pulse Pw, a sustain pulse Psc, and an erase pulse Pe are output at a predetermined timing for each line, that is, for each scan electrode 12, using the write / erase signal SW output from the write / erase generating circuit 53. Then, each scan electrode 12 is driven.

The sustain driver 4 outputs the setup pulse ST and the sustain pulse Psu using the sustain driver basic drive signal SU output from the setup circuit 55, and drives the plurality of sustain electrodes 13 simultaneously.

In the present embodiment, the scan electrode 12 corresponds to the first electrode, the address electrode 11 corresponds to the second electrode, the sustain electrode 13 corresponds to the third electrode, and the setup circuits 52 and 55 , Address driver 2, scan driver 3 and sustain driver 4 are adjusting means,
It corresponds to a setup adjusting unit, a wall charge storage unit, and a wall charge reduction unit. Further, the subfield conversion unit 8 corresponds to a subfield dividing unit, the write / erase generating circuit 53 and the scan driver 3 correspond to a first voltage applying unit, and the address driver 2 corresponds to a second voltage applying unit. , Sustain discharge generating circuit 54 and sustain driver 4 correspond to third voltage applying means.

FIG. 2 is a circuit diagram showing a configuration of a main part of scan driver 3 and sustain discharge generating circuit 51 shown in FIG.

The scan driver 3 shown in FIG. 2 includes a plurality of output circuits 31 and 3 provided for each scan electrode 12.
Includes 2, ... For example, when there are 480 scan electrodes 12, 480 output circuits are provided. The write / erase signal SW from the write / erase generating circuit 53
Control signals S11 to S13, S21 to S output as
Are output at a predetermined timing for each line, that is, for each scan electrode 12, and control signals S11 to S1
3 is input to the output circuit 31, the control signals S21 to S23 are input to the output circuit 32, and thereafter each control signal is input to each output circuit.

The output circuit 31 includes FETs (field-effect transistors, hereinafter referred to as transistors) Q1 to Q3 as switching elements. One end of the transistor Q1 is connected to the setup circuit 52, the other end is connected to the node N1, and the gate thereof has a write / erase generation circuit 53.
Receives the control signal S11. One end of the transistor Q2 is connected to the node N1, the other end is connected to the power supply terminal V1, and a control signal S12 from the write / erase generation circuit 53 is input to its gate. A voltage Vw for a write operation is applied to the power supply terminal V1, and in this embodiment, for example, a voltage of −90 V is applied. One end of the transistor Q3 is connected to the node N1, the other end is connected to the ground terminal, and a control signal S13 from the write / erase generating circuit 53 is input to the gate. The output signal Pc1 output from the node N1 is output to the scan electrode 12 on the first line.

The output circuits 32,... Have the same configuration as the output circuit 31. The output circuit 32 receives the control signals S21 to S23 from the write / erase generation circuit 53 and outputs an output signal Pc2 to the scan electrode 12 on the second line. Thereafter, similarly, a control signal for each line is input from the write / erase generation circuit 53 to each output circuit, and each output circuit outputs an output signal to the scan electrode 12 of the corresponding line.

The sustain discharge generating circuit 51 shown in FIG.
Includes transistors Q11 and Q12. One end of the transistor Q11 is connected to the power supply terminal V11, the other end is connected to the setup circuit 52 via the node N11, and its gate has a control signal internally generated based on the horizontal synchronization signal H and the vertical synchronization signal V. S1 is input.
The sustain voltage Vs is applied to the power supply terminal V11. In the present embodiment, for example, a voltage of 185 V is applied.
Transistor Q12 has one end connected to set-up circuit 52 via node N11, the other end connected to a ground terminal, and a control signal S2 internally generated based on horizontal synchronization signal H and vertical synchronization signal V at its gate. Is entered.

Next, the operation of the scan driver 3 configured as described above will be described. In the following description, as the operation of the scan driver 3, the operation of the output circuit 31 for driving the scan electrodes 12 of the first line will be described. However, the operation of the other output circuits is the same as that of the output circuit 31.

First, the address electrode 11 and the scan electrode 1
The setup pulse SP applied to the scan electrode 12 during the setup period for adjusting the wall potential difference caused by the wall charge formed between the scan electrode 12 and the scan electrode 12 and the sustain electrode 13 is adjusted. The case where the voltage is applied to the scan electrode 12 will be described.

In this case, the control signal S1 goes low, the transistor Q11 turns off, the control signal S2 goes high, and the transistor Q2 turns on. Therefore, a sustain discharge signal of the ground potential is output from sustain discharge generating circuit 51 to setup circuit 52, and setup circuit 52 superimposes a setup pulse SP described later on the sustain discharge signal and outputs it to scan driver 3. At this time, in the scan driver 3, the control signal S11 goes high, the transistor Q1 turns on, and the control signal S1
2, S13 goes low and the transistors Q2, Q2
3 is turned off. Therefore, the setup pulse SP output from the setup circuit 52 is the output signal Pc1
Is applied to the scan electrode 12 on the first line.

Next, a case where a write pulse Pw applied to the scan electrode 12 during the address period for selecting a discharge cell to be discharged from the plurality of discharge cells 14 and performing an address discharge is applied to the scan electrode 12 will be described. explain.

In this case, the write pulse Pw output from the address driver 2 according to the pixel data to be displayed
When a rises from 0V to 70V, the control signal S1
1 goes low, the transistor Q1 turns off, the control signal S12 goes high, and the transistor Q2 turns on. Therefore, the voltage of the node N1 falls to the voltage Vw of the power supply terminal V1, that is, -90V, and is held.

Next, when the write pulse Pwa falls from 70 V to 0 V, the control signal S11 goes high, the transistor Q1 turns on, the control signal S12 goes low, and the transistor Q2 turns off. Therefore, the voltage of the node N1 rises to 0V and is maintained. As a result, output signal P output from node N1 is output.
c1 changes from 0V to -90V and returns to 0V, and a negative pulse voltage of -90V is applied to the scan electrode 12 of the first line as the write pulse Pw.

Next, a case where the sustain pulse Psc applied to the scan electrode 12 in the sustain period for performing the sustain discharge of the discharge cell selected in the above address period is output to the scan electrode 12 will be described.

In this case, the control signal S11 goes high, the transistor Q1 turns on, and the control signals S12, S1
3 goes low, turning off the transistors Q2 and Q3. Therefore, the sustain discharge signal output from sustain discharge generating circuit 51 is used as scan driver basic drive signal SC via setup circuit 52 as scan driver 3.
And a sustain discharge signal is output as an output signal Pc1 via the transistor Q1.

At this time, in the sustain discharge generating circuit 51, first, the control signal S2 goes high, and the transistor Q1
2 turns on, the control signal S1 goes low, and the transistor Q11 turns off. Therefore, a ground potential, that is, a voltage of 0 V is output as scan driver basic drive signal SC. After a lapse of a predetermined time, the control signal S1 goes high and the transistor Q11 turns on, the control signal S2 goes low and the transistor Q12 turns off. Therefore, the sustain voltage Vs of the power supply terminal V11, that is, 185
The voltage of V is output as the scan driver basic drive signal SC.

The above operation is sequentially repeated at a predetermined timing, so that the voltage changes from 0V to 185V and becomes 0V.
The scan driver basic drive signal SC is periodically output as the output signal Pc1 via the transistor Q1. Therefore, an output signal Pc1 in which a pulse voltage that changes from 0V to 185V and returns to 0V is periodically repeated is output as sustain pulse Psc, and sustain pulse Ps
c is applied to the scan electrode 12 of the first line.

Next, a case where an erase pulse Pe for stopping the sustain discharge at the end of the sustain period is applied to the scan electrode 12 will be described.

First, at the end of the sustain period, the sustain pulse Psc rises from 0 V to 185 V in the same manner as described above.
It is kept at 5V. At this time, after a lapse of a predetermined time, the control signal S11 goes low, the transistor Q1 turns off, the control signal S13 goes high, and the transistor Q1
3 turns on. Therefore, the voltage of node N1 falls to the ground potential of 0 V, and normal sustain pulse Psc
A pulse having a smaller pulse width is output as the output signal Pc1.

At this time, as described later, the sustain pulse Psu applied to the sustain electrode 13 is maintained at 0V, and the scan electrode 12 and the sustain electrode 13
And the sustain discharge is stopped, and the narrow pulse applied to the scan electrode 12 at this time becomes the erase pulse Pe. The erase pulse Pe is applied to the scan electrode 1
When the voltage is applied to 2, the sustain discharge is stopped, the sustain period ends, and the process shifts to the idle period.

Next, the setup circuit 52 shown in FIG. 2 will be described in more detail. FIG. 3 is a circuit diagram showing a configuration of setup circuit 52 shown in FIG.

The setup circuit 52 shown in FIG. 3 includes transistors Q51 to Q60, resistors R51 to R53, capacitors C51 to C53, power supplies VF51 to VF54, and a power supply terminal V51.

One end of the transistor Q51 is connected to the power supply VF51.
, The other end is connected to one end of a resistor R51, and a control signal S51 is input to a gate of the resistor R51. The other end of resistor R51 is connected to node N52. Transistor Q52 has one end connected to node N52, the other end connected to node N51, and a control signal S51 input to its gate. Capacitor C51 is connected between power supply terminal V51 and node N52. The maximum voltage Vcp, which is a positive setup voltage, is applied to the power supply terminal V51.
A voltage of V is applied. Transistor Q53 has one end connected to power supply terminal V51, the other end connected to node N51, and the gate connected to node N52.

One end of the transistor Q54 is connected to the power supply VF52.
Is connected to a ground terminal, the other end is connected to one end of a resistor R52, and a control signal S52 is input to its gate. The other end of resistor R52 is connected to node N53. Transistor Q55 has one end connected to node N53, the other end connected to a ground terminal, and a control signal S5 connected to its gate.
2 is input. Capacitor C52 is connected between nodes N51 and N53. Transistor Q56 has one end connected to node N51, the other end connected to ground potential, and the gate connected to node N53.

One end of the transistor Q57 is connected to the power supply VF53.
, The other end is connected to one end of a resistor R53, and a control signal S53 is input to a gate of the resistor R53. The other end of resistor R53 is connected to node N54. Transistor Q58 has one end connected to node N54, the other end connected to node N51, and a control signal S53 input to its gate. Capacitor C53 is connected between nodes N54 and N55. Transistor Q59 has one end connected to node N55, the other end connected to node N51, and the gate connected to node N54.

Transistor Q60 is connected between nodes N51 and N56, and has a control signal S at its gate.
54 is input. Power supply VF54 is connected between nodes N55 and N56. The power supply VF54 outputs a minimum voltage Vcn that is a negative setup voltage. In the present embodiment, for example, the minimum voltage Vcn is −100 V
It is. The voltage of the node N56 is the setup pulse SP
Is output as

FIG. 4 shows the setup circuit 52 shown in FIG.
FIG. 5 is a timing chart showing an operation during a setup period of FIG.
FIG. 4 shows the control signals S51 to S54 and the setup pulse SP of FIG. The control signals S51 to S51
S54 is a signal generated in the setup circuit 52 based on the horizontal synchronization signal H, the vertical synchronization signal V, and the like.

First, in the period immediately before the period A, the control signal S51 is at the high level, the transistor Q51 is turned off, and the transistor Q52 is turned on. Therefore,
The potentials of the nodes N51 and N52 become equal,
Transistor Q53 is off. Also, the control signal S
52 is at low level, transistor Q54 is on, and transistor Q55 is off. Therefore,
The voltage of the node N53 becomes high level, and the transistor Q56 is turned on. Further, the control signal S53 is at the high level, the transistor Q57 is turned off, and the transistor Q58 is turned on. Therefore, the potentials of nodes N51 and N54 become equal, and transistor Q5
9 is off. Further, the control signal S54 is at the high level, and the transistor Q60 is on. Therefore, transistors Q56 and Q60 turn on, and node N5
The voltage of 6 becomes the ground potential, and the setup pulse SP is output at the ground potential (0 V).

Next, in the period A, the control signal S52 goes high, the transistor Q54 turns off, and the transistor Q55 turns on. Therefore, the node N53
Becomes the ground potential, and the transistor Q56 turns off. Also, the control signal S51 goes low, turning on the transistor Q51 and turning off the transistor Q52.

At this time, the voltage at the node N52, which is the gate voltage of the transistor Q53, depends on the resistance value of the resistor R51, the capacitance of the capacitor C51, and the parallel capacitance of the gate-drain capacitance and the gate-source capacitance of the transistor Q53. The voltage gradually increases from 0 V according to the determined time constant. When the voltage at the node N52 reaches a level at which the transistor Q53 can be turned on, the transistor Q53 is turned on.
53 turns on, and the voltage Vcp of the power supply terminal V51 tries to appear on the source side of the transistor Q53 via the transistor Q53.

However, when the source voltage of transistor Q53 rises, the voltage of power supply VF51 also rises with the rise, so that the gate voltage of transistor Q53 also rises via transistor Q51,
The potential difference between the gate and the source of 53 is kept constant. Therefore, transistor Q53 does not attain a complete ON state at once, but has a ramp waveform in which the source voltage gradually increases in accordance with the above time constant, and this ramp waveform is output to node N56 via transistor Q60. As a result, the setup pulse SP is output as a ramp waveform that gradually rises, rises until its voltage reaches the maximum voltage Vcp, and is maintained at the maximum voltage Vcp in the period B.

Next, in a period C, the control signal S51 goes high, the transistor Q51 turns off, and the transistor Q52 turns on. Therefore, the node N51
And the voltage of the node N52 becomes equal, and the transistor Q53 is turned off. Further, the control signal S52 becomes low level, the transistor Q54 turns on, and the transistor Q54
55 turns off.

At this time, the voltage at the node N53, which is the gate voltage of the transistor Q56, depends on the resistance of the resistor R52, the capacitance of the capacitor C52, and the parallel capacitance of the gate-drain capacitance and the gate-source capacitance of the transistor Q56. It gradually increases according to the determined time constant. Then, the voltage of the node N53 becomes the transistor Q56
Is turned on, the transistor Q56 is turned on, and charges are discharged to the ground terminal via the turned-on transistor Q56. Therefore, the drain voltage of transistor Q56, that is, the voltage of node N51 has a gradually falling ramp waveform, and this ramp waveform is output to node N56 via transistor Q60. As a result, the setup pulse SP is output as a ramp waveform that gradually decreases, falls until the voltage reaches the ground potential, and is maintained at the ground potential during the period D.

Next, in the period E, the control signal S54 goes low, the transistor Q60 turns off, and the voltage of the node N51 is not output to the node N56. on the other hand,
When the control signal S53 goes low, the transistor Q5
7 turns on, and the transistor Q58 turns off. At this time, the node N5 which is the gate voltage of the transistor Q59
4 is the resistance value of the resistor R57 and the resistance of the capacitor C53.
, And the parallel capacitance of the gate-drain capacitance and the gate-source capacitance of the transistor Q59. Here, the drain voltage of the transistor Q59, that is, the voltage of the node N55 is the output voltage of the power supply VF54 when the voltage of the node N56 is 0 V, but the voltage of the node N54 reaches a level at which the transistor Q59 can be turned on. When the transistor Q59 is turned on, the drain voltage of the transistor Q59 tends to drop to the ground potential because the node N51 is connected to the ground terminal via the transistor Q56.

However, when the drain voltage of the transistor Q59 drops, the gate voltage of the transistor Q59 also drops via the capacitor C53, so that the transistor Q59 does not turn on completely at once, and the charge at the drain of the transistor Q59 is reduced. It is gradually discharged to the ground terminal via Q56, and the transistor Q59
Drain voltage gradually approaches 0V. here,
Since the voltage of the node N56 is lower than the potential of the drain of the transistor Q59 by the output voltage of the power supply VF54, the voltage gradually approaches the minimum voltage Vcn and a ramp waveform that gradually decreases is output from the node N56. As a result, the setup pulse SP is output as a gradually falling ramp waveform, and falls until its voltage reaches the minimum voltage Vcn.
In the period F, the voltage is kept at the minimum voltage Vcn.

Finally, in the period G, the control signal S53
Goes high, the transistor Q57 turns off, and the transistor Q58 turns on. Therefore, node N5
1 and the potential of the node N54 become equal, and the transistor Q59 is turned off. Also, the control signal S54 goes high, turning on the transistor Q60. At this time, since the transistor Q56 is on, the node N
The voltage of 56 is immediately returned to the ground potential via the transistor Q56, and is maintained at 0V.

Note that sustain discharge generating circuit 54 shown in FIG. 1 is configured similarly to sustain discharge generating circuit 51 shown in FIG. 2, and in the sustain period, scan driver basic drive signal SC is inverted to change from 185V to 0V. The basic driver drive signal SU that returns to 185 V is output to the sustain driver 4.

The setup circuit 55 shown in FIG. 1 is configured similarly to the sustain discharge generation circuit 51 shown in FIG. 2 by changing the sustain voltage Vs of the power supply terminal V11 to the setup voltage Vup for the sustain electrode 13. In the period, the sustain driver basic drive signal SU that changes from 0 V to 280 V and returns to 0 V is output to the sustain driver 4.

As described above, the sustain driver 4 outputs a setup pulse ST and a sustain pulse Psu, which will be described later, to all the sustain electrodes 13 in accordance with the sustain driver basic drive signal SU.

FIG. 5 is a timing chart showing driving voltages applied to the respective electrodes of PDP 1 of FIG. FIG. 5 shows the drive voltages of the address electrode 11, the sustain electrode 13, the scan electrode 12 (n) of the n-th line, and the scan electrode 12 (n + 1) of the (n + 1) -th line. Here, n is an arbitrary integer. Note that the discharge start voltages Vsp, Vdp, Vsn, and Vdn in FIG. 5 are shown when the effective potential difference between the electrodes reaches the discharge start voltages Vsp, Vdp, Vsn, and Vdn in the scan pulse SP. The same applies to other embodiments.

In the present embodiment, for example, one field is divided into eight subfields, and a setup period is set only before the first subfield, that is, every vertical scanning period. An address period, a sustain period, and a pause period are set for each line. Note that the number of subfield divisions is not particularly limited to the above example, may be another number, and the setup period is not particularly limited to the above example, either before the first subfield of each subfield or After the last subfield, it may be set at a time interval that is an integral multiple of the vertical scanning period. The above points are the same in the following embodiments.

First, the setup operation between scan electrode 12 and sustain electrode 13 will be described. FIG.
As shown in (1), the setup pulse SP is simultaneously applied to all the scan electrodes 12 during the setup period. The setup pulse SP sequentially increases from 0 V by a ramp waveform and rises to the maximum voltage Vcp. on the other hand,
Address electrode 11 and sustain electrode 13 are both 0
Held at V.

At this time, the above setup pulse SP
The voltage obtained by summing the potential difference due to the gently increasing voltage applied from the outside and the wall potential difference between the scan electrode 12 and the sustain electrode 13 already stored at the time of entering the setup period becomes the scan electrode 12 From the point in time when the discharge start voltage Vsp in the positive direction between the scan electrode 12 and the sustain electrode 1 has been exceeded.
3, the weak discharge in the positive direction starts and continues until the voltage of the setup pulse SP reaches the maximum voltage Vcp.

As described above, in the wall charge accumulation period CS1 between the scan electrode 12 and the sustain electrode 13, the scan electrode 12 and the sustain electrode 1
3, wall charges are gradually accumulated, and a large negative wall potential difference is formed.

Next, while the voltage of the setup pulse SP applied to the scan electrode 12 is maintained at the maximum voltage Vcp, the voltage of the setup pulse ST applied to the sustain electrode 13 is raised to the setup voltage Vup. Thereafter, the voltage of the setup pulse SP is gradually reduced by a ramp waveform.

At this time, the sum of the wall potential difference between the scan electrode 12 and the sustain electrode 13 and the potential difference due to the voltage applied to the scan electrode 12 and the sustain electrode 13 becomes the scan electrode 12 and the sustain electrode 13.
From the point at which the discharge start voltage Vsn in the negative direction is exceeded, a weak discharge in the negative direction starts between the scan electrode 12 and the sustain electrode 13 and continues until the voltage of the setup pulse SP reaches 0V.

As described above, in the wall charge reduction period CS2 between the scan electrode 12 and the sustain electrode 13, the weak discharge causes the scan electrode 12 and the sustain electrode 1 to fall.
3 gradually decreases and remains as a negative wall potential difference, the wall potential difference becomes 0 V, or changes to a positive wall potential difference and remains. That is the state.

The above state depends on whether the setup voltage Vup applied to the sustain electrode 13 and the wall potential difference between the scan electrode 12 and the sustain electrode 13 are 0V.
And the discharge starting voltage Vsn0 in the negative direction at the time of For example, when | Vup | <| Vsn0 |, a negative wall potential difference remains, and when | Vup | = | Vsn0 |, the wall potential difference becomes 0 V, and | Vup |> | Vsn0 |
In this case, a positive wall potential difference remains. The above-mentioned negative firing voltage Vsn0 is a value unique to each scan electrode 12, and by adjusting the setup voltage Vup applied to the sustain electrode 13, the wall potential difference between the scan electrode 12 and the sustain electrode 13 is adjusted. Can be adjusted to various states as described above.

Next, the scan electrode 12 and the address electrode 1
1 will be described. The voltage obtained by adding the wall potential difference between the scan electrode 12 and the address electrode 11 already stored at the time of entering the setup period and the potential difference due to the voltage gradually increased by the setup pulse SP is the scan electrode 12 and the address. From the point in time when the voltage exceeds the discharge start voltage Vdp in the positive direction between the scan electrode 12 and the address electrode 11, weak discharge in the positive direction starts between the scan electrode 12 and the address electrode 11, and the setup pulse S
It continues until the voltage of P reaches the maximum voltage Vcp.

As described above, during the wall charge accumulation period CD1 between the scan electrode 12 and the address electrode 11, the weak discharge gradually accumulates the wall charge between the scan electrode 12 and the address electrode 11, and the large negative electrode A wall potential difference is formed.

Next, even if the voltage of the setup pulse SP is gradually reduced to 0 V, the voltage applied to the address electrode 11 remains at 0 V. Is the sum of the wall potential difference and the potential difference due to the setup pulse SP,
The voltage does not exceed the discharge start voltage Vdn in the negative direction between the scan electrode 12 and the address electrode 11, and no discharge occurs during this period.

Thereafter, the voltage of the setup pulse SP is maintained at 0 V for a predetermined time and then gradually decreased in the negative direction. When the voltage exceeds the discharge start voltage Vdn in the negative direction, a weak discharge is started. , Setup pulse S
It continues until the voltage of P reaches the minimum voltage Vcn. Therefore, in the wall charge reduction period CD2 between the scan electrode 12 and the address electrode 11, the wall charge stored between the scan electrode 12 and the address electrode 11 gradually decreases due to the weak discharge, and the negative polarity wall Either the potential remains as it is, the wall potential difference becomes 0 V, or the state changes to a positive wall potential difference and remains.

The above state is determined by the minimum voltage Vcn of the setup pulse SP and the discharge start voltage Vdn0 in the negative direction when the wall potential difference between the scan electrode 12 and the address electrode 11 is 0V. You. For example, a negative wall potential difference remains when | Vcn | <| Vdn0 |, a wall potential difference becomes 0 when | Vcn | = | Vdn0 |, and a positive wall when | Vcn |> | Vdn0 | A potential difference remains. The above-mentioned discharge starting voltage Vdn in the negative direction
0 is a value unique to each scan electrode 12, and the wall potential difference between the scan electrode 12 and the address electrode 11 can be adjusted by adjusting the minimum voltage Vcn of the setup pulse SP.

As described above, by adjusting the sustain voltage Vup applied to the sustain electrode 13 during the setup period, the wall potential difference between the scan electrode 12 and the sustain electrode 13 can be adjusted, and the voltage applied to the scan electrode can be adjusted. Setup pulse SP
Of the scan electrode 1 by adjusting the minimum voltage Vcn of
It is possible to adjust the wall potential difference between the address electrodes 2 and the address electrodes 11.

In the above adjustment, since the wall potential difference between the electrodes is adjusted by a weak discharge which does not affect the other wall charge, the adjustments can be performed independently without interfering with each other. Therefore, during the setup period before the address discharge, the scan electrode 12 and the sustain electrode 13
Between the scan electrode 12 and the address electrode 1
1 can be independently and precisely adjusted with high accuracy, and can be in an optimal state for address discharge.

The ramp waveform of the setup pulse SP for stably performing the weak discharge is about 1-3 V / μs when the rising period A of the setup pulse SP shown in FIG. 4 is about 150-450 μs. And the first falling period C is about 150 to 45
It is preferable to decrease at a rate of about 1 to 3 V / μs at 0 μs, and to decrease at a rate of about 1 to 3 V / μs when the second fall period E is about 30 to 100 μs.

Next, the address electrode 11 and the scan electrode 1
2 will be described. During the address period, a negative write pulse Pw is applied to the scan electrode 12. The write pulse Pw is located at the beginning of each subfield. This write pulse P
A write pulse Pwa of a positive polarity is applied to the address electrode 11 in synchronization with w. ON / OFF of the write pulse Pwa applied to the address electrode 11 is controlled according to each pixel to be displayed. When the write pulse Pw and the write pulse Pwa are applied simultaneously, the scan electrode 12
An address discharge is generated in the discharge cell 14 at the intersection of the address and the address electrode 11, and the discharge cell 14 is turned on.

More specifically, the write pulse Pwa applied to the address electrode 11 rises from 0V to 70V, and falls from 70V to 0V after a predetermined time has elapsed. The write pulse Pw falls from 0V to -90V in synchronization with the write pulse Pwa of the address electrode 11,
After a lapse of a predetermined time, the voltage rises from -90V to 0V. Therefore, a voltage of 160 V is applied between the address electrode 11 and the scan electrode 12, and an address discharge occurs between the address electrode 11 and the scan electrode 12. The voltage applied to the sustain electrode 13 rises from 0 V to 185 V at the beginning of the address period, and
It is kept at 85V.

Next, conditions of the wall potential difference suitable for the address discharge will be described. In the first address discharge after the setup period, the presence / absence of discharge is determined by the sum of the wall potential difference between the electrodes adjusted by the setup operation and the potential difference due to the voltage of the driving pulse applied from the outside.

The voltage applied to the sustain electrode 13 during the address period is set to the sustain voltage Vs required for sustain discharge, and scans the voltage Vw of the negative write pulse Pw and the voltage Vd of the positive write pulse Pwa. Electrode 12
Address discharge is started by applying the voltage to the address electrodes 11 simultaneously.

At this time, voltage Vw applied to scan electrode 12 and sustain voltage V applied to sustain electrode 13
s and the wall potential difference accumulated during the setup period are set so that the total voltage does not exceed the discharge start voltage between the sustain electrode 13 and the scan electrode 12 during the address period. On the other hand, the sum of the potential difference between the voltage Vw applied to the scan electrode 12 and the voltage Vd applied to the address electrode 11 and the wall potential difference accumulated during the setup period is a voltage between the scan electrode 12 and the address electrode 11. Is set so as to exceed the discharge starting voltage.

As described above, when the address discharge is started between the scan electrode 12 and the address electrode 11, a discharge between the scan electrode 12 and the sustain electrode 13 is induced by the priming effect to complete the address discharge. Is performed, and a wall charge is formed between the scan electrode 12 and the sustain electrode 13 so as to be a wall potential difference required for the sustain discharge.

On the other hand, in the present embodiment, since the setup period is set only before the first subfield,
Other than during the address discharge of the first subfield, that is, the second
At each address discharge after the subfield, the wall potential difference adjusted by the setup period cannot be directly used. Therefore, after the second subfield, in the sustain period of the immediately preceding subfield, the wall potential difference formed by the sustain pulse Psc and the sustain pulse Psu is changed to the wall potential difference required for the next address discharge by the erase discharge as described later. I have to adjust.

In the present embodiment, the erasing discharge is performed by applying a pulse having a narrower pulse width than the sustain pulse Psc as the erasing pulse Pe in synchronization with the sustain pulse Psu. As described above, the pulse width of the erase pulse Pe can be controlled by changing the timing at which the control signal S11 goes low and the control signal S13 goes high. Therefore, write /
By adjusting the pulse width of the erase pulse Pe by the erase generation circuit 53, the scan electrode 12 and the sustain electrode 1 are adjusted.
3 can be adjusted. Further, it has been experimentally found that the wall potential difference between the scan electrode 12 and the address electrode 11 at the time of the erasing discharge is almost half of the sustain voltage Vs of the sustain pulse Psc at the time of the sustain discharge.

In this manner, the wall potential difference between the electrodes after the erasing discharge, that is, at the time of the next address discharge, is determined. In the present embodiment, the wall potential difference after the setup period is set to match the wall potential difference at this time. Is adjusted. Therefore, the wall potential difference of the first subfield immediately after the setup period matches the wall potential difference of the other subfields, and address discharge can be stably performed in all subfields.

It is not necessary that the wall potential difference of the first subfield immediately after the setup period completely coincides with the wall potential differences of the other subfields. Even if the voltage conditions applied between the electrodes during the address discharge are the same. In any of the wall potential difference states, a slight deviation of the wall potential difference is acceptable as long as it is within a range that satisfies the condition that the address discharge occurs stably.
This case is also within the scope of the present invention.

Next, the operation of the sustain discharge between scan electrode 12 and sustain electrode 13 will be described. In the sustain period, the sustain pulse Psu applied to the sustain electrode 13 changes from the sustain voltage Vs of 185 V to 0.
It rises to V and falls from 0 V to 185 V after a lapse of a predetermined time. The sustain pulse Psc is applied to the scan electrode 12 in synchronization with the sustain pulse Psu. The sustain pulse Psc changes from 0 V to the sustain voltage Vs of 185 V
And falls from 185V to 0V after a predetermined time has elapsed. Therefore, a voltage of 185 V is applied between the scan electrode 12 and the sustain electrode 13, and a sustain discharge is generated only in the discharge cells lit by the address discharge. Thereafter, the sustain pulse Psc and the sustain pulse Psu are similarly applied to the scan electrode 12 and the sustain electrode 13.
At the same time, a sustain discharge is performed at both edges of each pulse, and the sustain discharge is continued.

The sustain pulse Psc and the sustain pulse Psu are inserted by a number corresponding to the weight of each subfield during the period from the write pulse Pw to the erase pulse Pe. For example, in the scan electrode 12 (n), first, in the first subfield, the sustain pulse Psc and the sustain pulse Psu are respectively inserted twice, and the sustain discharge is performed four times. Next, in the second subfield, the sustain pulse Psc and the sustain pulse Psu are inserted four times each, and eight sustain discharges are performed.

At the end of the sustain period, scan electrode 12
Is applied with the erase pulse Pe. Thereby, each charge of each discharge cell is reduced to such an extent that disappearance or sustain discharge does not occur, and the sustain discharge ends. Here, the pulse width of the erasing pulse Pe is set so that the wall potential difference between the scan electrode 12 and the sustain electrode 13 becomes a wall potential difference suitable for address discharge in the next subfield.

Finally, during the pause period after the application of the erase pulse Pe, the sustain pulse Psu is applied to the sustain electrode 13.
Even if the same pulse is applied once, no pulse is applied to the scan electrode 12 and no discharge occurs. After the end of the sleep period, the next subfield starts.

In the scan electrode 12 (n + 1),
A setup operation is performed simultaneously with the scan electrode 12 (n), and the same operation as described above is performed in each subfield with a delay of one cycle of the sustain pulse Psu.
Similarly, the other scan electrodes 12 are also set up at the same time, and then, after a predetermined period of time, are sequentially operated for each subfield, and are driven line by line.

Next, the process of adjusting the wall potential difference between the scan electrode 12 and the sustain electrode 13 during the setup period will be described in more detail. FIG.
FIG. 6 is a diagram for explaining an example of a process of adjusting a wall potential difference between the scan electrode 12 and the sustain electrode 13 during the setup period shown in FIG. 5. In FIG. 6,
The potential difference L1 due to the setup pulse SP applied to the scan electrode 12 and the setup pulse ST applied to the sustain electrode 13, which is an externally applied voltage, is shown by a solid line, and is caused by the formation of wall charges between the scan electrode 12 and the sustain electrode 13. The wall potential difference L2 is indicated by a dashed line, and the effective potential difference L3 obtained by adding the potential difference L1 and the wall potential difference L2 due to the externally applied voltage is indicated by a dashed line.

When the voltage of the scan electrode 12 and the sustain electrode 13 during the setup period is set to 0 V as a reference, the maximum voltage Vcp of the setup pulse SP is 450 V, the minimum voltage Vcn is -100 V, and the setup voltage Vup of the sustain electrode 13 is 280 V. The wall potential difference between the scan electrode 12 and the sustain electrode 13 immediately before the period is -30 V, and the positive firing voltage Vsp between the scan electrode 12 and the sustain electrode 13 is 250.
V, the case where the discharge start voltage Vsn in the negative direction is -250V will be described.

First, the positive discharge start voltage Vsp is 25
Since the voltage is 0 V, the scan electrode 12 and the sustain electrode 1
3 has a potential difference of 280 V obtained by adding a wall potential difference of −30 V formed before the setup period.
(= 250 + 30). Therefore, as shown in FIG. 6, the potential difference L1 due to the externally applied voltage
Exceeds 280 V, a weak discharge starts. afterwards,
The potential difference L1 due to the externally applied voltage increases to 450V,
The wall potential difference L2 is obtained by increasing the potential difference by -170 V (= 28
0-450) and a total of -200V (=
−30-170) is formed. At this time, the effective potential difference L3 is maintained at 250 V because the wall potential difference L2 increases with a negative polarity.

Next, when the setup pulse SP reaches the maximum voltage Vcp of 450 V, the sustain electrode 1
3, a voltage of 280 V is applied as the setup voltage Vup, so that the potential difference L1 due to the externally applied voltage is 170
V (= 450-280). Therefore, the effective potential difference L3 at this time is −30 V (= 170−200).

Thereafter, as the voltage of the setup pulse SP decreases, the potential difference L1 due to the externally applied voltage becomes -280.
It descends slowly to V. At this time, the effective potential difference L3 also decreases at the same gradient as the potential difference L1 due to the externally applied voltage, and the effective potential difference L3 is the negative-direction discharge start voltage Vsn-2.
When the voltage reaches 50 V, a weak discharge occurs between the scan electrode 12 and the sustain electrode 13. Therefore, wall charges are formed from this point, the wall potential difference L2 gradually rises, and the effective potential difference L3 is maintained at -250V.

At this time, the wall potential difference caused by the accumulated wall charges is the maximum attained voltage -480 V (= -30-45) when the effective potential difference continues to decrease.
0) and an effective potential difference of -25, which is actually fixed and unchanged.
230V (= −250 − (− 48) which is a difference from 0V
0)). Therefore, when the potential difference L1 due to the externally applied voltage returns to 0 V at the end of the setup period, the difference between the stored wall potential difference of 230 V and the immediately preceding wall potential difference of -200 V is 30 V (= 230 V).
−200) will remain as the final wall potential difference.

Next, even if a voltage of about -100 to -150 V as the minimum voltage Vcn of the setup pulse SP is subsequently applied to the scan electrode 12 from the outside, the discharge start voltage Vsn in the negative direction reaches -250 V. Therefore, a weak discharge does not occur between the scan electrode 12 and the sustain electrode 13, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 is determined at a previous stage.

As described above, when the above-described wall potential difference adjusting process is used, the last value of the wall potential difference to be left is determined by the negative-going discharge start voltage Vsn and the set-up voltage Vup applied to the sustain electrode 13. Other voltages have no effect. Therefore, by changing the setup voltage Vup applied to the sustain electrode 13,
It is possible to arbitrarily adjust the wall potential difference between the scan electrode 12 and the sustain electrode 13.

Next, the process of adjusting the wall potential difference between the scan electrode 12 and the address electrode 11 during the setup period will be described. FIG. 7 is a diagram for explaining an example of a process of adjusting a wall potential difference between the scan electrode 12 and the address electrode 11 during the setup period shown in FIG. In FIG. 7, the setup pulse SP applied to the scan electrode 12 which is an externally applied voltage is shown.
Is shown by a solid line, and the wall potential difference L4 caused by the formation of wall charges between the scan electrode 12 and the address electrode 11 is shown in FIG.
5 is indicated by a broken line, and the effective potential difference L6 obtained by adding the potential difference L4 and the wall potential difference L5 due to the externally applied voltage is indicated by a dashed line.

The maximum voltage Vcp of the setup pulse SP is set to 450 V and the minimum voltage Vcn is set to -120 V with reference to the voltage of the scan electrode 12 and the address electrode 11 during the setup period. The case where the wall potential difference between the scan electrode 12 and the scan electrode 12 is −50 V, the positive discharge start voltage Vdp between the scan electrode 12 and the address electrode 11 is 300 V, and the negative discharge start voltage Vdn is −210 V will be described.

First, the positive firing voltage Vdp is 30
Since the voltage is 0 V, the scan electrode 12 and the address electrode 11
And the potential difference obtained by adding the wall potential difference −50 V formed before the setup period is 350 V (=
It occurs when it exceeds 300 + 50). Therefore, as shown in FIG. 7, the potential difference L4 due to the externally applied voltage is 35
When the voltage exceeds 0 V, a weak discharge starts. Thereafter, the potential difference L4 due to the externally applied voltage increases to 450 V, and the wall potential difference L5 increases by the potential difference of −100 V (= 350−4).
50), and a total of -150 V (= -50
-100) is formed. At this time, the effective potential difference L6 is maintained at 300 V because the wall potential difference L5 increases with a negative polarity.

Next, the setup pulse SP reaches 450 V, which is the maximum voltage Vcp, is kept at that value for a predetermined period, and then gradually decreases to 0 V. At this point, no weak discharge occurs. Furthermore, the setup pulse SP
When the effective potential difference 6 reaches −210 V, which is the discharge start voltage Vdn in the negative direction, the scan electrode 1
A weak discharge occurs between the address electrode 2 and the address electrode 11. Therefore, wall charges are formed from this point, and the wall potential difference L
5 gradually rises, and the effective potential difference L6 is maintained at -210V.

At this time, the wall potential difference caused by the accumulated wall charges is the maximum attained voltage -270 V (= -150-12
0) and an effective potential difference -21 which is fixed and does not change in practice.
60V which is a difference from 0V (= −210 − (− 270))
Becomes Therefore, when the potential difference L4 due to the externally applied voltage returns to 0 V at the end of the setup period, -90 V (= 60 V) is a difference between the stored wall potential difference of 60 V and the immediately preceding wall potential difference of -150 V. -15
0) will remain as the final wall potential difference.

As described above, if the above-described wall potential difference adjusting process is used, the last value of the wall potential difference to be left is determined by the negative discharge start voltage Vdn and the minimum voltage Vcn applied to the scan electrode 12. Other voltages have no effect. Therefore, by changing the minimum voltage Vcn applied to the scan electrode 12, the wall potential difference between the scan electrode 12 and the address electrode 11 can be arbitrarily adjusted.

As described above, in the present embodiment, during the setup period before the first subfield, the wall potential difference between scan electrode 12 and sustain electrode 13 is adjusted, and the scan is performed independently of this adjustment. Electrode 12
Since the wall potential difference between the gate electrode and the address electrode 11 is adjusted, the wall charge formed between the electrodes can be adjusted to an optimal state for the address discharge, and the address discharge can be stably performed at a low voltage. Can be. Further, in the weak discharge used for the above adjustment, only very weak light emission is generated, so that the brightness level of black display does not increase and the contrast of the display screen does not deteriorate.

In the present embodiment, in a state where the wall charges are adjusted to be optimal for the address discharge by the set-up operation, a positive write pulse Pw of 70 V is applied to the address electrode 11 during the address period. By applying a 90V negative polarity write pulse Pw to the scan electrode 12, a 160V voltage can be applied between the address electrode 11 and the scan electrode 12, and the address discharge can be stably performed at a low voltage. it can.

The voltage of the address electrode 11 output from the address driver 2 is 70 V, which is a very small value as compared with 310 V which is the voltage of the write pulse output from the conventional address driver. The withstand voltage can be made very small. As a result, power consumption can be reduced, and the address driver 2 can be easily integrated.

Further, in the above driving waveform, after the voltage applied to the scan electrode 12 is once returned to the ground potential from 185 V, it falls in two steps from the ground potential to -90 V.
Since the write pulse Pw is generated by returning the voltage from −90 V to the ground potential, it is not necessary to rapidly lower and raise the voltage of the write pulse Pw at a time. Therefore, the configuration of the scan driver 3 can be simplified, and the power consumption can be further reduced.

(Second Embodiment) Next, a description will be given of a plasma display device according to a second embodiment of the present invention. The difference between the plasma display device of the second embodiment and the plasma display device of the first embodiment is that the setup circuit 52 shown in FIG. 3 is changed to a setup circuit described below. Is similar to that of the first embodiment, and only different points will be described in detail below.

FIG. 8 is a circuit diagram showing a configuration of a setup circuit used in the plasma display device according to the second embodiment.

The setup circuit 52a shown in FIG. 8 includes transistors Q61 to Q72, resistors R61 to R63, capacitors C61 to C63, power supplies VF61 to VF65, and a power supply terminal V61.

One end of the transistor Q61 is connected to a power supply VF61.
, The other end is connected to one end of a resistor R61, and a control signal S61 is input to a gate of the resistor R61. The other end of resistor R61 is connected to node N62. Transistor Q62 has one end connected to node N62, the other end connected to node N61, and a control signal S61 input to its gate. The capacitor C61 is connected to the power supply V
Connected between one end of F65 and node N62. The other end of power supply VF65 is connected to node N67. Power supply VF
65 is the maximum voltage Vc which is the setup voltage of the positive polarity
intermediate voltage V which is lower than the discharge start voltage Vsp in the positive direction from p
A voltage obtained by subtracting b is output. In the present embodiment, for example, the discharge start voltage Vsp in the positive direction is 250 V, the intermediate voltage Vb is 200 V, and the output voltage is 50 V. Transistor Q63 has one end connected to one end of power supply VF65, the other end connected to node N61, and the gate connected to node N62.

One end of the transistor Q64 is connected to the power supply VF62.
, And the other end is connected to one end of a resistor R62, and a control signal S62 is input to the gate of the resistor R62. The other end of resistor R62 is connected to node N63. Transistor Q65 has one end connected to node N63, the other end connected to node N67, and a control signal S62 input to its gate. Capacitor C62 is connected between nodes N61 and N63. Transistor Q66 has one end connected to node N61, the other end connected to node N67, and the gate connected to node N63.

One end of the transistor Q71 is connected to the power terminal V6.
1 and the other end is connected to the node N67, and the control signal S62 is input to its gate. Power supply terminal V61
, An intermediate voltage Vb is applied. Transistor Q72
Is connected to a node N67, the other end is connected to a ground terminal, and a control signal S61 is input to its gate.

One end of the transistor Q67 is connected to the power supply VF63.
, The other end is connected to one end of the resistor R63, and the control signal S63 is input to the gate. The other end of resistor R63 is connected to node N64. Transistor Q68 has one end connected to node N64, the other end connected to node N61, and a control signal S63 input to its gate. Capacitor C63 is connected between nodes N64 and N65. Transistor Q69 has one end connected to node N65, the other end connected to node N61, and the gate connected to node N64.

Transistor Q70 is connected between nodes N61 and N66, and has a control signal S at its gate.
64 is input. Power supply VF64 is connected between nodes N65 and N66. The power supply VF64 outputs a minimum voltage Vcn that is a negative setup voltage. In the present embodiment, for example, the minimum voltage Vcn is −100 V
It is. The voltage of the node N66 is the setup pulse SP
Is output as

In this embodiment, the setup circuit 52
a, 55, an address driver 2, a scan driver 3, and a sustain driver 4 correspond to an adjusting unit, a setup adjusting unit, a wall charge accumulating unit, and a wall charge reducing unit, and the other components are the same as those in the first embodiment.

FIG. 9 shows the setup circuit 52 shown in FIG.
5A is a timing chart showing the operation during the setup period of FIG. FIG. 9 shows the control signals S61 to S64 and the setup pulse SP of FIG. The control signal S6
1 to S64 are signals generated in the setup circuit 52a based on the horizontal synchronization signal H, the vertical synchronization signal V, and the like.

First, in a period immediately before the period A, the control signal S61 is at a high level, the transistor Q61 is turned off, and the transistor Q62 is turned on. Therefore,
The potentials of the nodes N61 and N62 become equal,
Transistor Q63 is off. Also, the control signal S
62 is at the low level, the transistor Q64 is on, and the transistor Q65 is off. Therefore,
The voltage of the node N63 becomes high level, and the transistor Q66 is turned on. Further, since the control signal S61 is at a high level and the control signal S62 is at a low level,
The transistor Q71 turns off, the transistor Q72 turns on, and the node N, which is the source voltage of the transistor Q66,
The voltage at 67 is the ground potential. Also, the control signal S
63 is at a high level, transistor Q67 turns off,
Transistor Q68 is on. Therefore, the potentials of the node N61 and the node N64 become equal, and the transistor Q69 is off. Also, the control signal S64
Is at a high level, and the transistor Q70 is on. Therefore, transistors Q66, Q70, Q72
Is turned on, the voltage of the node N66 becomes the ground potential, and the setup pulse SP is output at the ground potential (0 V).

Next, in the period A, the control signal S61 goes low, the control signal S62 goes high, the transistor Q72 is turned off, and the transistor Q71 is turned off.
Is turned on, and the voltage at the node N67, which is the source voltage of the transistor Q66, becomes the intermediate voltage Vb. Therefore, the intermediate voltage Vb is added to the output voltage Vcp-Vb of the power supply VF65, and the drain voltage of the transistor Q63 immediately increases by the intermediate voltage Vb to reach the maximum voltage Vcp. Further, the voltage of the node N66 rises to the intermediate voltage Vb at a stretch, and the setup pulse SP rises to the intermediate voltage Vb at a stretch.

When the control signal S62 goes high, the transistor Q64 turns off and the transistor Q65 turns off.
Turns on. Therefore, the nodes N63 and N
The potential of 67 becomes equal, and transistor Q66 turns off. On the other hand, when the control signal S61 becomes low level, the transistor Q61 turns on and the transistor Q62 turns off.

At this time, the gate of transistor Q63
The voltage between the sources gradually increases from 0 V by a time constant determined by the resistance value of the resistor R61, the capacitance of the capacitor C61, the parallel capacitance of the gate-drain capacitance and the gate-source capacitance of the transistor Q63. When the voltage at the node N62 reaches a level at which the transistor Q63 can be turned on, the transistor Q63 turns on,
Maximum voltage Vc which is the drain voltage of transistor Q63
p tries to appear on the source side of transistor Q63 via transistor Q63.

However, when the source voltage of transistor Q63 rises, the voltage of power supply VF51 also rises with the rise, so that the gate voltage of transistor Q63 also rises via transistor Q61,
63, the potential difference between the gate and the source is kept constant. Therefore, transistor Q63 does not attain a complete ON state at once, but has a ramp waveform in which the source voltage gradually increases in accordance with the above time constant, and this ramp waveform is output to node N66 via transistor Q70.

As described above, the setup pulse SP is
The voltage rises at a stretch to the intermediate voltage Vb, and then is output as a ramp waveform that gradually rises, and the voltage is changed to the maximum voltage Vcp
, And is maintained at the maximum voltage Vcp during the period B.

Next, in a period C, the control signal S61 goes high, the control signal S62 goes low, the transistor Q71 is turned off, and the transistor Q72 is turned off.
Is turned on, and the voltage of the node N67, which is the source voltage of the transistor Q66, becomes the ground potential. Therefore, the drain voltage of the transistor Q63 immediately drops by the intermediate voltage Vb to become the output voltage Vcp-Vb of the power supply VF65. Further, the voltage of the node N66 drops at once by the intermediate voltage Vb, and the setup pulse SP falls at a stretch.

When the control signal S61 goes high, the transistor Q61 turns off and the transistor Q62 turns off.
Turns on. Therefore, the nodes N62 and N61
Become equal, and the transistor Q63 is turned off.
On the other hand, when the control signal S62 becomes low level, the transistor Q64 turns on and the transistor Q65 turns off.

At this time, the voltage at the node N63, which is the gate voltage of the transistor Q66, depends on the resistance value of the resistor R62, the capacitance of the capacitor C62, and the parallel capacitance of the gate-drain capacitance and the gate-source capacitance of the transistor Q66. It gradually increases according to the determined time constant. Then, the voltage of the node N63 changes to the transistor Q66.
Is turned on, the transistor Q66 is turned on, and the drain voltage of the transistor Q66, that is, the voltage of the node N61 is changed to the turned on transistors Q66 and Q66.
The charge is released to the ground terminal via the gate 72, and a ramp waveform that gradually decreases is formed.
0 to the node N66.

As described above, the setup pulse SP is
The voltage drops at a stretch by the intermediate voltage Vb, and is then output as a ramp waveform that gradually decreases, then drops until the voltage reaches the ground potential, and is maintained at the ground potential during the period D.

Thereafter, during the periods E to G, the operation is the same as that of the setup circuit 52 shown in FIG. 3, and the same waveform is output.

FIG. 10 shows the setup circuit 5 shown in FIG.
FIG. 4 is a timing chart showing a driving voltage applied to each electrode of the PDP 1 of the present embodiment using 2a. Note that FIG.
Since the drive voltages other than the setup period shown in FIG. 5 are the same as the drive voltages shown in FIG. 5, the description thereof will be omitted, and only the setup period will be described in detail below.

First, the setup operation between scan electrode 12 and sustain electrode 13 will be described. FIG.
As shown by 0, a setup pulse SP is simultaneously applied to all the scan electrodes 12 during the setup period. The setup pulse SP changes from 0V to the intermediate voltage V
After being started at a stretch at b, the voltage gradually increases according to the ramp waveform and rises to the maximum voltage Vcp. On the other hand, both the address electrode 11 and the sustain electrode 13 are maintained at 0V.

At this time, when the voltage of the setup pulse SP is between 0 V and the intermediate voltage Vb, the intermediate voltage Vb
Is the sum of the potential difference caused by the scan electrode 12 and the wall potential difference between the scan electrode 12 and the sustain electrode 13 already stored at the time of entering the setup period, and discharge in the positive direction between the scan electrode 12 and the sustain electrode 13 starts. Voltage Vs
Since it is lower than p, weak discharge does not occur.

Next, the potential difference due to the voltage of the setup pulse SP gradually increased by the ramp waveform and the wall potential difference between the scan electrode 12 and the sustain electrode 13 already stored at the time of entering the setup period are calculated. From the point in time when the total voltage exceeds the positive discharge start voltage Vsp, a weak positive discharge starts between the scan electrode 12 and the sustain electrode 13, and the setup pulse S
It continues until the voltage of P reaches the maximum voltage Vcp.

Therefore, in this embodiment, similarly to the first embodiment, in the wall charge accumulation period CS1 between scan electrode 12 and sustain electrode 13, scan electrode 12 and sustain electrode 13 , The wall charge is gradually accumulated, and a large negative wall potential difference is formed.

Next, while the voltage of the setup pulse SP applied to the scan electrode 12 is maintained at the maximum voltage Vcp, the voltage of the setup pulse ST applied to the sustain electrode 13 is raised to the setup voltage Vup. After that, the voltage of the setup pulse SP is dropped at once by the intermediate voltage Vb, and further gradually reduced by the ramp waveform.

At this time, during a period in which the voltage of the setup pulse SP decreases from the maximum voltage Vcp by the intermediate voltage Vb, the voltage of the setup pulse SP applied to the scan electrode 12 and the voltage of the setup pulse ST applied to the sustain electrode 13 Of the potential difference between the scan electrode 12 and the sustain electrode 13 and the wall potential difference between the scan electrode 12 and the sustain electrode 13 which have already been stored are equal to the discharge start voltage Vsn in the negative direction between the scan electrode 12 and the sustain electrode 13.
Since it is higher, a weak discharge does not occur.

Next, the setup pulse SP is gradually reduced by the ramp waveform, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 and the potential difference due to the voltage applied to the scan electrode 12 and the sustain electrode 13 are summed. When the voltage exceeds the negative discharge start voltage Vsn, a weak negative discharge starts between the scan electrode 12 and the sustain electrode 13 and continues until the voltage of the setup pulse SP reaches 0V.

Therefore, in the present embodiment, similarly to the first embodiment, in the wall charge reduction period CS2 between scan electrode 12 and sustain electrode 13, this weak discharge causes scan electrode 12 and sustain electrode 13 to fall. The wall charge stored between the scan electrode 12 and the sustain electrode 13 gradually decreases, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 is adjusted to various states by adjusting the setup voltage Vup applied to the sustain electrode 13. be able to.

Next, the scan electrode 12 and the address electrode 1
1 will be described. Similarly to the above, during the period in which the voltage of the setup pulse SP is from 0 V to the intermediate voltage Vb, the potential difference between the intermediate voltage Vb and the scan electrode 12 and the address electrode 11 already stored at the time of entering the setup period. The voltage obtained by summing the wall potential difference is the scan electrode 12 and the address electrode 11.
And weak discharge does not occur because the voltage is lower than the discharge start voltage Vdp in the positive direction.

Next, the potential difference due to the voltage of the setup pulse SP gradually increased by the ramp waveform and the wall potential difference between the scan electrode 12 and the address electrode 11 already stored at the time of entering the setup period are calculated. From the point in time when the summed voltage exceeds the positive firing voltage Vdp between the scan electrode 12 and the address electrode 11,
A weak discharge in the positive direction starts between the scan electrode 12 and the address electrode 11, and continues until the voltage of the setup pulse SP reaches the maximum voltage Vcp.

Therefore, in this embodiment, as in the first embodiment, the scan electrode 12 and the address electrode 1
In the wall charge accumulation period CD1 between the scan electrodes 12 and 1, the weak discharge gradually stores wall charges between the scan electrode 12 and the address electrode 11, and a large negative wall potential difference is formed.

Next, the voltage applied to the address electrode 11 remains at 0 V even if the voltage of the setup pulse SP falls at once at the intermediate voltage Vb and is further reduced gradually to 0 V by the ramp waveform. Therefore, the sum of the wall potential difference between the scan electrode 12 and the address electrode 11 and the potential difference due to the setup pulse SP does not exceed the negative discharge start voltage Vdn between the scan electrode 12 and the address electrode 11, No discharge occurs during this period.

Thereafter, after the voltage of the setup pulse SP is maintained at 0 V for a predetermined time, the voltage is gradually decreased in the negative direction by a ramp waveform. When the voltage exceeds the discharge start voltage Vdn in the negative direction, the weak discharge occurs. Is started and continued until the voltage of the setup pulse SP reaches the minimum voltage Vcn.

Therefore, also in the present embodiment, the scan electrode 12 and the address electrode 1 are similar to the first embodiment.
During the wall charge reduction period CD2 between the scan electrodes 12 and 1, the wall charge stored between the scan electrode 12 and the address electrode 11 gradually decreases due to the weak discharge, and the minimum voltage Vcn of the setup pulse SP is adjusted. The wall potential difference between the scan electrode 12 and the address electrode 11 can be adjusted.

As described above, also in this embodiment, the same effects as those of the first embodiment can be obtained, and
Discharge start voltage Vs between electrodes during setup period
By raising or lowering the voltage of the setup pulse SP at a stretch within a range not exceeding p, Vsn, Vdp, Vdn, the setup period can be shortened. Therefore, by transferring the shortened time to the maintenance period, the maintenance period can be made longer,
The light emission luminance can be increased.

The ramp rate of the setup pulse SP for stably performing the weak discharge is the same as that in the first embodiment.

(Third Embodiment) Next, a plasma display device according to a third embodiment of the present invention will be described. The difference between the plasma display device of the third embodiment and the plasma display device of the first embodiment is that the setup circuit 52 shown in FIG. 3 is changed to a setup circuit described below. Is similar to that of the first embodiment, and only different points will be described in detail below.

FIG. 11 is a circuit diagram showing a configuration of a setup circuit used in the plasma display device according to the third embodiment.

The setup circuit 52b shown in FIG.
It includes transistors Q81 to Q85, resistors R81 and R82, a capacitor C81, and power supply terminals V81 and V82.

One end of the transistor Q81 is connected to the power terminal V8
1 and the other end is connected to the node N81, and the control signal S81 is input to the gate. Power supply terminal V81
Has a maximum voltage Vcp which is a setup voltage of the positive polarity.
Is applied, and in the present embodiment, for example, a voltage of 450 V is applied. One end of the transistor Q82 is connected to the node N
81, the other end is connected to a ground terminal, and a control signal S81 is input to its gate. Resistance R81 is connected between nodes N81 and N82. Transistor Q83 has one end connected to node N82, the other end connected to a ground terminal, and a control signal S83 input to its gate. Transistor Q84 has one end connected to node N83 via resistor R82, the other end connected to power supply terminal V82, and a control signal S84 input to its gate. The minimum voltage Vcn, which is a negative setup voltage, is applied to the power supply terminal V82. In the present embodiment, for example, a voltage of −100 V is applied. Transistor Q
85 has one end connected to a node N82 and the other end connected to a node N82.
The control signal S85 is input to its gate. Capacitor C81 is connected between node N83 and a ground terminal. The voltage of node N83 is output as setup pulse SP.

In this embodiment, the setup circuit 52
b, 55, the address driver 2, the scan driver 3, and the sustain driver 4 correspond to an adjusting unit, a setup adjusting unit, a wall charge accumulating unit, and a wall charge reducing unit, and the other components are the same as those in the first embodiment.

FIG. 12 is a timing chart representing an operation of the setup circuit 52b shown in FIG. 11 during a setup period. FIG. 12 shows the control signals S81 to S85 and the setup pulse SP of FIG. The control signals S81 to S85 are signals generated in the setup circuit 52b based on the horizontal synchronization signal H, the vertical synchronization signal V, and the like.

First, in the period immediately before the period A, the control signal S81 is at the low level, the transistor Q81 is turned off, the control signal S82 is at the low level, the transistor Q82 is turned off, and the control signal S83 is at the high level. Yes,
The transistor Q83 is turned on, the control signal S84 is at a low level, the transistor Q84 is turned off, and the control signal S84 is turned off.
85 is at the high level, and the transistor Q85 is on. Therefore, node N83 is connected to transistor Q8.
5, Q83 to the ground terminal, and the setup pulse SP is output at the ground potential (0 V).

Next, in the period A, the control signal S81 goes high, the transistor Q81 turns on, the control signal S83 goes low, and the transistor Q83 turns off. Therefore, the node N83 is connected to the transistor Q
85, Q81 and a power supply terminal V81 via a resistor R81.
Connected to. At this time, the voltage of the node N83 increases exponentially with a time constant determined by the resistance value of the resistor R81 and the capacitance of the capacitor C81, and the maximum voltage Vc
rise to p. Therefore, the setup pulse SP
Rises from 0 V to the maximum voltage Vcp by a charge / discharge waveform as shown in the drawing, which changes sharply at first and then gradually, and is held at the maximum voltage Vcp. It is preferable that the time constant is set so that the voltage of the setup pulse SP is sufficiently saturated during the period A.

Next, in the period B, the control signal S81 goes low, the transistor Q81 turns off, the control signal S82 goes high, and the transistor Q82 turns on. Therefore, the node N83 is connected to the transistor Q
85, Q82 and a resistor R81 connected to the ground terminal. At this time, the voltage of the node N83 is
, And decreases exponentially with a time constant determined by the resistance of the capacitor C81 and drops to the ground potential. Therefore, the setup pulse SP falls from the maximum voltage Vcp to 0 V by a charge / discharge waveform as shown in the drawing, which changes sharply at first and then changes slowly, and is held at the ground potential. Note that the above time constant is preferably set such that the voltage of the setup pulse SP is sufficiently saturated during the period B.

Next, in a period C, the control signal S82 goes low, the transistor Q82 turns off, the control signal S84 goes high, the transistor Q84 turns on, the control signal S85 goes low, and the transistor Q85 turns off. Therefore, node N83 is connected to power supply terminal V via resistor R82 and transistor Q84.
82. At this time, the voltage of the node N83 becomes
It decreases exponentially with a time constant determined by the resistance value of the resistor R82 and the capacitance of the capacitor C81, and drops to the minimum voltage Vcn. Therefore, the setup pulse SP falls from 0 V to the minimum voltage Vcn by the charge / discharge waveform as shown in the drawing, which changes sharply at first, and then changes slowly, and is held at the minimum voltage Vcn. It should be noted that the above time constant indicates that the voltage of the setup pulse SP
It is preferable to set so as to sufficiently saturate the inside.

Finally, in the period D, the control signal S83
Goes high, the transistor Q83 turns on, the control signal S84 goes low, and the transistor Q84
Turns off, the control signal S85 goes high, and the transistor Q85 turns on. Therefore, the node N83 is connected to the ground terminal via the transistors Q85 and Q83, and the setup pulse SP rises to the ground potential at once, and is maintained at the ground potential.

Since the PDP 1 to which the setup pulse SP is applied is a capacitive load, the resistance values of the resistors R81 and R82 and the capacitance of the capacitor C81 are determined in consideration of this capacitance.

FIG. 13 is a timing chart showing drive voltages applied to each electrode of PDP 1 of the present embodiment using setup circuit 52b shown in FIG. Note that the drive voltage other than the setup period shown in FIG.
Since the driving voltage is the same as that shown in FIG. 5, the description thereof is omitted, and only the setup period will be described in detail below.

First, the setup operation between scan electrode 12 and sustain electrode 13 will be described. FIG.
As shown in FIG. 3, the setup pulse SP is simultaneously applied to all the scan electrodes 12 during the setup period. The setup pulse SP rises from 0 V to the maximum voltage Vcp by a charge / discharge waveform as shown in FIG.
p. On the other hand, both the address electrode 11 and the sustain electrode 13 are maintained at 0V.

At this time, the scan electrode 1 already stored at the time when the voltage of the setup pulse SP enters the setup period and the potential difference due to the setup pulse SP.
No weak discharge occurs during a period in which a voltage obtained by adding the wall potential difference between the scan electrode 2 and the sustain electrode 13 is lower than the positive discharge start voltage Vsp between the scan electrode 12 and the sustain electrode 13.

Next, the potential difference due to the voltage of the setup pulse SP gradually increased by the charging / discharging waveform, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 already stored at the time of entering the setup period are described. From the point at which the voltage exceeds the positive discharge start voltage Vsp, a weak positive discharge starts between the scan electrode 12 and the sustain electrode 13, and the setup pulse S
It continues until the voltage of P reaches the maximum voltage Vcp.

Therefore, in the present embodiment, similarly to the first embodiment, in the wall charge accumulation period CS1 between scan electrode 12 and sustain electrode 13, scan electrode 12 and sustain electrode 13 , The wall charge is gradually accumulated, and a large negative wall potential difference is formed.

Next, while the voltage of the setup pulse SP applied to the scan electrode 12 is maintained at the maximum voltage Vcp, the voltage of the setup pulse ST applied to the sustain electrode 13 rises to the setup voltage Vup. Thereafter, the setup pulse SP falls from the maximum voltage Vcp to 0 V by a charge / discharge waveform as shown in FIG.
It is kept at the ground potential.

At this time, the voltage of the setup pulse SP applied to the scan electrode 12 and the sustain electrode 1
3 and the sum of the potential difference caused by the voltage of the setup pulse ST applied to the scan electrode 12 and the already stored wall potential difference between the scan electrode 12 and the sustain electrode 13 is a negative voltage between the scan electrode 12 and the sustain electrode 13. In the period higher than the discharge start voltage Vsn in the direction, the weak discharge does not occur.

Next, the setup pulse SP is further reduced gradually by the charge / discharge waveform, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 and the potential difference due to the voltage applied to the scan electrode 12 and the sustain electrode 13 are reduced. The summed voltage is the discharge start voltage Vsn in the negative direction.
, A weak discharge in the negative direction starts between the scan electrode 12 and the sustain electrode 13 and continues until the voltage of the setup pulse SP reaches 0V.

Therefore, in the present embodiment, similarly to the first embodiment, in the wall charge reduction period CS2 between the scan electrode 12 and the sustain electrode 13, the scan electrode 12 and the sustain electrode 13 The wall charge stored between the scan electrode 12 and the sustain electrode 13 gradually decreases, and the wall potential difference between the scan electrode 12 and the sustain electrode 13 is adjusted to various states by adjusting the setup voltage Vup applied to the sustain electrode 13. be able to.

Next, the scan electrode 12 and the address electrode 1
1 will be described. Similarly to the above, the voltage obtained by summing the potential difference due to the setup pulse SP and the wall potential difference between the scan electrode 12 and the address electrode 11 already stored at the time of entering the setup period becomes the scan electrode 12 and the address electrode 11. No weak discharge occurs during a period lower than the positive-direction discharge start voltage Vdp.

Next, the potential difference due to the voltage of the setup pulse SP gradually increased by the charge / discharge waveform and the wall potential difference between the scan electrode 12 and the address electrode 11 already stored at the time of entering the setup period are described. From the point in time when the total voltage exceeds the discharge start voltage Vdp in the positive direction between the scan electrode 12 and the address electrode 11,
A weak discharge in the positive direction starts between the scan electrode 12 and the address electrode 11, and continues until the voltage of the setup pulse SP reaches the maximum voltage Vcp.

Therefore, in this embodiment, as in the first embodiment, the scan electrode 12 and the address electrode 1
In the wall charge accumulation period CD1 between the scan electrodes 12 and 1, the weak discharge gradually stores wall charges between the scan electrode 12 and the address electrode 11, and a large negative wall potential difference is formed.

Next, even if the voltage of the setup pulse SP is reduced from the maximum voltage Vcp to 0 V by the charge / discharge waveform, the voltage applied to the address electrode 11 remains at 0 V. Is the sum of the wall potential difference between the scan electrode 12 and the potential difference due to the setup pulse SP.
, Does not exceed the discharge start voltage Vdn in the negative direction, and no discharge occurs during this period.

Thereafter, after the voltage of the setup pulse SP is maintained at 0 V for a predetermined time, and further gradually reduced in the negative direction by the charge / discharge waveform, the voltage becomes slightly weaker when the voltage exceeds the discharge start voltage Vdn in the negative direction. The discharge is started and is continued until the voltage of the setup pulse SP reaches the minimum voltage Vcn.

Therefore, in this embodiment, as in the first embodiment, the scan electrode 12 and the address electrode 1
In the wall charge reduction period CD2 between 1 and 1, the wall charge stored between the scan electrode 12 and the address electrode 11 gradually decreases due to the weak discharge, and the minimum voltage Vcn of the setup pulse SP is adjusted. The wall potential difference between the scan electrode 12 and the address electrode 11 can be adjusted.

As described above, also in this embodiment, the same effects as those of the first embodiment can be obtained.
During the setup period, the discharge start voltage Vs between the electrodes is calculated using the charge / discharge waveform by the resistor and the capacitor.
By setting the voltage of the setup pulse SP to rise or fall to some extent steeply within a range not exceeding p, Vsn, Vdp, and Vdn, and then gradually changing the voltage, the setup period can be shortened while generating a weak discharge, and , The configuration of the setup circuit can be simplified.

The change rate of the charge / discharge waveform after exceeding the discharge start voltage of the setup pulse SP for stably performing the weak discharge is in the same range as the change rate at the time of the weak discharge by the ramp waveform.

(Fourth Embodiment) Next, a plasma display device according to a fourth embodiment of the present invention will be described. FIG. 14 is a block diagram showing a configuration of a plasma display device according to the fourth embodiment of the present invention. The difference between the plasma display device shown in FIG. 14 and the plasma display device shown in FIG. 1 is that the setup circuit 55 shown in FIG. 1 is changed to a setup circuit 55a that outputs a setup pulse ST ′ having a waveform similar to the setup pulse SP. The write / erase generation circuit 53 shown in FIG. 1 is changed to a write / erase generation circuit 53a for adjusting the wall potential difference between the scan electrode 12 and the sustain electrode 13 by changing the pulse width of the erase pulse Pe. Since the other points are the same as those of the plasma display device shown in FIG. 1, the same portions are denoted by the same reference numerals, and only different points will be described in detail below.

A discharge control circuit 5a shown in FIG. 14 includes sustain discharge generation circuits 51 and 54, and setup circuits 52 and 55a.
And a write / erase generating circuit 53a. The horizontal synchronization signal H and the vertical synchronization signal V are input to the setup circuit 55a and the write / erase generation circuit 53a. The write / erase generation circuit 53a operates in the same manner as the write / erase generation circuit 53 shown in FIG. 1, and erases by changing the timing at which the control signal S11 goes low and the control signal S13 goes high. The pulse width of the pulse Pe is controlled to adjust the wall potential difference between the scan electrode 12 and the sustain electrode 13.

The setup circuit 55a outputs the sustain driver basic drive signal SU in which the setup pulse ST 'is superimposed on the sustain discharge signal input from the sustain discharge generation circuit 54, to the scan driver 3.

More specifically, the setup circuit 55a
In the setup period, the difference between the voltage of the setup pulse ST ′ applied to the sustain electrode 13 and the voltage of the setup pulse SP applied to the scan electrode 11 does not generate a weak discharge between the scan electrode 12 and the sustain electrode 13. The setup pulse ST ′ that changes with respect to the setup pulse SP so as to fall within the range.
Is output. Therefore, the setup pulse ST '
Need not necessarily have the same waveform as the setup pulse SP.

For example, as a setup pulse ST ', a ramp waveform is used to change the setup voltage V from the ground potential.
up, and maintained at the setup voltage Vup for a predetermined period of time.
A waveform falling from p to the ground potential is used. The setup circuit 55a in this case can be configured in the same manner as the setup circuit 52 shown in FIG. 3 which outputs a similar waveform except that the setup circuit 55a further drops beyond the ground potential, and a detailed description thereof will be omitted.

In this embodiment, the setup circuit 5
2, 55a, address driver 2, scan driver 3
And the sustain driver 4 corresponds to an adjusting unit, a first adjusting unit, a wall charge accumulating unit, and a wall charge reducing unit, and the write / erase generating circuit 53a, the sustain discharge generating circuit 54,
The scan driver 3 and the sustain driver 4 correspond to an adjusting unit, a second adjusting unit and an erasing pulse applying unit, the write / erase generating circuit 53a and the scan driver 3 correspond to a first voltage applying unit, and the other units are the first. This is the same as the embodiment.

FIG. 15 is a timing chart showing driving voltages applied to the respective electrodes of PDP 1 shown in FIG. The scan electrode 12 in the setup period shown in FIG.
Since the drive voltage other than the setup operation and the erase discharge operation between the scan electrode 12 and the sustain electrode 13 is the same as the drive voltage shown in FIG. 5, the description is omitted, and the connection between the scan electrode 12 and the sustain electrode 13 during the setup period is omitted. Only the setup operation and the erase discharge operation during this will be described in detail below.

As shown in FIG. 15, the setup pulse S is applied to all scan electrodes 12 during the setup period.
P is applied at the same time, and the setup pulse ST ′ is applied to all the sustain electrodes 13 at the same time. The setup pulse SP rises from the ground potential to the maximum voltage Vcp by the ramp waveform, is held at the maximum voltage Vcp for a predetermined period, and thereafter is 0 V from the maximum voltage Vcp by the ramp waveform.
Descend to On the other hand, the setup pulse ST 'rises from 0 V to the setup voltage Vup according to the ramp waveform, is held at the setup voltage Vup for a predetermined period, and thereafter, from the setup voltage Vup to 0 V according to the ramp waveform.
And held at 0V.

At this time, the potential difference between the scan electrode 12 and the sustain electrode 13 due to the setup pulse SP and the setup pulse ST ′ and the potential difference between the scan electrode 12 and the sustain electrode 13 already stored at the time of entering the setup period. A voltage obtained by summing the wall potential difference between the scan electrode 12 and the sustain electrode 13 forms a positive firing voltage Vsp and a negative firing voltage Vsp between the scan electrode 12 and the sustain electrode 13.
Since the voltage of the setup pulse ST is set so as not to exceed sn, a weak discharge does not occur between the scan electrode 12 and the sustain electrode 13 during the setup period.

Therefore, in the present embodiment, the wall potential difference between scan electrode 12 and sustain electrode 13 does not change during the setup period, and the wall potential difference adjusted in the last subfield immediately before the setup period is equal to the wall potential difference. Will keep. That is, in the present embodiment, the write / erase generation circuit 53a adjusts the pulse width of the erase pulse Pe by the write / erase generating circuit 53a at the end of the sustain period of each subfield, not the setup period, so that the scan electrode 12 and the sustain electrode 13 The wall potential difference between them is adjusted. Therefore, also in the present embodiment, the wall potential difference between scan electrode 12 and sustain electrode 13 is changed to various states by adjusting the pulse width of erase pulse Pe applied to scan electrode 11 at the end of the sustain period. Can be adjusted.

The scan electrode 12 and the address electrode 1
1 is the same as in the first embodiment, and adjusts the minimum voltage Vcn of the setup pulse SP to adjust the wall potential difference between the scan electrode 12 and the address electrode 11. Can be.

As described above, in the present embodiment, the adjustment of the wall potential difference between scan electrode 12 and address electrode 11 is performed during the setup period, and the adjustment of the wall potential difference between scan electrode 12 and sustain electrode 13 is performed. Can be performed by the erasing discharge at the end of the sustain period, so that each adjustment can be performed completely separately. Therefore, each adjustment can be performed with high precision without being affected by the other discharge, and a state suitable for address discharge can be achieved with higher precision. Also, in the weak discharge used for the former adjustment, since only very weak light emission is generated, the brightness level of black display does not increase and the contrast of the display screen does not deteriorate.

The voltage and polarity of each drive pulse of the address electrode 11, scan electrode 12, and sustain electrode 13 according to the present invention are not particularly limited to the above examples, and various voltages may be used without departing from the spirit of the present invention. And reverse polarity can be used.

[0244]

According to the present invention, the wall potential difference between the first electrode and the third electrode is adjusted before the address discharge, and the first electrode and the second electrode are adjusted independently of this adjustment. Since the wall potential difference between the electrodes is adjusted, the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode are adjusted to desired values. It can be adjusted with high precision. As a result, the wall charges formed on the first to third electrodes can be adjusted to an optimal state for the address discharge, and the address discharge can be stably performed at a low voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a main part of a scan driver and a sustain discharge generating circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a setup circuit shown in FIG. 2;

FIG. 4 is a timing chart showing an operation of the setup circuit shown in FIG. 3 during a setup period;

FIG. 5 is a timing chart showing a driving voltage applied to each electrode of the PDP of FIG. 1;

6 is a diagram for explaining an example of a process of adjusting a wall potential difference between a scan electrode and a sustain electrode during the setup period shown in FIG. 5;

FIG. 7 is a view for explaining an example of a process of adjusting a wall potential difference between a scan electrode and an address electrode during the setup period shown in FIG. 5;

FIG. 8 is a circuit diagram showing a configuration of a setup circuit used in a plasma display device according to a second embodiment of the present invention.

9 is a timing chart showing an operation of the setup circuit shown in FIG. 8 during a setup period.

FIG. 10 is a timing chart showing a drive voltage applied to each electrode of the PDP according to the present embodiment using the setup circuit shown in FIG. 8;

FIG. 11 is a circuit diagram showing a configuration of a setup circuit used in a plasma display device according to a third embodiment of the present invention.

FIG. 12 is a timing chart showing an operation of the setup circuit shown in FIG. 11 during a setup period;

FIG. 13 is a timing chart showing a drive voltage applied to each electrode of the PDP of the present embodiment using the setup circuit shown in FIG. 11;

FIG. 14 is a block diagram showing a configuration of a plasma display device according to the first embodiment of the present invention.

FIG. 15 is a timing chart showing a drive voltage applied to each electrode of the PDP shown in FIG.

FIG. 16 is a schematic diagram mainly showing a configuration of a PDP of a conventional plasma display device.

FIG. 17 is a schematic sectional view of a three-electrode surface discharge cell in an AC type PDP.

FIG. 18 is a diagram for explaining the ADS method.

FIG. 19 is a view for explaining an address / sustain simultaneous driving method;

FIG. 20 is a timing chart showing a drive voltage of each electrode according to a conventional simultaneous address and sustain drive method.

[Explanation of symbols]

Reference Signs List 1 PDP 2 Address driver 3 Scan driver 4 Sustain driver 5 Discharge control circuit 6 A / D converter 7 Scanning number conversion unit 8 Subfield conversion unit 11 Address electrode 12 Scan electrode 13 Sustain electrode 14 Discharge cell 51, 54 Sustain discharge generation circuit 52 , 52a, 52b, 55, 55b Setup circuit 53, 53a Write / erase generation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Ohira 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Hidehiko Shoji 1006 Odakadoma Kadoma, Osaka Pref. Matsushita Electric Industrial F Terms (reference) 5C080 AA05 DD26 DD30 EE29 FF12 HH02 HH04 HH07 JJ02 JJ03 JJ04 JJ06

Claims (20)

[Claims] A plurality of first electrodes arranged in a first direction; a plurality of second electrodes arranged in a second direction intersecting the first direction; and a plurality of first electrodes. A plurality of third electrodes arranged so as to be paired with the first electrode, and the first electrode and the third electrode before the address discharge by the first electrode and the second electrode. And a wall potential difference between the first electrode and the second electrode independently of the adjustment of the wall potential difference between the first electrode and the third electrode. A display device comprising: an adjustment unit that adjusts a potential difference. 2. The method according to claim 1, wherein the adjusting unit adjusts a wall potential difference between the first electrode and the third electrode during a setup period before the address period in which the address discharge is performed. And a setup adjusting means for adjusting the wall potential difference between the first electrode and the second electrode independently of the adjustment of the wall potential difference between the first electrode and the third electrode. The display device according to claim 1. 3. The apparatus according to claim 1, wherein the setup adjusting unit is arranged between the first electrode and the third electrode, and between the first electrode and the third electrode.
A first electrode which does not interfere with each other between the first electrode and the second electrode
And a second weak discharge, respectively, to accumulate wall charges between the first electrode and the third electrode and between the first electrode and the second electrode. Means, by causing a third weak discharge having a polarity opposite to that of the first weak discharge between the first electrode and the third electrode, And a fourth weak discharge having a polarity opposite to that of the second weak discharge is generated between the first electrode and the second electrode during a period different from the third weak discharge. 3. The display device according to claim 2, further comprising wall charge reduction means for reducing wall charges between the first electrode and the second electrode by performing the operation. 4. The first adjusting means for adjusting a wall potential difference between the first electrode and the second electrode in a setup period before an address period in which the address discharge is performed. And second adjusting means for adjusting a wall potential difference between the first electrode and the third electrode by an erase discharge for stopping a sustain discharge performed after the address period. The display device according to claim 1. 5. The first adjusting means, wherein the first electrode and the second electrode are caused to perform a weak discharge between the first electrode and the second electrode without causing any other interference. Wall charge accumulating means for accumulating wall charges between the first electrode and the first electrode by causing a weak discharge having a polarity opposite to that of the weak discharge between the first electrode and the second electrode. Wall charge reducing means for reducing wall charges between the first electrode and the second electrode by changing an erase pulse applied to the first electrode. 5. The display device according to claim 4, further comprising an erase pulse applying means for adjusting a wall potential difference between said third electrode and said third electrode. 6. The method according to claim 3, wherein the wall charge accumulating unit and the wall charge reducing unit generate the weak discharge by applying a drive pulse having a ramp waveform to the first electrode. 5. The display device according to 5. 7. The wall charge accumulating means and the wall charge reducing means apply a drive pulse having a waveform which changes sharply within a range not exceeding a discharge starting voltage and thereafter changes gradually to the first electrode. The display device according to claim 3, wherein the weak discharge is generated by the operation. 8. The wall charge accumulating unit and the wall charge reducing unit generate the weak discharge by applying a drive pulse having a waveform whose change amount decreases exponentially to the first electrode. The display device according to claim 3 or 5, wherein: 9. A sub-field dividing unit which temporally divides each field set for each of the first electrodes into a plurality of sub-fields for performing gradation display, wherein the adjusting unit comprises: Immediately after the adjustment means adjusts the wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the second electrode. The wall potential difference between the first electrode and the third electrode at the beginning of the subfield and the wall potential difference between the first electrode and the second electrode, and the wall potential difference at the beginning of the other subfields The first electrode and the third electrode are arranged such that a wall potential difference between the first electrode and the third electrode and a wall potential difference between the first electrode and the second electrode are equal. Wall potential difference between Claim, characterized in that adjusting the wall potential difference between the second electrode and the fine the first electrode 1
9. The display device according to any one of 8. 10. A first voltage applying means for applying a first pulse voltage of a predetermined polarity to the first electrode during an address period in which the address discharge is performed, and wherein the first pulse voltage is equal to the first pulse voltage. A second voltage applying means for applying a second pulse voltage having a polarity opposite to that of the first pulse voltage to the second electrode in accordance with image data, when the voltage is applied to the electrodes; And a third voltage applying means for applying a third voltage having a polarity opposite to that of the first pulse voltage to the third electrode, wherein the adjusting means comprises:
No discharge is generated between the first electrode and the third electrode even when only the first voltage is applied, and the first voltage is applied by applying the first pulse voltage and the second pulse voltage.
The first electrode and the third electrode so that a discharge is induced between the first electrode and the third electrode by an address discharge between the first electrode and the second electrode. The display device according to any one of claims 1 to 9, wherein a wall potential difference between the first electrode and the second electrode is adjusted between the first electrode and the second electrode. 11. A plurality of first electrodes arranged in a first direction, a plurality of second electrodes arranged in a second direction intersecting with the first direction, and the plurality of first electrodes. And a plurality of third electrodes arranged so as to be paired with each other, wherein the first electrode and the second electrode perform an address discharge before the address discharge. Adjusting the wall potential difference between the first electrode and the third electrode, and adjusting the wall potential difference between the first electrode and the third electrode independently of the adjustment of the wall potential difference between the first electrode and the third electrode. A method for driving a display device, comprising: adjusting a wall potential difference between the display device and the second electrode. 12. The adjusting step includes adjusting a wall potential difference between the first electrode and the third electrode during a setup period before an address period in which the address discharge is performed, and adjusting the first electrode and the first electrode. Adjusting the wall potential difference between the first electrode and the second electrode independently of adjusting the wall potential difference between the first electrode and the third electrode. 12. The method for driving a display device according to item 11. 13. The adjusting step in the setup period, wherein the adjusting step is performed between the first electrode and the third electrode and between the first electrode and the third electrode.
A first electrode which does not interfere with each other between the first electrode and the second electrode
And accumulating wall charges between the first electrode and the third electrode and between the first electrode and the second electrode by causing a second weak discharge, respectively. By causing a third weak discharge having a polarity opposite to that of the first weak discharge to be performed between the first electrode and the third electrode, a distance between the first electrode and the third electrode is reduced. Reducing a wall charge and causing a fourth weak discharge having a polarity opposite to that of the second weak discharge to be performed between the first electrode and the second electrode during a period different from the third weak discharge. 13. The method according to claim 12, further comprising: reducing a wall charge between the first electrode and the second electrode. 14. The adjusting step, comprising: adjusting a wall potential difference between the first electrode and the second electrode during a setup period before an address period in which the address discharge is performed; Adjusting the wall potential difference between the first electrode and the third electrode by an erasing discharge for stopping a sustain discharge performed after the period. Drive method. 15. The step of adjusting the first and second electrodes, wherein the first electrode is subjected to a weak discharge that does not interfere with another between the first electrode and the second electrode. Accumulating wall charges between the first electrode and the second electrode; and performing the weak discharge having a polarity opposite to that of the weak discharge between the first electrode and the second electrode. Reducing the wall charge between the first electrode and the second electrode, and the step of adjusting the first and third electrodes comprises:
15. The method according to claim 14, further comprising the step of changing an erase pulse applied to the first electrode to adjust a wall potential difference between the first electrode and the third electrode. 16. The wall charge accumulating step and the wall charge decreasing step include a step of generating a weak discharge by applying a drive pulse having a ramp waveform to the first electrode. Item 16. The method for driving a display device according to item 13 or 15. 17. The wall charge accumulating step and the wall charge decreasing step apply a drive pulse having a waveform that changes sharply within a range not exceeding a discharge starting voltage and then changes gradually to the first electrode. 16. The display device according to claim 13, further comprising the step of generating the weak discharge. 18. The step of generating a weak discharge by applying a drive pulse having a waveform whose change amount decreases exponentially to the first electrode in the wall charge accumulation step and the wall charge reduction step. The method for driving a display device according to claim 13, further comprising: 19. The method according to claim 19, further comprising the step of temporally dividing each field set for each of the first electrodes into a plurality of subfields for performing a gray scale display, wherein the adjusting step comprises: The wall potential difference between the first electrode and the third electrode and the first
The wall potential difference between the first electrode and the third electrode and the wall potential difference between the first electrode and the third electrode at the beginning of the subfield immediately after the wall potential difference between the first electrode and the second electrode are adjusted. The wall potential difference between the second electrode and the wall potential difference between the first electrode and the third electrode at the beginning of the other subfields and the wall potential difference between the first electrode and the second electrode So that the wall potential difference between them becomes equal.
19. The method according to claim 11, further comprising adjusting a wall potential difference between the first electrode and the third electrode and a wall potential difference between the first electrode and the second electrode. The method for driving a display device according to any one of the above. 20. applying a first pulse voltage of a predetermined polarity to the first electrode during an address period in which the address discharge is performed; and applying the first pulse voltage to the first electrode. Applying a second pulse voltage having a polarity opposite to that of the first pulse voltage to the second electrode in accordance with image data; and a polarity opposite to the first pulse voltage during the address period. Applying a third voltage to the third electrode, wherein the adjusting step further comprises applying the first electrode and the third electrode even if only the first pulse voltage and the third voltage are applied. No discharge is generated between the third electrode and the address discharge between the first electrode and the second electrode due to the application of the first pulse voltage and the second pulse voltage. The first The wall potential difference between the first electrode and the third electrode, and the first electrode and the second electrode, so that a discharge is induced between the first electrode and the third electrode. 12. The method according to claim 11, wherein a wall potential difference between the two is adjusted.
20. The method for driving a display device according to any one of claims to 19,