JP2001177511A - Communication processor and method for adjusting its received clock frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust the frequency of a received clock signal on-line. SOLUTION: When a reception signal 9 is received, a reception detection circuit 3 outputs a reception detection signal 7. An IC 2 for communication processing converts the signal 9 into reception data, and when an error exists in the reception data, a communication error signal 6 is outputted and remains as it is. A CPU 1 changes the frequencies of a received clock signal by setting another frequency in an internal register 10 when the signal 6 is outputted and remains as it is. When the IC 2 for communication processing releases the output of the signal 6, the frequency set in the register 10 is defined as a normal frequency of the frequency of the received clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication processing device for performing clock synchronous communication and a method for adjusting a reception clock frequency thereof.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional communication processing device for performing clock synchronous communication. As shown in FIG. 4, the conventional communication processing device includes a CPU 1, a communication processing IC 2, and a communication clock setting switch 11. The communication processing IC 2 is connected to the transmission path 14, and communication between the communication processing apparatuses is performed by transmitting and receiving a transmission signal via the transmission path 14. The transmission signal includes a transmission signal 8 transmitted to another communication processing device and a reception signal 9 received from another communication processing device.

The communication processing IC 2 has an internal register 10. In the communication processing IC 2, a reference clock signal (not shown) input from the outside is frequency-divided to a frequency set in the internal register 10 to generate a reception clock signal. The reception signal 9 is sampled by the reception clock signal and converted into reception data.

[0004] An address bus 4 and a data bus 5 are connected between the CPU 15 and the internal register 10 of the communication processing IC 2. The CPU 15 controls the operation of the communication processing IC 2 via these buses. The communication clock setting switch 11 can set several patterns of a predetermined frequency set in the internal register 10.
Any one of the predetermined frequencies is designated. CPU 15 is a communication clock setting switch 1
The predetermined frequency designated by 1 is set in the internal register 10.

In such a communication processing device, if the frequency of the transmission clock signal used when the transmission source converts the reception data into the reception signal 9 and the frequency of the reception clock signal do not match, the reception signal 9 is transmitted. Cannot receive correctly. In such a case, the communication processing IC 2 detects a communication error by performing an error detection process such as a cyclic redundancy check code (CRC) check. Communication processing IC when a communication error is detected
2 outputs a communication error detection signal 6.

The communication error detection signal 6 is initially at a high level (hereinafter, H). When the reception signal 9 is received and the communication processing IC 2 detects the communication error as described above, the communication error detection signal 6 remains at H. When the communication processing IC 2 does not detect a communication error, the level becomes low (hereinafter, L).

If the communication error detection signal 6 remains H, the CPU 15 determines that the communication error detection signal 6 has been output, and if the communication error detection signal 6 is L,
It is determined that the output of the communication error detection signal 6 has been released.
When the output of the communication error detection signal 6 is released, the CPU 15 performs communication error processing such as discarding the received data and displaying a communication error on a display device (not shown).

In the conventional communication processing device as described above, the frequency of the reception clock signal for converting the reception signal 9 into the reception data is specified by the communication clock setting switch 11. Therefore, when it is desired to change the frequency of the reception clock signal, it is necessary to change the designation of the communication clock setting switch 11. When changing the designation of the frequency set in the communication clock setting switch 11, it is necessary to temporarily suspend the communication.

FIG. 5 is a block diagram showing a configuration of a network constituted by a large number of communication processing devices. In the network shown in FIG. 5, one communication host device 12 and many communication terminal devices 13 are connected to one transmission line 14. Communication terminal device 13 of such a network
In the case where a conventional communication processing device is used, it is necessary to set the frequency of the communication clock setting switches 11 of all the communication terminal devices 13 to be the same. It is necessary to manage the frequency of the clock signal, such as recording settings such as the frequency of the clock signal.

[0010]

The above conventional communication processing apparatus has the following two problems. (1) When a reception clock signal for converting a reception signal into reception data is fixed during communication, and when the frequency of the reception clock signal does not match the frequency of the transmission clock signal, the communication is temporarily interrupted. The receive clock signal must be changed. (2) In a network to which a large number of communication processing devices are connected, it is necessary to make the frequency of the reception clock signal of all the communication processing devices the same, and the frequency of the transmission clock signal and the frequency of the reception clock signal of each communication processing device And had to manage.

An object of the present invention is to provide an information processing apparatus capable of adjusting the frequency of a reception clock signal online without having to manage the frequency of the transmission clock signal or the frequency of the reception clock signal. .

[0012]

In order to solve the above problem, the present invention converts a received transmission signal into reception data in synchronization with a reception clock signal divided into a frequency set in an internal register. A communication processing IC that outputs a communication error detection signal when an error is detected in the received data;
A communication processing device including a CPU for setting a frequency in the internal register, further comprising a reception detection unit that outputs a reception detection signal when the reception of the transmission signal is detected; If entered,
If the output of the communication error detection signal is not canceled even after a predetermined time has elapsed after monitoring the communication error detection signal, the frequency set in the internal register is changed to output the communication error detection signal. The frequency set in the internal register at the time of release is set as the frequency of the reception clock signal.

According to the information processing apparatus of the present invention, the reception detecting means for detecting the reception of the transmission signal and the CPU for adjusting the frequency of the reception clock signal are provided, so that the frequency of the reception clock signal can be changed even during communication. The transmission clock signal can be adjusted online, eliminating the need to manage the frequency of the transmission clock signal and the frequency of the reception clock signal used when the transmission signal is transmitted. it can.

In another communication processing apparatus according to the present invention, the reception detecting means outputs the reception detection signal assuming that the transmission signal has been received when the fluctuation of the transmission signal has continued for a predetermined time.

In the communication processing apparatus according to the present invention, the reception detecting means monitors the fluctuation of the transmission signal for a predetermined time to detect the reception of the transmission signal, and thereby detects the reception detection signal by the instantaneous fluctuation of the transmission signal due to noise or the like. Is no longer output, so that it is possible to accurately detect the reception of the transmission signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a communication processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings, components denoted by the same reference numerals are all the same components. FIG. 1 is a block diagram illustrating a configuration of a communication processing device according to the present embodiment. As shown in FIG. 1, the communication processing device of the present embodiment is different from the conventional communication processing device in that the communication processing device of the present embodiment does not include the communication clock setting switch 11 and newly includes the reception detection circuit 3.

The reception detection circuit 3 receives the reception signal 9 and detects the reception signal 9 when the fluctuation of the reception signal 9 between H and L is detected for a predetermined period of time. . The reception detection circuit 3 outputs the reception detection signal 7 to the CPU 1 when detecting the reception of the reception signal 9. The reception detection signal 7 is L in the initial state, becomes H when the reception of the reception signal 9 is detected, and becomes L when the reception of the reception signal 9 ends.

When the reception detection signal 7 is L, the CPU 1 determines that the reception signal 9 is not input,
When the reception detection signal 7 is H, it is determined that the reception signal 9 is input. When the reception detection signal 7 is input, the CPU 1 monitors the communication error detection signal 6 output from the communication processing IC 2. The CPU 1 sets a timer (not shown) and switches the frequency set in the internal register 10 to another frequency selected from the predetermined frequencies when the output of the communication error detection signal 6 has not been released for a predetermined time. . Then, the communication error detection signal 6
Is adjusted to the normal frequency of the received clock signal by adjusting the frequency set when the signal becomes L.

Next, the operation of the communication processing apparatus according to the present embodiment will be described in detail with reference to FIGS. FIG.
5 is a timing chart illustrating an operation of the communication processing device according to the embodiment. FIG. 2A is a timing chart illustrating an operation of the communication processing device according to the present embodiment at the start of communication.
FIG. 2B is a timing chart illustrating the operation of the communication processing device of the present embodiment when communication is interrupted. FIG. 2 (a),
(B) Both the reception signal 9, the reception detection signal 7,
The state of the fluctuation of the communication error detection signal 6 is shown.

First, the operation of the communication processing apparatus according to the present embodiment at the start of communication will be described with reference to FIG. When the reception signal 9 is not received, the reception detection signal 7
Is L, and the communication error detection signal 6 is H. When the reception signal 9 is transmitted from another communication processing device, the reception signal 9 fluctuates between H and L. When the fluctuation of the reception signal 9 continues for a predetermined time, the reception detection circuit 3 determines that the reception signal 9 has been received, and sets the reception detection signal 7 to H. A predetermined frequency is set in the internal register 10 of the communication processing IC 2 in advance, and the communication processing IC 2 divides the frequency of the reception clock signal to that frequency and synchronizes the reception signal 9 with the reception clock signal. Convert to The communication processing IC 2 performs error detection processing on the received data and, if an error is detected, keeps the communication error detection signal 6 at H.

The CPU 1 causes the timer to measure the time, and if the communication error detection signal 6 does not become L after a certain period of time, changes the frequency of the reception clock signal by setting another frequency in the internal register 10. . The communication processing IC 2 converts the reception signal 9 into reception data again at the frequency set in the internal register 10 and performs error detection processing of the reception data. Then, when the frequency of the transmission clock signal used when the reception signal 9 is transmitted from the communication host device 12 matches the frequency of the reception clock signal, no communication error occurs, and the communication error detection signal 6 becomes L. . When the communication error detection signal 6 becomes L, the CPU 1
Sets the frequency set in the internal register 10 at that time as the normal frequency of the received clock signal and ends the adjustment of the frequency of the received clock signal.

FIG. 2A shows a reception clock signal frequency adjustment period as a period during which the CPU 1 sets the frequency of the reception clock signal.

Next, a case where the reception signal 9 is temporarily interrupted will be described. FIG. 2B is a timing chart illustrating the operation of the communication processing device of the present embodiment when communication is interrupted.

As shown in FIG. 2B, when the reception signal 9 is temporarily interrupted, the reception detection circuit 3 sets the reception detection signal 7 to H level.
To L, and the communication processing IC 2 changes the communication error detection signal 6 from L to H. When the reception signal 9 is input again, the reception detection circuit 3 sets the reception detection signal 7 to L again.
To H. Then, the CPU 1 adjusts the frequency of the reception clock signal in the same manner as at the start of communication, and the frequency of the transmission clock signal and the frequency of the reception clock signal used when the reception signal 9 is transmitted from the upper communication device 12 are adjusted. If they match, the communication processing IC 2 outputs the communication error detection signal 6
From H to L. When the communication error signal 6 becomes L, the CPU 1 sets the frequency set in the internal register 10 at that time as the normal frequency of the reception clock signal, and ends the adjustment of the frequency of the reception clock signal.

FIG. 3 is a flowchart showing the operation of the CPU 1 in the communication processing device of the present embodiment. First,
The CPU 1 waits until the reception detection signal 7 becomes H (step 101). When the reception detection signal 7 becomes H, the CPU
1 starts a timer (not shown) (step 102) and checks whether or not the communication error detection signal 6 is L (step 103). When the communication error detection signal 6 is L,
The CPU 1 terminates the processing on the assumption that the frequency of the transmission clock signal used when the reception signal 9 is transmitted matches the frequency of the reception clock signal. If the communication error detection signal 6 is not L, the CPU 1 checks whether a timeout has occurred, and if no timeout has occurred, returns to step 103 (step 104). If a timeout has occurred in step 104, the CPU 1 checks whether all the predetermined frequencies have been set (step 1).
05), if a frequency that has not been set remains, the frequency is set in the internal register 10 (step 10).
6) Return to step 102. If all the frequencies have been set in step 105, the CPU 1
Performs a communication error process (step 107) and ends the process.

As described above, in the communication processing device of the present embodiment, the reception detection circuit 3 for detecting the reception of the reception signal 9,
By providing the CPU 1 that adjusts the frequency of the reception clock signal, the frequency of the transmission clock signal used when the reception signal 9 is transmitted and the frequency of the reception clock signal can be matched during communication. .

Further, in the communication processing apparatus of the present embodiment, the frequency of the transmission clock signal of the transmission source of the reception signal 9 is changed by adjusting the frequency of the reception clock signal every time the reception signal 9 is received. Even by changing the frequency of the reception clock signal, the reception signal 9 can be normally received.

[0028]

As described above, the communication processing device of the present invention includes the reception detection circuit for detecting the reception of the reception signal and the CPU for adjusting the frequency of the reception clock signal, so that the communication processing device can perform the communication during the communication. Since the frequency of the receive clock signal can be changed, the frequency of the receive clock signal can be adjusted online, and the frequency of the transmit clock signal used when the source of the receive signal used to transmit the receive signal and the receive It is not necessary to manage the frequency of the clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication processing device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the communication processing device according to the embodiment of the present invention.

FIG. 3 shows C in the communication processing apparatus according to the embodiment of the present invention;
6 is a flowchart illustrating an operation of a PU.

FIG. 4 is a block diagram illustrating a configuration of a conventional communication processing device.

FIG. 5 is a block diagram illustrating a configuration of a network including a plurality of communication processing devices.

[Description of Signs] 1, 15 CPU 2 Communication processing IC 3 Reception detection circuit 4 Address bus 5 Data bus 6 Communication error detection signal 7 Reception detection signal 8 Transmission signal 9 Reception signal 10 Internal register 11 Communication clock setting switch 12 Communication Upper device 13 Communication terminal device 14 Transmission line 101 to 107 Step

Claims (3)

[Claims] 1. A reception clock signal is divided by a frequency set in an internal register, a received transmission signal is converted into reception data in synchronization with the reception clock signal, and an error detection of the reception data is performed. A communication processing I that outputs a communication error detection signal when an error is detected in data
C, a communication processing device comprising: a CPU for setting a frequency in the internal register; further comprising: reception detection means for outputting a reception detection signal when the reception of the transmission signal is detected; When the signal is input, the communication error detection signal is monitored, and when the output of the communication error detection signal is not released even after a predetermined time has elapsed, the frequency set in the internal register is changed, A communication processing device, wherein the frequency set in the internal register when the output of the error detection signal is canceled is used as the frequency of the reception clock signal. 2. The communication processing apparatus according to claim 1, wherein the reception detecting unit outputs the reception detection signal assuming that the transmission signal has been received when the fluctuation of the transmission signal has continued for a predetermined time. 3. A reception of the transmission signal is detected by monitoring a fluctuation of the transmission signal for a predetermined time, and is output from the communication processing IC when an error is detected in the reception data converted from the transmission signal. The communication error detection signal is monitored and the setting of the reception clock signal set in the internal register of the communication processing IC for receiving the transmission signal is selected and switched from a predetermined frequency, and the output of the communication error detection signal is A method for adjusting a reception clock frequency of a communication processing device, wherein the frequency set in the internal register when the communication clock is released is used as the frequency of the reception clock signal.