JP2001177081A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001177081A JP2001177081A JP35605999A JP35605999A JP2001177081A JP 2001177081 A JP2001177081 A JP 2001177081A JP 35605999 A JP35605999 A JP 35605999A JP 35605999 A JP35605999 A JP 35605999A JP 2001177081 A JP2001177081 A JP 2001177081A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- semiconductor device
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、能動面に受光部を
備えた半導体チップを、基板の表面に実装して成る半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip having a light receiving portion on an active surface is mounted on a surface of a substrate.
【0002】[0002]
【従来の技術】図14は、ビデオカメラ等に搭載される
読取センサとしての半導体装置Aを示しており、この半
導体装置Aは、ウェハ上にCCD(charge coupled devi
ce)を形成して成る半導体チップ(CCDチップ)Cを、
基板Bの表面Baに実装することにより構成されてい
る。2. Description of the Related Art FIG. 14 shows a semiconductor device A as a reading sensor mounted on a video camera or the like. This semiconductor device A is mounted on a wafer by a CCD (charge coupled device).
ce) to form a semiconductor chip (CCD chip) C,
It is configured by mounting on the surface Ba of the substrate B.
【0003】上記半導体チップCは、能動面Caに受光
部(CCD)Chと複数の接続用電極Cc,Cc…とが形
成されており、一方、上記基板Bの表面Baには複数の
接続用電極Bc,Bc…が形成されている。In the semiconductor chip C, a light receiving portion (CCD) Ch and a plurality of connection electrodes Cc, Cc... Are formed on an active surface Ca, while a plurality of connection electrodes Cc are formed on a surface Ba of the substrate B. The electrodes Bc are formed.
【0004】また、上記半導体チップCは、接着剤Gを
介して基板Bの表面Baに固定されており、半導体チッ
プCにおける接続用電極Cc,Cc…と、基板Bにおけ
る接続用電極Bc,Bc…とは、それぞれボンディング
ワイヤW,W…を介して互いに接続されている。The semiconductor chip C is fixed to the surface Ba of the substrate B via an adhesive G. The connection electrodes Cc, Cc... Of the semiconductor chip C and the connection electrodes Bc, Bc Are connected to one another via bonding wires W, W, respectively.
【0005】[0005]
【発明が解決しようとする課題】ところで、上述した如
く基板Bと半導体チップCとをボンディングワイヤWで
接続している半導体装置Aでは、広い実装面積を必要と
することから大型化を免れず、延いては半導体装置Aを
搭載した機器の大型化をも招いてしまう。However, as described above, the semiconductor device A in which the substrate B and the semiconductor chip C are connected by the bonding wires W requires a large mounting area, so that the semiconductor device A is inevitably increased in size. As a result, the size of the device on which the semiconductor device A is mounted is also increased.
【0006】一方、近年における半導体装置の小型化、
薄型化の要求に応える技術として、基板の表面に半導体
チップを直接に実装するフリップチップ実装方法(フリ
ップチップボンディング法)が提供されている。On the other hand, recent miniaturization of semiconductor devices,
As a technology to meet the demand for thinning, a flip chip mounting method (flip chip bonding method) for mounting a semiconductor chip directly on the surface of a substrate has been provided.
【0007】ここで、上述した半導体装置Aにおける半
導体チップCは、その上下を反転させ、接続用電極C
c,Cc…を基板に対向させることで、基板に対するフ
リップチップ実装が可能となる。Here, the semiconductor chip C in the above-described semiconductor device A is turned upside down so that the connection electrode C
By making c, Cc... face the substrate, flip-chip mounting on the substrate becomes possible.
【0008】しかし、上述の如く半導体チップCをフリ
ップチップ実装した場合、半導体装置のコンパクト化は
達成されるものの、半導体チップCの受光部Chが接続
用電極Ccと同じ能動面Caに形成されているため、受
光部Chが基板Bに対向することとなり、該受光部Ch
への光照射が基板で遮られることで、読取センサとして
の機能を為さなくなってしまう。However, when the semiconductor chip C is flip-chip mounted as described above, the semiconductor device can be made compact, but the light receiving portion Ch of the semiconductor chip C is formed on the same active surface Ca as the connection electrode Cc. Therefore, the light receiving unit Ch faces the substrate B, and the light receiving unit Ch
Since the light irradiation on the substrate is blocked by the substrate, the function as a reading sensor cannot be performed.
【0009】一方、読取センサとしての確実な動作を確
保するには、半導体チップCの受光部Chに対して確実
に光が照射されるよう、従来の如く受光部Chを上方
(基板と反対方向)に向けて露出させることが望ましい
が、半導体チップCの接続用電極Ccは受光部Chと同
一の能動面Caに形成されているため、上記半導体チッ
プCを基板にフリップチップ実装することは不可能とな
る。On the other hand, in order to ensure a reliable operation as a reading sensor, the light receiving portion Ch of the semiconductor chip C is moved upward (in the direction opposite to the substrate) as in the conventional art so that light is reliably irradiated to the light receiving portion Ch. ) Is desirably exposed, but since the connection electrode Cc of the semiconductor chip C is formed on the same active surface Ca as the light receiving portion Ch, it is not possible to flip-chip mount the semiconductor chip C on the substrate. It becomes possible.
【0010】本発明は、前記実状に鑑みて、光照射に基
づく半導体チップの動作を損なうことなく、可及的なコ
ンパクト化を達成し得る半導体装置の提供を目的とする
ものである。The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of achieving as small a size as possible without impairing the operation of a semiconductor chip based on light irradiation.
【0011】[0011]
【課題を解決するための手段】前記目的を達成するべ
く、本発明に関わる半導体装置は、能動面に受光部とと
もに接続用電極を設けた半導体チップと、該半導体チッ
プの実装域に開口を形成した基板とを具備し、半導体チ
ップの能動面を基板の表面に対向させ、かつ半導体チッ
プの受光部を基板の開口に臨ませる態様で、半導体チッ
プを基板の表面にフリップチップ実装している。In order to achieve the above-mentioned object, a semiconductor device according to the present invention comprises a semiconductor chip having a light receiving portion and a connection electrode on an active surface, and an opening formed in a mounting area of the semiconductor chip. The semiconductor chip is flip-chip mounted on the surface of the substrate such that the active surface of the semiconductor chip faces the surface of the substrate and the light receiving portion of the semiconductor chip faces the opening of the substrate.
【0012】また、本発明に関わる半導体装置は、能動
面に受光部を設けるとともに能動面と反対側の実装面に
接続用電極を設けた半導体チップを具備し、該半導体チ
ップの実装面を基板の表面に対向させて受光部を露呈さ
せる態様で、半導体チップを基板の表面にフリップチッ
プ実装している。A semiconductor device according to the present invention includes a semiconductor chip provided with a light receiving portion on an active surface and a connection electrode provided on a mounting surface opposite to the active surface, and the mounting surface of the semiconductor chip is mounted on a substrate. The semiconductor chip is flip-chip mounted on the surface of the substrate in such a manner that the light receiving portion is exposed to face the surface of the substrate.
【0013】[0013]
【発明の実施の形態】以下、実施例を示す図面に基づい
て、本発明を詳細に説明する。図1〜図4は、読取セン
サを構成する半導体装置に、本発明を適用した例を示し
ており、本発明に関わる半導体装置1は、基板2に半導
体チップ3を実装することによって構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments. 1 to 4 show an example in which the present invention is applied to a semiconductor device constituting a reading sensor. A semiconductor device 1 according to the present invention is configured by mounting a semiconductor chip 3 on a substrate 2. I have.
【0014】基板2は、酸化アルミニウム等から成るセ
ラミック材、エポキシ等の樹脂材、あるいは液晶ポリマ
ー等から成るフレキシブル材等から形成され、図3に示
す如く半導体チップ3の実装域には貫通した開口2oが
形成されている。The substrate 2 is made of a ceramic material such as aluminum oxide, a resin material such as epoxy, or a flexible material such as a liquid crystal polymer. As shown in FIG. 2o is formed.
【0015】また、基板2の表面2aには、導電材料か
ら成る配線パターン2pが形成されており、上記配線パ
ターン2pの所定位置には、後述する半導体チップ3の
各接続用電極3c,3c…と対応する、複数の接続用電
極2c,2c…が形成されている。A wiring pattern 2p made of a conductive material is formed on the surface 2a of the substrate 2. At predetermined positions of the wiring pattern 2p, connection electrodes 3c, 3c. , A plurality of connection electrodes 2c, 2c,.
【0016】一方、図4に示す如く半導体チップ3は、
ウェハの能動面3aに配線パターン(図示せず)が形成さ
れているとともに、CCD(charge coupled device)か
ら成る受光部3hが形成されており、上記配線パターン
の所定位置には受光部3hの周囲を囲う態様で複数の接
続用電極3c,3c…が形成されている。On the other hand, as shown in FIG.
A wiring pattern (not shown) is formed on the active surface 3a of the wafer, and a light receiving unit 3h formed of a charge coupled device (CCD) is formed, and a predetermined position of the wiring pattern surrounds the light receiving unit 3h. Are formed in a manner surrounding the connection electrodes 3c.
【0017】また、図2に示す如く、半導体チップ3に
おける各接続用電極3c,3c…の表面には、それぞれ
ハンダやAu(金)等の導電材料から成るバンプ4,4…
が、メッキ法やバンピング法によって形成されている。As shown in FIG. 2, bumps 4, 4,... Made of a conductive material such as solder or Au (gold) are provided on the surfaces of the connection electrodes 3c, 3c.
Are formed by a plating method or a bumping method.
【0018】上記半導体チップ3は、基板2の表面2a
に能動面3aを対向させた姿勢で、各バンプ4を介して
各接続用電極3cと基板2の各接続用電極2cとを接合
することにより、上記基板2の表面2aに対してフリッ
プチップ実装されている。The semiconductor chip 3 is provided on the surface 2 a of the substrate 2.
By connecting the connection electrodes 3c and the connection electrodes 2c of the substrate 2 via the bumps 4 in a posture in which the active surface 3a faces the flip-chip mounting on the surface 2a of the substrate 2, Have been.
【0019】ここで、図1および図2に示す如く、基板
2の所定位置に半導体チップ3を実装した状態におい
て、半導体チップ3における受光部3hは、基板2にお
ける開口2oに臨んで位置している。Here, as shown in FIGS. 1 and 2, in a state where the semiconductor chip 3 is mounted at a predetermined position on the substrate 2, the light receiving portion 3h of the semiconductor chip 3 is positioned facing the opening 2o of the substrate 2. I have.
【0020】また、図2に示す如く、上記半導体チップ
3の周囲と基板2との間隙には、基板2と半導体チップ
3との機械的な接合強度を向上させるべく、エポキシ樹
脂等から成る封止樹脂5が充填されている。As shown in FIG. 2, a gap between the periphery of the semiconductor chip 3 and the substrate 2 is sealed with an epoxy resin or the like in order to improve the mechanical bonding strength between the substrate 2 and the semiconductor chip 3. The sealing resin 5 is filled.
【0021】さらに、図1および図2に示す如く、基板
2における裏面2bには、基板2の開口2oから臨む半
導体チップ3の受光部3hを保護する目的で、ガラスプ
レートから成るカバー6が接着剤7によって取り付けら
れている。As shown in FIGS. 1 and 2, a cover 6 made of a glass plate is adhered to the back surface 2b of the substrate 2 for the purpose of protecting the light receiving portion 3h of the semiconductor chip 3 from the opening 2o of the substrate 2. It is attached by the agent 7.
【0022】因みに、上記構成の半導体装置1を製造す
るには、先ず基板2を用意するとともに、半導体チップ
3の各接続用電極3cにバンプ4を形成する。Incidentally, in order to manufacture the semiconductor device 1 having the above configuration, first, the substrate 2 is prepared, and the bumps 4 are formed on the connection electrodes 3c of the semiconductor chip 3.
【0023】次いで、基板2の所定位置に半導体チップ
3を搭載したのち、基板2の各接続用電極2c,2c…
と、半導体チップ3の各接続用電極3c,3c…とを、
加熱および加圧によって機械的かつ電気的に接続するこ
とで、基板2に半導体チップ3をフリップチップ実装す
る。Next, after mounting the semiconductor chip 3 at a predetermined position on the substrate 2, the connection electrodes 2 c, 2 c.
And the connection electrodes 3c of the semiconductor chip 3,
The semiconductor chip 3 is flip-chip mounted on the substrate 2 by being mechanically and electrically connected by heating and pressing.
【0024】基板2に半導体チップ3をフリップチップ
実装したのち、半導体チップ3の周囲と基板2との間隙
に封止樹脂5を充填する。このとき、基板2に形成され
た開口2oに、上述した封止樹脂5が入り込むことのな
いよう、上記隙間に対する封止樹脂5の供給方向や供給
量が、適宜に調整されることは言うまでもない。After the semiconductor chip 3 is flip-chip mounted on the substrate 2, the gap between the periphery of the semiconductor chip 3 and the substrate 2 is filled with a sealing resin 5. At this time, it goes without saying that the supply direction and the supply amount of the sealing resin 5 with respect to the gap are appropriately adjusted so that the above-described sealing resin 5 does not enter the opening 2o formed in the substrate 2. .
【0025】上述の如く充填した封止樹脂5を加熱して
硬化させたのち、基板2の裏面2bに接着剤7を塗布
し、この接着剤7によってカバー6を基板2の裏面2b
に取付けることで、読取センサとしての半導体装置1が
完成することとなる。After the sealing resin 5 filled as described above is heated and cured, an adhesive 7 is applied to the back surface 2b of the substrate 2, and the cover 6 is attached to the back surface 2b of the substrate 2 by the adhesive 7.
Is completed, the semiconductor device 1 as a reading sensor is completed.
【0026】上述した構成の半導体装置1では、基板2
に半導体チップ3をフリップチップ実装しているため、
基板2に対する半導体チップ3の実装面積が抑えられる
こととなる。In the semiconductor device 1 having the above configuration, the substrate 2
Since the semiconductor chip 3 is flip-chip mounted on the
The mounting area of the semiconductor chip 3 on the substrate 2 can be reduced.
【0027】また、基板2に半導体チップ3を実装した
状態において、半導体チップ3の受光部3hを基板2の
開口2oに臨ませことで、半導体チップ3の受光部3h
に対して確実に光照射が為されることとなる。In a state where the semiconductor chip 3 is mounted on the substrate 2, the light receiving portion 3 h of the semiconductor chip 3 faces the opening 2 o of the substrate 2 so that the light receiving portion 3 h
Is surely irradiated with light.
【0028】もって、上述した構成の半導体装置1で
は、光照射に基づく半導体チップ3の動作を損なうこと
なく、可及的なコンパクト化を達成することが可能とな
る。Therefore, in the semiconductor device 1 having the above-described configuration, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip 3 based on light irradiation.
【0029】ところで、本発明に関わる半導体装置は、
受光部を有する特定の半導体チップを、基板上に1個の
み実装した構成に限定されるものではなく、以下に説明
するように、基板上に特定の半導体チップとともに他の
電子部品を実装した構成をも含むことは言うまでもな
い。Incidentally, the semiconductor device according to the present invention comprises:
The configuration is not limited to a configuration in which only one specific semiconductor chip having a light receiving unit is mounted on a substrate, and a configuration in which other electronic components are mounted together with the specific semiconductor chip on the substrate, as described below. It goes without saying that it also includes
【0030】図5に示した半導体装置10は、基板12
に半導体チップ13をフリップチップ実装するととも
に、半導体チップ等の電子部品10A、10B、10
C、10Dを、基板12にフリップチップ実装すること
によって構成されている。なお、上記半導体装置10に
おいて、上述した半導体装置1と基本的に同一な構成要
素には、図1〜図4の符合に10を足した番号を付すこ
とで、構成要素に関する詳細な説明を省略する。The semiconductor device 10 shown in FIG.
The semiconductor chip 13 is flip-chip mounted on the electronic component 10A, and the electronic components 10A, 10B, 10
C and 10D are configured by flip-chip mounting on the substrate 12. In the semiconductor device 10, components that are basically the same as those of the semiconductor device 1 described above are given the same reference numerals as in FIGS. I do.
【0031】図6に示した半導体装置20は、基板22
に半導体チップ23をフリップチップ実装するととも
に、半導体チップ等の電子部品20A、20B、20
C、20Dを、基板22にハンダ付けすることによって
構成されている。なお、上記半導体装置20において、
上述した半導体装置1と基本的に同一な構成要素には、
図1〜図4の符合に20を足した番号を付すことで、構
成要素に関する詳細な説明を省略する。The semiconductor device 20 shown in FIG.
The semiconductor chip 23 is flip-chip mounted on the semiconductor chip and electronic components 20A, 20B, 20
C and 20D are soldered to the substrate 22. In the above semiconductor device 20,
The components basically the same as the semiconductor device 1 described above include:
A detailed description of components will be omitted by adding a number obtained by adding 20 to the reference numerals in FIGS.
【0032】図7に示した半導体装置30は、基板32
に半導体チップ33をフリップチップ実装し、かつ半導
体チップ等の電子部品30A、30B、30Dを基板3
2にフリップチップ実装するとともに、半導体チップ等
の電子部品30Cを基板32にハンダ付することによっ
て構成されている。なお、上記半導体装置30におい
て、上述した半導体装置1と基本的に同一な構成要素に
は、図1〜図4の符合に30を足した番号を付すこと
で、構成要素に関する詳細な説明を省略する。The semiconductor device 30 shown in FIG.
A semiconductor chip 33 is mounted on the substrate 3 by flip chip mounting, and electronic components 30A, 30B, 30D such as semiconductor chips are mounted on the substrate 3.
2 and an electronic component 30C such as a semiconductor chip is soldered to a substrate 32. In the semiconductor device 30, components that are basically the same as those of the semiconductor device 1 described above are given the same reference numerals as in FIGS. I do.
【0033】図8に示す半導体装置40は、異方性導電
接合材料48を用いて、基板42に半導体チップ43を
フリップチップ実装することで構成されている。なお、
上記半導体装置40は、異方性導電接合材料48を用い
ている点以外、図1〜図4の半導体装置1と基本的に同
一なので、半導体装置1と同一の要素には、図1〜図4
の符合に40を足した番号を付すことで、構成要素に関
する詳細な説明を省略する。A semiconductor device 40 shown in FIG. 8 is constructed by flip-chip mounting a semiconductor chip 43 on a substrate 42 using an anisotropic conductive bonding material 48. In addition,
The semiconductor device 40 is basically the same as the semiconductor device 1 of FIGS. 1 to 4 except that the anisotropic conductive bonding material 48 is used. 4
By adding a number obtained by adding 40 to the sign of, a detailed description of the components will be omitted.
【0034】因みに、上記構成の半導体装置40を製造
するには、先ず半導体チップ43の各接続用電極43
c,43c…にバンプ44を形成するとともに、基板4
2の表面42aに接続用電極42c,42c…を覆う態
様で異方性導電接合材料48を供給する。Incidentally, in order to manufacture the semiconductor device 40 having the above configuration, first, each connection electrode 43 of the semiconductor chip 43 is formed.
c, 43c... and the substrate 44
The anisotropic conductive bonding material 48 is supplied so as to cover the connection electrodes 42c, 42c,.
【0035】ここで、異方性導電接合材料48は、ペー
スト状の絶縁性樹脂48aに多数の導電粒子48b,4
8b…を混練して構成されている。なお、異方性導電接
合材料としては、導電粒子を含有した絶縁性樹脂をフィ
ルム状とした、いわゆる異方性導電フィルムを採用する
ことも可能である。Here, the anisotropic conductive bonding material 48 is formed by adding a large number of conductive particles 48b, 4 to a paste-like insulating resin 48a.
8b are kneaded. Note that as the anisotropic conductive bonding material, a so-called anisotropic conductive film in which an insulating resin containing conductive particles is formed into a film shape can be used.
【0036】基板42に異方性導電接合材料48を供給
したのち、基板42の所定位置に半導体チップ43を搭
載し、ボンディングツール(図示せず)によって半導体チ
ップ43を基板42に熱圧着する。After supplying the anisotropic conductive bonding material 48 to the substrate 42, the semiconductor chip 43 is mounted at a predetermined position on the substrate 42, and the semiconductor chip 43 is thermocompression-bonded to the substrate 42 by a bonding tool (not shown).
【0037】かくして、半導体チップ43の各バンプ4
4,44…と、基板42の各接続用電極42c,42c
…との間に、異方性導電接合材料48における導電粒子
48bが挟み込まれることで、基板42とが半導体チッ
プ43と電気的に接続され、また異方性導電接合材料4
8における絶縁性樹脂48aが熱硬化することで、基板
42と半導体装置43とが機械的に接合される。Thus, each bump 4 of the semiconductor chip 43
, 44,... And connection electrodes 42c, 42c of the substrate 42
Are sandwiched between the conductive particles 48b of the anisotropic conductive bonding material 48, the substrate 42 is electrically connected to the semiconductor chip 43, and the anisotropic conductive bonding material 4
By thermally hardening the insulating resin 48a in 8, the substrate 42 and the semiconductor device 43 are mechanically joined.
【0038】上述の如く、基板42に半導体装置43を
フリップチップ実装したのち、基板42の裏面42bに
接着剤47を用いてカバー6を取付けることで、読取セ
ンサとしての半導体装置40が完成することとなる。As described above, after the semiconductor device 43 is flip-chip mounted on the substrate 42, the cover 6 is attached to the back surface 42b of the substrate 42 using the adhesive 47, thereby completing the semiconductor device 40 as a reading sensor. Becomes
【0039】上述の如く製造された半導体装置40によ
れば、先に説明した半導体装置1と同じく、光照射に基
づく半導体チップの動作を損なうことなく、可及的なコ
ンパクト化を達成することが可能となる。According to the semiconductor device 40 manufactured as described above, as much as possible in the semiconductor device 1 described above, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip based on light irradiation. It becomes possible.
【0040】また、上記構成の半導体装置40によれ
ば、異方性導電接合材料48の絶縁性樹脂48aが基板
42と半導体装置43とを機械的に接合するので、先に
説明した半導体装置1の製造時における封止樹脂の供給
が不要となり、製造工程が簡易なものとなる。According to the semiconductor device 40 having the above structure, the insulating resin 48a of the anisotropic conductive bonding material 48 mechanically bonds the substrate 42 and the semiconductor device 43. It is not necessary to supply the sealing resin at the time of manufacturing the device, and the manufacturing process is simplified.
【0041】また、半導体装置40の製造時には、基板
42の開口42oに入り込むことのないよう異方性導電
接合材料48の供給量を調整する必要があるが、異方性
導電接合材料48の供給時には基板42の表面が解放さ
れているため、供給量の調整は極めて容易であり、さら
に異方性導電接合材料として異方性導電フィルムを採用
すれば、供給量の管理が極めて簡易なものとなる。When the semiconductor device 40 is manufactured, it is necessary to adjust the supply amount of the anisotropic conductive bonding material 48 so as not to enter the opening 42o of the substrate 42. Since the surface of the substrate 42 is sometimes released, it is extremely easy to adjust the supply amount. Further, if an anisotropic conductive film is used as the anisotropic conductive bonding material, the supply amount can be extremely easily controlled. Become.
【0042】ここで、図8に示した半導体装置40の半
導体チップ43と同様にして、上述した半導体装置10
(図5)の半導体チップ13および電子部品10A〜10
D、半導体装置20(図6)の半導体チップ23、半導体
装置30(図7)の半導体チップ33および電子部品30
A、30B、30D等、基板に対してフリップチップ実
装されている半導体チップ(電子部品)を、異方性導電接
合材料を用いてフリップチップ実装するよう構成し得る
ことは言うまでもない。Here, similarly to the semiconductor chip 43 of the semiconductor device 40 shown in FIG.
(FIG. 5) Semiconductor chip 13 and electronic components 10A to 10
D, semiconductor chip 23 of semiconductor device 20 (FIG. 6), semiconductor chip 33 of semiconductor device 30 (FIG. 7) and electronic component 30
It goes without saying that semiconductor chips (electronic components) flip-chip mounted on a substrate, such as A, 30B, and 30D, can be flip-chip mounted using an anisotropic conductive bonding material.
【0043】一方、図9〜図12も、読取センサを構成
する半導体装置に、本発明を適用した例を示しており、
本発明に関わる半導体装置100は、基板102に半導
体チップ103を実装することによって構成されてい
る。On the other hand, FIGS. 9 to 12 also show examples in which the present invention is applied to a semiconductor device constituting a reading sensor.
The semiconductor device 100 according to the present invention is configured by mounting a semiconductor chip 103 on a substrate 102.
【0044】基板102は、酸化アルミニウム等から成
るセラミック材、エポキシ等の樹脂材、あるいは液晶ポ
リマー等から成るフレキシブル材等から形成されてお
り、図11に示すように、その表面102aには配線パ
ターン(図示せず)が形成され、この配線パターンの所定
位置には、後述する半導体チップ103の各接続用電極
103c,103c…と対応する、複数の接続用電極1
02c,102c…が形成されている。The substrate 102 is formed of a ceramic material made of aluminum oxide or the like, a resin material such as epoxy, or a flexible material made of a liquid crystal polymer or the like. As shown in FIG. (Not shown) are formed, and a plurality of connection electrodes 1 corresponding to the connection electrodes 103c, 103c,.
.. Are formed.
【0045】半導体チップ103は、図12に示す如
く、ウェハの能動面103aに配線パターン103pが
形成されているとともに、CCD(charge coupled dev
ice)から成る受光部103hが形成されている。As shown in FIG. 12, the semiconductor chip 103 has a wiring pattern 103p formed on the active surface 103a of the wafer and a CCD (charge coupled device).
A light receiving portion 103h made of ice) is formed.
【0046】また、半導体チップ103における能動面
103aと反対側の実装面103bには、複数の接続用
電極103c,103c…が形成されており、これら接
続用電極103c,103c…は、ウェハ内部に形成さ
れたスルーホール103t,103t…を介して、能動
面103aの配線パターン(図示せず)と接続されてい
る。On the mounting surface 103b of the semiconductor chip 103 opposite to the active surface 103a, a plurality of connection electrodes 103c, 103c... Are formed, and these connection electrodes 103c, 103c. Are connected to a wiring pattern (not shown) on the active surface 103a through the formed through holes 103t.
【0047】さらに、図10に示すように、半導体チッ
プ103の各接続用電極103c,103c…の表面に
は、それぞれハンダやAu(金)等の導電材料から成るバ
ンプ104,104…が、メッキ法やバンピング法によ
って形成されている。Further, as shown in FIG. 10, bumps 104 made of a conductive material such as solder or Au (gold) are plated on the surfaces of the connecting electrodes 103c of the semiconductor chip 103, respectively. It is formed by a method or a bumping method.
【0048】上記半導体チップ103は、基板102の
表面102aに実装面103bを対向させた姿勢で、各
バンプ104を介して各接続用電極103cと基板10
2の各接続用電極102cとを接合することにより、上
記基板102の表面102aに対してフリップチップ実
装されている。The semiconductor chip 103 is connected to the connection electrodes 103c and the substrate 10 via the bumps 104 with the mounting surface 103b facing the surface 102a of the substrate 102.
By bonding the two connection electrodes 102c to the surface 102a of the substrate 102, flip-chip mounting is performed.
【0049】ここで、図10に示す如く、基板102の
所定位置に半導体チップ103を実装した状態におい
て、半導体チップ103における受光部103hは、上
方に向かって露呈している。Here, as shown in FIG. 10, when the semiconductor chip 103 is mounted at a predetermined position on the substrate 102, the light receiving portion 103h of the semiconductor chip 103 is exposed upward.
【0050】また、図10に示す如く、基板102と半
導体チップ103との間隙には、基板102と半導体チ
ップ103との機械的な接合強度を向上させるべく、エ
ポキシ樹脂等から成る封止樹脂105が充填されてい
る。As shown in FIG. 10, a sealing resin 105 made of epoxy resin or the like is provided in a gap between the substrate 102 and the semiconductor chip 103 in order to improve mechanical bonding strength between the substrate 102 and the semiconductor chip 103. Is filled.
【0051】因みに、上記構成の半導体装置100を製
造するには、先ず基板102を用意するとともに、半導
体チップ103の各接続用電極103cにバンプ104
を形成する。Incidentally, in order to manufacture the semiconductor device 100 having the above structure, first, a substrate 102 is prepared, and a bump 104 is formed on each connection electrode 103c of the semiconductor chip 103.
To form
【0052】次いで、基板102の所定位置に半導体チ
ップ103を搭載したのち、基板102の各接続用電極
102cと、半導体チップ103の各接続用電極103
cとを、加熱および加圧によって機械的かつ電気的に接
続することで、基板102に半導体チップ103をフリ
ップチップ実装する。Next, after mounting the semiconductor chip 103 at a predetermined position on the substrate 102, each connection electrode 102 c of the substrate 102 and each connection electrode 103 of the semiconductor chip 103 are mounted.
The semiconductor chip 103 is flip-chip mounted on the substrate 102 by mechanically and electrically connecting the semiconductor chip 103 to the substrate 102 by heating and pressing.
【0053】基板102に半導体チップ103をフリッ
プチップ実装したのち、基板102と半導体チップ10
3との間隙に封止樹脂105を充填し、加熱により封止
樹脂105を硬化させることで、読取センサとしての半
導体装置100が完成することとなる。After the semiconductor chip 103 is flip-chip mounted on the substrate 102, the substrate 102 and the semiconductor chip 10
3 is filled with the sealing resin 105 and the sealing resin 105 is cured by heating, whereby the semiconductor device 100 as a reading sensor is completed.
【0054】上述した構成の半導体装置100では、基
板102に半導体チップ103をフリップチップ実装し
ているため、基板102に対する半導体チップ103の
実装面積が抑えられることとなる。In the semiconductor device 100 having the above-described structure, the semiconductor chip 103 is flip-chip mounted on the substrate 102, so that the mounting area of the semiconductor chip 103 on the substrate 102 can be reduced.
【0055】また、基板102に半導体チップ103を
実装した状態において、半導体チップ103の受光部1
03hを上方に向けて露呈させたことで、半導体チップ
103の受光部103hに対して確実に光照射が為され
ることとなる。When the semiconductor chip 103 is mounted on the substrate 102, the light receiving section 1 of the semiconductor chip 103
By exposing 03h upward, the light receiving section 103h of the semiconductor chip 103 is reliably irradiated with light.
【0056】もって、上述した構成の半導体装置100
によれば、光照射に基づく半導体チップ103の動作を
損なうことなく、可及的なコンパクト化を達成すること
が可能となる。Thus, the semiconductor device 100 having the above-described configuration
According to this, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip 103 based on light irradiation.
【0057】なお、上述した半導体チップ103では、
配線パターン103pと接続用電極103cとをスルー
ホール103tによって接続しているが、ウェハに形成
した多層配線によって、配線パターン103pと接続用
電極103cと接続することも可能である。In the above-described semiconductor chip 103,
Although the wiring pattern 103p and the connection electrode 103c are connected by the through hole 103t, the wiring pattern 103p and the connection electrode 103c can be connected by a multilayer wiring formed on the wafer.
【0058】図13に示す半導体装置110は、異方性
導電接合材料118を用いて、基板112に半導体チッ
プ113をフリップチップ実装して構成されている。な
お、上記半導体装置110は、異方性導電接合材料11
8を用いている点以外、図9〜図12の半導体装置10
0と基本的に同一なので、半導体装置100と同一の要
素には、図10の符合に10を足した番号を付すこと
で、構成要素に関する詳細な説明を省略する。A semiconductor device 110 shown in FIG. 13 is configured by flip-chip mounting a semiconductor chip 113 on a substrate 112 using an anisotropic conductive bonding material 118. The semiconductor device 110 is made of an anisotropic conductive bonding material 11.
8 except that the semiconductor device 10 of FIGS.
Since it is basically the same as 0, the same elements as those of the semiconductor device 100 are denoted by the same reference numerals as in FIG.
【0059】因みに、上記半導体装置110を製造する
には、先ず半導体チップ113の各接続用電極113c
にバンプ114を形成する一方、基板112の表面11
2aに接続用電極112cを覆う態様で異方性導電接合
材料118を供給する。In order to manufacture the semiconductor device 110, first, each connection electrode 113c of the semiconductor chip 113 is formed.
While the bumps 114 are formed on the surface 11 of the substrate 112.
An anisotropic conductive bonding material 118 is supplied to 2a so as to cover the connection electrode 112c.
【0060】次いで、基板112の所定位置に半導体チ
ップ113を搭載し、ボンディングツール(図示せず)に
より半導体チップ113を基板112に熱圧着して、基
板112に半導体チップ113をフリップチップ実装す
るここで、半導体チップ113の各バンプ114と、基
板112の各接続用電極112cとの間に、異方性導電
接合材料118の導電粒子118bが挟み込まれること
で、基板112とが半導体チップ113と電気的に接続
され、また異方性導電接合材料118における絶縁性樹
脂118aが熱硬化することで、基板112と半導体装
置113とが機械的に接合され、読取センサとしての半
導体装置110が完成することとなる。Next, the semiconductor chip 113 is mounted at a predetermined position on the substrate 112, and the semiconductor chip 113 is thermocompression-bonded to the substrate 112 by a bonding tool (not shown), and the semiconductor chip 113 is flip-chip mounted on the substrate 112. The conductive particles 118b of the anisotropic conductive bonding material 118 are sandwiched between each bump 114 of the semiconductor chip 113 and each connection electrode 112c of the substrate 112, so that the substrate 112 is electrically connected to the semiconductor chip 113. The substrate 112 and the semiconductor device 113 are mechanically joined by thermally connecting the insulating resin 118a of the anisotropic conductive bonding material 118, thereby completing the semiconductor device 110 as a reading sensor. Becomes
【0061】上述の如く製造された半導体装置110に
よれば、先に説明した半導体装置100と同じく、光照
射に基づく半導体チップ113の動作を損なうことな
く、可及的なコンパクト化を達成することが可能とな
る。According to the semiconductor device 110 manufactured as described above, as much as possible in the semiconductor device 100 described above, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip 113 based on light irradiation. Becomes possible.
【0062】また、上記構成の半導体装置110によれ
ば、異方性導電接合材料118の絶縁性樹脂118aが
基板112と半導体装置113とを機械的に接合するの
で、先に説明した半導体装置100の製造時における封
止樹脂の供給が不要となり、もって製造工程が簡易なも
のとなる。According to the semiconductor device 110 having the above structure, the insulating resin 118a of the anisotropic conductive bonding material 118 mechanically bonds the substrate 112 and the semiconductor device 113. It is not necessary to supply the sealing resin at the time of manufacturing, and the manufacturing process is simplified.
【0063】ここで、図9〜図12に示した半導体装置
100、および図13に示した半導体装置110は、受
光部を有する特定の半導体チップを、基板上に1個のみ
実装しているが、本発明に関わる半導体装置は、基板上
に特定の半導体チップとともに他の電子部品を実装した
構成をも含むことは言うまでもない。Here, in the semiconductor device 100 shown in FIGS. 9 to 12 and the semiconductor device 110 shown in FIG. 13, only one specific semiconductor chip having a light receiving portion is mounted on the substrate. Needless to say, the semiconductor device according to the present invention also includes a configuration in which other electronic components are mounted together with a specific semiconductor chip on a substrate.
【0064】なお、上述した各実施例では、本発明を基
板にCCDチップを実装して成る読取センサ(半導体装
置)に適用した例を示したが、例えばCMOS(compleme
ntarymetal oxide semiconductor)チップ等、受光部を
有する種々の半導体チップを基板に実装して成る読取セ
ンサにおいても、本発明を有効に適用し得ることは勿論
である。In each of the above embodiments, an example is shown in which the present invention is applied to a reading sensor (semiconductor device) having a CCD chip mounted on a substrate.
Of course, the present invention can also be effectively applied to a read sensor in which various semiconductor chips having a light receiving section such as an ntary metal oxide semiconductor chip are mounted on a substrate.
【0065】また、読取センサに限らず、例えばUVE
PROM(ultra violet erasableand programmable RO
M)チップ等、受光部に対する光の照射に基づいて動作
する各種の半導体チップを、基板に実装して成る様々な
半導体装置に対しても、本発明を極めて有効に適用し得
ることは言うまでもない。In addition to the reading sensor, for example, UVE
PROM (ultra violet erasable and programmable RO
M) Needless to say, the present invention can be very effectively applied to various semiconductor devices in which various semiconductor chips such as chips that operate based on light irradiation on a light receiving unit are mounted on a substrate. .
【0066】[0066]
【発明の効果】以上、詳述した如く、本発明に関わる半
導体装置は、能動面に受光部とともに接続用電極を設け
た半導体チップと、該半導体チップの実装域に開口を形
成した基板とを具備し、半導体チップの能動面を基板の
表面に対向させ、かつ半導体チップの受光部を基板の開
口に臨ませる態様で、半導体チップを基板の表面にフリ
ップチップ実装している。上記構成によれば、基板に半
導体チップをフリップチップ実装したことで、基板に対
する半導体チップの実装面積を抑えられるとともに、半
導体チップの受光部を基板の開口に臨ませことで、受光
部に対して確実に光照射が為されることとなる。もって
本発明に関わる半導体装置によれば、光照射に基づく半
導体チップの動作を損なうことなく、可及的なコンパク
ト化を達成することが可能となる。As described in detail above, the semiconductor device according to the present invention comprises a semiconductor chip provided with a connection electrode together with a light receiving portion on an active surface, and a substrate having an opening formed in a mounting area of the semiconductor chip. The semiconductor chip is flip-chip mounted on the surface of the substrate such that the active surface of the semiconductor chip faces the surface of the substrate and the light receiving portion of the semiconductor chip faces the opening of the substrate. According to the above configuration, the semiconductor chip is flip-chip mounted on the substrate, so that the mounting area of the semiconductor chip with respect to the substrate can be reduced. Light irradiation is surely performed. Thus, according to the semiconductor device of the present invention, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip based on light irradiation.
【0067】また、本発明に関わる半導体装置は、能動
面に受光部を設けるとともに能動面と反対側の実装面に
接続用電極を設けた半導体チップを具備し、該半導体チ
ップの実装面を基板の表面に対向させて受光部を露呈さ
せる態様で、半導体チップを基板の表面にフリップチッ
プ実装している。上記構成によれば、基板に半導体チッ
プをフリップチップ実装したことで、基板に対する半導
体チップの実装面積を抑えられるとともに、半導体チッ
プの実装面に接続用電極を設けて受光部を露呈させたこ
とで、受光部に対して確実に光照射が為されることとな
る。もって本発明に関わる半導体装置によれば、光照射
に基づく半導体チップの動作を損なうことなく、可及的
なコンパクト化を達成することが可能となる。A semiconductor device according to the present invention includes a semiconductor chip having a light receiving portion on an active surface and a connection electrode provided on a mounting surface opposite to the active surface, wherein the mounting surface of the semiconductor chip is mounted on a substrate. The semiconductor chip is flip-chip mounted on the surface of the substrate in such a manner that the light receiving portion is exposed to face the surface of the substrate. According to the above configuration, by mounting the semiconductor chip on the substrate by flip-chip, the mounting area of the semiconductor chip with respect to the substrate can be reduced, and the light receiving portion is exposed by providing the connection electrode on the mounting surface of the semiconductor chip. Thus, light irradiation is reliably performed on the light receiving unit. Thus, according to the semiconductor device of the present invention, it is possible to achieve as small a size as possible without impairing the operation of the semiconductor chip based on light irradiation.
【図1】(a)および(b)は、本発明に関わる半導体装置
を示す平面図および要部破断底面図。FIGS. 1A and 1B are a plan view and a fragmentary bottom view showing a semiconductor device according to the present invention.
【図2】本発明に関わる半導体装置を示す図1(a)中の
II−II線断面側面図。FIG. 2 shows a semiconductor device according to the present invention in FIG.
II-II sectional side view.
【図3】本発明に関わる半導体装置の基板を示す平面
図。FIG. 3 is a plan view showing a substrate of a semiconductor device according to the present invention.
【図4】(a)および(b)は、本発明に関わる半導体装置
の半導体チップを示す側面図および底面図。FIGS. 4A and 4B are a side view and a bottom view showing a semiconductor chip of a semiconductor device according to the present invention.
【図5】(a)および(b)は、本発明に関わる半導体装置
の他の実施例を示す平面図および断面側面図。FIGS. 5A and 5B are a plan view and a sectional side view showing another embodiment of the semiconductor device according to the present invention.
【図6】(a)および(b)は、本発明に関わる半導体装置
の他の実施例を示す平面図および断面側面図。FIGS. 6A and 6B are a plan view and a cross-sectional side view showing another embodiment of a semiconductor device according to the present invention.
【図7】(a)および(b)は、本発明に関わる半導体装置
の他の実施例を示す平面図および断面側面図。FIGS. 7A and 7B are a plan view and a cross-sectional side view showing another embodiment of a semiconductor device according to the present invention.
【図8】本発明に関わる半導体装置の他の実施例を示す
び断面側面図。FIG. 8 is a sectional side view showing another embodiment of the semiconductor device according to the present invention.
【図9】本発明に関わる半導体装置を示す平面図。FIG. 9 is a plan view showing a semiconductor device according to the present invention.
【図10】本発明に関わる半導体装置を示す図9中の X
−X 線断面側面図。FIG. 10 shows a semiconductor device according to the present invention.
-X-ray sectional side view.
【図11】図9の半導体装置における基板を示す平面
図。FIG. 11 is a plan view showing a substrate in the semiconductor device of FIG. 9;
【図12】(a)、(b)および(c)は、図9の半導体装置
における半導体チップを示す平面図、断面側面図および
底面図。12A, 12B, and 12C are a plan view, a cross-sectional side view, and a bottom view illustrating a semiconductor chip in the semiconductor device in FIG. 9;
【図13】本発明に関わる半導体装置の他の実施例を示
す断面側面図。FIG. 13 is a sectional side view showing another embodiment of the semiconductor device according to the present invention.
【図14】(a)および(b)は、従来の半導体装置を示す
平面図および断面側面図。14A and 14B are a plan view and a cross-sectional side view showing a conventional semiconductor device.
1…半導体装置、 2…基板、 2a…表面、 2c…接続用電極、 2o…開口、 3…半導体チップ、 3h…受光部、 3c…接続用電極、 10,20,30,40…半導体装置、 100…半導体装置、 102…基板、 102…表面、 102c…接続用電極、 103…半導体チップ、 103h…受光部、 103c…接続用電極、 110…半導体装置。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Substrate, 2a ... Surface, 2c ... Connection electrode, 2o ... Opening, 3 ... Semiconductor chip, 3h ... Light receiving part, 3c ... Connection electrode, 10, 20, 30, 40 ... Semiconductor device, 100: semiconductor device, 102: substrate, 102: surface, 102c: connection electrode, 103: semiconductor chip, 103h: light receiving portion, 103c: connection electrode, 110: semiconductor device.
Claims (3)
を、基板の表面に実装して成る半導体装置であって、 能動面に前記受光部とともに接続用電極を設けた半導体
チップと、該半導体チップの実装域に開口を形成した基
板とを具備し、前記半導体チップの前記能動面を前記基
板の表面に対向させ、かつ前記半導体チップの前記受光
部を前記基板の開口に臨ませる態様で、前記半導体チッ
プを前記基板の表面にフリップチップ実装して成ること
を特徴とする半導体装置。1. A semiconductor device comprising: a semiconductor chip having a light receiving portion on an active surface mounted on a surface of a substrate; and a semiconductor chip having an active surface provided with connection electrodes together with the light receiving portion; A substrate having an opening formed in a chip mounting area, wherein the active surface of the semiconductor chip faces the surface of the substrate, and the light receiving portion of the semiconductor chip faces the opening of the substrate, A semiconductor device, wherein the semiconductor chip is flip-chip mounted on a surface of the substrate.
前記開口を覆う透光性のカバーを設けて成ることを特徴
とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a light-transmitting cover for covering the opening formed in the substrate is provided on the back surface of the substrate.
を、基板の表面に実装して成る半導体装置であって、 前記能動面と反対側の実装面に接続用電極を設けた半導
体チップを具備し、前記半導体チップの前記実装面を前
記基板の表面に対向させ、前記半導体チップの前記受光
部を露呈させた態様で、前記半導体チップを前記基板の
表面にフリップチップ実装して成ることを特徴とする半
導体装置。3. A semiconductor device comprising: a semiconductor chip having a light receiving portion on an active surface mounted on a surface of a substrate; and a semiconductor chip provided with connection electrodes on a mounting surface opposite to the active surface. The semiconductor chip is flip-chip mounted on the surface of the substrate in a mode in which the mounting surface of the semiconductor chip is opposed to the surface of the substrate and the light receiving portion of the semiconductor chip is exposed. Characteristic semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35605999A JP2001177081A (en) | 1999-12-15 | 1999-12-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35605999A JP2001177081A (en) | 1999-12-15 | 1999-12-15 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001177081A true JP2001177081A (en) | 2001-06-29 |
JP2001177081A5 JP2001177081A5 (en) | 2007-02-01 |
Family
ID=18447120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35605999A Pending JP2001177081A (en) | 1999-12-15 | 1999-12-15 | Semiconductor device |
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JP (1) | JP2001177081A (en) |
Cited By (6)
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US6787812B2 (en) * | 2001-02-24 | 2004-09-07 | Zarlink Semiconductor Ab | Active optical device |
JP2005501414A (en) * | 2001-08-24 | 2005-01-13 | カール−ツアイス−シュティフツンク | Method and printed circuit package for forming contacts |
JP2007142058A (en) * | 2005-11-17 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Semiconductor imaging element and manufacturing method thereof, and semiconductor imaging apparatus and manufacturing method thereof |
JP2009105459A (en) * | 2009-02-12 | 2009-05-14 | Seiko Epson Corp | Optical device, optical module, and electronic apparatus |
WO2013146098A1 (en) * | 2012-03-26 | 2013-10-03 | シャープ株式会社 | Image pickup module and method for manufacturing image pickup module |
US11476226B2 (en) | 2018-12-28 | 2022-10-18 | Murata Manufacturing Co., Ltd. | Radio-frequency module and communication device |
-
1999
- 1999-12-15 JP JP35605999A patent/JP2001177081A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6787812B2 (en) * | 2001-02-24 | 2004-09-07 | Zarlink Semiconductor Ab | Active optical device |
JP2005501414A (en) * | 2001-08-24 | 2005-01-13 | カール−ツアイス−シュティフツンク | Method and printed circuit package for forming contacts |
US7700957B2 (en) | 2001-08-24 | 2010-04-20 | Schott Ag | Process for making contact with and housing integrated circuits |
US7821106B2 (en) | 2001-08-24 | 2010-10-26 | Schott Ag | Process for making contact with and housing integrated circuits |
US7880179B2 (en) | 2001-08-24 | 2011-02-01 | Wafer-Level Packaging Portfolio Llc | Process for making contact with and housing integrated circuits |
US8349707B2 (en) | 2001-08-24 | 2013-01-08 | Wafer-Level Packaging Portfolio Llc | Process for making contact with and housing integrated circuits |
JP2007142058A (en) * | 2005-11-17 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Semiconductor imaging element and manufacturing method thereof, and semiconductor imaging apparatus and manufacturing method thereof |
JP2009105459A (en) * | 2009-02-12 | 2009-05-14 | Seiko Epson Corp | Optical device, optical module, and electronic apparatus |
WO2013146098A1 (en) * | 2012-03-26 | 2013-10-03 | シャープ株式会社 | Image pickup module and method for manufacturing image pickup module |
JP2013201389A (en) * | 2012-03-26 | 2013-10-03 | Sharp Corp | Imaging module, and manufacturing method of imaging module |
US9761630B2 (en) | 2012-03-26 | 2017-09-12 | Sharp Kabushiki Kaisha | Method for manufacturing image pickup module |
US11476226B2 (en) | 2018-12-28 | 2022-10-18 | Murata Manufacturing Co., Ltd. | Radio-frequency module and communication device |
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