JP2001176916A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JP2001176916A
JP2001176916A JP35924199A JP35924199A JP2001176916A JP 2001176916 A JP2001176916 A JP 2001176916A JP 35924199 A JP35924199 A JP 35924199A JP 35924199 A JP35924199 A JP 35924199A JP 2001176916 A JP2001176916 A JP 2001176916A
Authority
JP
Japan
Prior art keywords
bonding
electrode
wire
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35924199A
Other languages
Japanese (ja)
Inventor
Hiroshi Arai
浩 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP35924199A priority Critical patent/JP2001176916A/en
Publication of JP2001176916A publication Critical patent/JP2001176916A/en
Pending legal-status Critical Current

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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

PROBLEM TO BE SOLVED: To stabilize bonding performance in wire bonding and to control the press contact size of a wire joining part to be small. SOLUTION: A semiconductor device is provided with a camera which picks up the images of the pad 1b of a semiconductor chip and a projection electrode 19; a control part which recognizes the outer shape of the pad 1b and the projection electrode 19 from the images, calculates the center position 19b of the projection electrode 19 based on the detection result, and automatically corrects a bonding coordinate which is previously set when the projection electrode 19 and the wire 3 on the pad 1b of the semiconductor chip are electrically connected; and a capillary pressing the wire 3 to the almost center part 19a of the projection electrode 19 based on correction and joining the projection electrode 19 and the wire 3. The center position 19b of the projection electrode 19 is recognized and the center part 19a is secondarily bonded. Then, the wire can be bonded to the projection electrode 19 by highly precisely executing positioning.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、ＫＧＤ（Known Good Die）として取得した
半導体チップに対するワイヤボンディング時のボンディ
ング性の安定化に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique which is effective when applied to stabilize bonding properties of a semiconductor chip obtained as a KGD (Known Good Die) during wire bonding.

【０００２】[0002]

【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

【０００３】半導体集積回路が形成された半導体チップ
に対するワイヤボンディングは、ウェハ製造工程でアル
ミニウムなどの導電材によってメタライズされたパッド
（表面電極）に対して、ワイヤを直接ボンディングして
結線している。In wire bonding to a semiconductor chip on which a semiconductor integrated circuit is formed, a wire is directly bonded to a pad (surface electrode) metallized with a conductive material such as aluminum in a wafer manufacturing process.

【０００４】最近の半導体チップのパッケージングは、
高集積化によるパッドの小面積化や狭ピッチ化が進んで
おり、これに伴い、ワイヤボンディングでのワイヤ接合
部の圧着サイズの小形化が要求されている。[0004] Recent semiconductor chip packaging includes:
The pad area and pitch are becoming smaller due to the higher integration, and accordingly, there is a demand for a smaller crimping size of the wire bonding part by wire bonding.

【０００５】なお、高実装密度化によって複数の半導体
チップを単体でパッケージングする半導体装置（マルチ
チップパッケージともいう）が開発されている。[0005] A semiconductor device (also referred to as a multi-chip package) has been developed in which a plurality of semiconductor chips are individually packaged due to a higher packaging density.

【０００６】複数の半導体チップを単体でパッケージン
グする際、パッケージ単位での歩留り向上のため、チッ
プ状態でエージングから選別まで実施して良品チップを
取得するＫＧＤプロセスを行う場合がある。When a plurality of semiconductor chips are packaged alone, a KGD process for obtaining good chips by performing aging to sorting in chip state may be performed in order to improve the yield in package units.

【０００７】この場合、ＫＧＤ取得として行ったワイヤ
ボンディング（これを以降、１次ボンディングともい
う）のワイヤにおけるワイヤ接合部が、半導体チップの
パッド上に突起電極として残留してしまうため、この突
起電極上にパッケージ組み立てでのワイヤボンディング
（これを以降、２次ボンディングともいう）を行うこと
になる。In this case, the wire bonding portion of the wire of the wire bonding (hereinafter also referred to as primary bonding) performed as the KGD acquisition remains as a protruding electrode on the pad of the semiconductor chip. Wire bonding (hereinafter, also referred to as secondary bonding) in package assembly is performed on the upper side.

【０００８】ここで、ワイヤボンディング技術について
は、例えば、日経ＢＰ社、１９９３年５月３１日発行、
「実践講座ＶＬＳＩパッケージング技術（下）」香山
晋、成瀬邦彦（監修）、２２頁〜３０頁に記載されてい
る。Here, regarding the wire bonding technology, for example, Nikkei BP, published on May 31, 1993,
"Practical Course VLSI Packaging Technology (2)" is described in Susumu Kayama and Kunihiko Naruse (supervised), pp. 22-30.

【０００９】[0009]

【発明が解決しようとする課題】ところが、前記した技
術のワイヤボンディングにおいては、半導体チップのパ
ッドの中心の座標を予め入力しておき、ワイヤボンディ
ング時に、この入力値と実際に検出したパッドの中心座
標との差をワイヤボンディング装置で補正してパッドの
中心に対してワイヤボンディングを行っている。However, in the wire bonding of the above-mentioned technique, the coordinates of the center of the pad of the semiconductor chip are input in advance, and the input value and the center of the pad actually detected during the wire bonding are input. The difference from the coordinates is corrected by a wire bonding device to perform wire bonding to the center of the pad.

【００１０】したがって、パッドの中心に対するボンデ
ィング位置として大きなずれは生じないものの、ワイヤ
ボンディング装置の機械的精度により、パッド上におい
て僅かにワイヤの圧着座標にずれが発生することがあ
る。[0010] Therefore, although a large displacement does not occur as the bonding position with respect to the center of the pad, a slight displacement may occur in the pressure bonding coordinates of the wire on the pad due to the mechanical accuracy of the wire bonding apparatus.

【００１１】そこで、ＫＧＤとして取得した半導体チッ
プのように、パッド上に突起電極が残留した半導体チッ
プに２次ボンディングを行う場合、１次ボンディングに
おいてパッド上で任意のある一方向に圧着座標がずれ、
さらに２次ボンディングでこれと逆方向に同様にずれた
場合、１次と２次とでのワイヤ接合部相互のずれが２倍
になる。Therefore, when secondary bonding is performed on a semiconductor chip having a protruding electrode remaining on a pad, such as a semiconductor chip obtained as a KGD, the pressure bonding coordinates are shifted in an arbitrary direction on the pad in the primary bonding. ,
Further, when the secondary bonding is similarly displaced in the opposite direction, the mutual displacement between the primary and secondary wire bonding portions is doubled.

【００１２】すなわち、１次、２次両方のボンディング
ともパッドの中心に対してワイヤボンディングを行うた
め、１次と２次とで反対の方向に圧着位置がずれると、
パッド上の１次の突起電極と２次のワイヤ接合部との間
のずれが２倍になる。That is, since wire bonding is performed to the center of the pad in both the primary and secondary bonding, if the crimping position is shifted in the opposite direction between the primary and the secondary,
The displacement between the primary bump electrode on the pad and the secondary wire joint is doubled.

【００１３】その際、突起電極のない平坦なパッドにワ
イヤボンディングする場合と異なり、２次ボンディング
では、凹凸のある不定形な突起電極上にワイヤボンディ
ングを行うため、圧着位置（座標）のずれが２倍になる
と、圧着面積不十分による圧着不良や、突起電極が片側
に大きく変形して隣接パッド間ショートが発生するなど
の問題が起こる。At this time, unlike wire bonding to a flat pad having no protruding electrode, in secondary bonding, wire bonding is performed on an irregular protruding electrode having irregularities, so that the displacement of the press-bonding position (coordinate) is shifted. If the size is doubled, problems such as insufficient pressure bonding due to insufficient pressure bonding area and short-circuit between adjacent pads due to large deformation of the protruding electrode to one side occur.

【００１４】なお、この問題は、狭パッドピッチによ
り、ボンディングの圧着サイズを小さくする必要がある
パッケージ、あるいは、センタパッド配列の半導体チッ
プを搭載して逆ボンド（第１ボンドをリード側とし、第
２ボンドをチップ側とするボンディング方法）を行い、
かつ２次ボンディングを行う必要があるパッケージなど
で特に顕著となる。[0014] This problem is caused by the need to reduce the bonding pressure size due to the narrow pad pitch, or mounting a semiconductor chip having a center pad array and mounting a reverse bond (where the first bond is the lead side and the Bonding method with two bonds on the chip side)
In addition, this is particularly noticeable in a package or the like that needs to perform secondary bonding.

【００１５】本発明の目的は、ワイヤボンディングにお
けるボンディング性を安定化させるとともに、ワイヤ接
合部の圧着サイズを小さく制御することが可能な半導体
装置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device capable of stabilizing the bonding property in wire bonding and controlling the compression size of a wire bonding portion to be small.

【００１６】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１７】[0017]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１８】すなわち、本発明の半導体装置の製造方法
は、表面電極に突起電極が形成された半導体チップを準
備する工程と、前記半導体チップをチップ支持基板に搭
載する工程と、前記半導体チップの前記表面電極に形成
された前記突起電極の位置を検出する工程と、前記検出
結果に基づいてボンディングツールにより前記突起電極
の中心部にボンディング用のワイヤを押し当てて前記突
起電極と前記ワイヤとを接合して、前記突起電極と前記
チップ支持基板のボンディング電極とをワイヤボンディ
ングによって接合する工程と、前記チップ支持基板に複
数の外部端子を設ける工程とを有するものである。That is, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a semiconductor chip having projecting electrodes formed on a surface electrode; a step of mounting the semiconductor chip on a chip supporting substrate; Detecting the position of the protruding electrode formed on the surface electrode, and bonding the protruding electrode and the wire by pressing a bonding wire against the center of the protruding electrode using a bonding tool based on the detection result. And a step of bonding the protruding electrode and the bonding electrode of the chip support substrate by wire bonding, and a step of providing a plurality of external terminals on the chip support substrate.

【００１９】また、本発明の半導体装置の製造方法は、
信頼性検査によって良品として選別され、表面電極にワ
イヤボンディングによって形成された突起電極が設けら
れた半導体チップを準備する工程と、前記半導体チップ
をチップ支持基板に搭載する工程と、前記半導体チップ
の前記表面電極に形成された前記突起電極の中心位置を
検出する工程と、前記検出結果に基づいてボンディング
ツールにより前記突起電極の中心部にボンディング用の
ワイヤを押し当てて前記突起電極と前記ワイヤとを接合
して、前記突起電極と前記チップ支持基板のボンディン
グ電極とをワイヤボンディングによって接合する工程
と、前記チップ支持基板に複数の外部端子を設ける工程
とを有するものである。Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a semiconductor chip which is selected as a non-defective product by a reliability test and has a surface electrode provided with a bump electrode formed by wire bonding, a step of mounting the semiconductor chip on a chip support substrate, and a step of mounting the semiconductor chip on a chip support substrate. Detecting a center position of the protruding electrode formed on the surface electrode, and pressing a bonding wire against a center portion of the protruding electrode by a bonding tool based on the detection result, thereby bonding the protruding electrode and the wire. And bonding the projecting electrode and the bonding electrode of the chip supporting substrate by wire bonding, and providing a plurality of external terminals on the chip supporting substrate.

【００２０】これにより、半導体チップの表面電極内に
おける突起電極の圧着位置に無関係に突起電極の中心に
対して２次ボンディングを行うことができ、したがっ
て、１次ボンディングによる突起電極上に精度良く２次
ボンディングを行うことができる。Thus, the secondary bonding can be performed to the center of the protruding electrode regardless of the compression position of the protruding electrode within the surface electrode of the semiconductor chip. Next bonding can be performed.

【００２１】その結果、２次ボンディングにおいても安
定したボンディング性を得ることが可能になり、これに
より、２次ボンディングでの圧着不良を低減できるとと
もに、隣接パッド間ショートの発生を防止することがで
きる。As a result, it is possible to obtain a stable bonding property even in the secondary bonding, whereby it is possible to reduce the bonding failure in the secondary bonding and to prevent the occurrence of a short circuit between adjacent pads. .

【００２２】したがって、２次ボンディングにおける歩
留り向上を図ることが可能になるとともに、半導体装置
の原価低減を図ることができる。Therefore, the yield in the secondary bonding can be improved, and the cost of the semiconductor device can be reduced.

【００２３】[0023]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一の機能を有する部材には同
一の符号を付し、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【００２４】図１は本発明の実施の形態の半導体装置の
製造方法によって組み立てられるＢＧＡ形のマルチチッ
プパッケージの構造の一例を示す平面図、図２は図１に
示すマルチチップパッケージの構造を示す図であり、
（ａ) は正面図、（ｂ）は側面図、（ｃ）は底面図、図
３は図１に示すマルチチップパッケージにおける半導体
チップの実装状態の一例を封止部を透過して示す概略平
面図、図４は図１に示すマルチチップパッケージのＡ−
Ａ線に沿う断面の構造を示す断面図、図５は本発明の実
施の形態の半導体装置の製造方法で用いられるワイヤボ
ンディング装置の基本構造の一例を示す構成図、図６は
図１に示すマルチチップパッケージの製造手順の一例を
示すプロセスフロー図、図７は本発明の実施の形態の半
導体装置の製造方法のワイヤボンディング工程における
突起電極の位置の検出状態の一例を示す平面図、図８は
本発明による実施の形態の半導体装置の製造方法のワイ
ヤボンディング工程における２次ボンディング時の状態
の一例を示す部分断面図、図９は本発明による実施の形
態の半導体装置の製造方法のワイヤボンディング工程に
おける２次ボンディング終了後のワイヤ接合部の構造の
一例を示す部分断面図、図１０は本発明による実施の形
態の半導体装置の製造方法のワイヤボンディング終了後
のワイヤ接合状態の一例を示す部分平面図、図１１は図
１０に示すワイヤ接合状態に対する比較例のワイヤ接合
状態を示す部分平面図である。FIG. 1 is a plan view showing an example of the structure of a BGA type multi-chip package assembled by the method of manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 2 shows the structure of the multi-chip package shown in FIG. FIG.
(A) is a front view, (b) is a side view, (c) is a bottom view, and FIG. 3 is a schematic plan view showing an example of a mounting state of a semiconductor chip in the multi-chip package shown in FIG. FIGS. 4A and 4B show the multi-chip package shown in FIG.
FIG. 5 is a cross-sectional view showing a cross-sectional structure along the line A, FIG. 5 is a configuration diagram showing an example of a basic structure of a wire bonding apparatus used in the method of manufacturing a semiconductor device according to the embodiment of the present invention, and FIG. FIG. 7 is a process flow diagram showing an example of a manufacturing procedure of a multi-chip package. FIG. 7 is a plan view showing an example of a detection state of a position of a protruding electrode in a wire bonding step of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a partial cross-sectional view showing an example of a state at the time of secondary bonding in a wire bonding step of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. FIG. 10 is a partial cross-sectional view showing an example of the structure of the wire bonding portion after the completion of the secondary bonding in the process. FIG. 10 shows a semiconductor device according to an embodiment of the present invention. Wire bonding after the end of the wire portion plane showing an example of a bonding state of the manufacturing method, and FIG. 11 is a partial plan view showing a wire bonding state of the comparison example with respect to wire bonding state shown in FIG. 10.

【００２５】本実施の形態の半導体装置は、表面実装形
で、かつＢＧＡ（Ball Grid Array)タイプの半導体パッ
ケージであり、例えば、マルチチップパッケージ１１と
呼ばれ、その概略構成は、記憶回路が形成された４個の
半導体チップ１と、この４個の半導体チップ１を支持す
るチップ支持基板であるＢＧＡ基板２と、このＢＧＡ基
板２のボンディング電極２ａと半導体チップ１の表面電
極であるパッド１ｂとを接続するボンディング用のワイ
ヤ３と、ＢＧＡ基板２のチップ支持面２ｂと反対側の面
である裏面２ｃに設けられるはんだボール（外部端子）
４と、ＢＧＡ基板２に実装された半導体チップ１および
ワイヤ３をモールドによって樹脂封止して形成した封止
部５とからなり、図１に示すように封止部５の表面の角
部にパッケージの向きを示すためのマーク１８が付され
ている。The semiconductor device of the present embodiment is a surface-mount type and a BGA (Ball Grid Array) type semiconductor package, for example, called a multi-chip package 11. Four semiconductor chips 1, a BGA substrate 2 as a chip support substrate for supporting the four semiconductor chips 1, bonding electrodes 2 a of the BGA substrate 2 and pads 1 b as surface electrodes of the semiconductor chip 1. And a solder ball (external terminal) provided on the back surface 2c opposite to the chip support surface 2b of the BGA substrate 2 for bonding.
4 and a sealing portion 5 formed by resin-sealing the semiconductor chip 1 and the wires 3 mounted on the BGA substrate 2 by molding. As shown in FIG. A mark 18 for indicating the direction of the package is provided.

【００２６】なお、このマルチチップパッケージ１１に
搭載された４個の半導体チップ１は、その平面形状が長
方形に形成され、かつ、それぞれ、例えば、ＳＤＲＡＭ
（Synchronous Dynamic Random Access Memory）の記憶
回路が形成されるとともに、この記憶回路に電気的に接
続された複数のパッド１ｂが、図３に示すように、長方
形の主面１ａの幅方向の中心付近に並んで設けられたセ
ンタパッド配列のものである。The four semiconductor chips 1 mounted on the multi-chip package 11 are formed in a rectangular shape in plan view, and each of them is, for example, an SDRAM.
(Synchronous Dynamic Random Access Memory) is formed, and a plurality of pads 1b electrically connected to the storage circuit are arranged near the center in the width direction of the rectangular main surface 1a as shown in FIG. Are arranged in a center pad arrangement.

【００２７】さらに、マルチチップパッケージ１１で
は、限られた外観サイズの中に複数（本実施の形態では
４個）の半導体チップ１を組み込むため、狭パッドピッ
チ化が図られた半導体チップ１を用いなければならな
い。Further, in the multi-chip package 11, since a plurality of (four in the present embodiment) semiconductor chips 1 are incorporated in a limited external size, the semiconductor chips 1 with a narrow pad pitch are used. There must be.

【００２８】この際、パッド１ｂの設置ピッチは、例え
ば、８５μｍであり、かつ図１０に示すパッド用開口部
１ｄの大きさは、例えば、７５μｍ×７５μｍであり、
従来の設置ピッチおよびパッド用開口部よりも小さくな
っている。At this time, the installation pitch of the pads 1b is, for example, 85 μm, and the size of the pad opening 1d shown in FIG. 10 is, for example, 75 μm × 75 μm.
It is smaller than the conventional installation pitch and pad opening.

【００２９】なお、本実施の形態のマルチチップパッケ
ージ１１に搭載されている半導体チップ１は、ＫＧＤと
呼ばれ、予め良品選別されたものであり、半導体チップ
１単体の状態でエージング検査などの信頼性検査（スク
リーニングテストともいう）を行い、良品として取得し
たものである。The semiconductor chip 1 mounted on the multi-chip package 11 according to the present embodiment is called a KGD and has been selected in advance as a non-defective product. It was obtained as a non-defective product after a sex test (also called a screening test).

【００３０】したがって、半導体チップ１のパッド１ｂ
には、信頼性検査用として接続したワイヤ３の残留部分
である突起電極１９が形成されている。Therefore, the pad 1b of the semiconductor chip 1
Is formed with a protruding electrode 19 which is a remaining portion of the wire 3 connected for reliability inspection.

【００３１】つまり、この突起電極１９は、半導体チッ
プ１のパッド１ｂと信頼性検査用基板の基板端子とをワ
イヤボンディングによって接続して（これを１次ボンデ
ィングという）信頼性検査を行い、検査後、パッド１ｂ
上にワイヤ接合部３ａのみを残してワイヤ３を切断した
ことによって形成されたものである。That is, the bump electrodes 19 are connected to the pads 1b of the semiconductor chip 1 and the substrate terminals of the reliability test board by wire bonding (this is called primary bonding), and a reliability test is performed. , Pad 1b
The wire 3 is formed by cutting the wire 3 while leaving only the wire joint 3a.

【００３２】したがって、本実施の形態のマルチチップ
パッケージ１１は、各パッド１ｂ上に予め突起電極１９
が形成された半導体チップ１を準備し、この半導体チッ
プ１を用いて組み立てが行われるものであり、前記組み
立て工程で半導体チップ１のパッド１ｂとＢＧＡ基板２
のボンディング電極２ａとをワイヤボンディング（これ
を２次ボンディングという）によって接続する際には、
ネイルヘッドボンディング（ボールボンディングともい
う）によって半導体チップ１のパッド１ｂ上の突起電極
１９に対してワイヤボンディングである２次ボンディン
グを行う。Therefore, the multi-chip package 11 of the present embodiment has a structure in which the bump electrodes 19 are provided on the pads 1b in advance.
The semiconductor chip 1 on which the semiconductor chip 1 is formed is prepared, and assembly is performed using the semiconductor chip 1. In the assembly step, the pad 1b of the semiconductor chip 1 and the BGA substrate 2
When the bonding electrode 2a is connected by wire bonding (this is called secondary bonding),
Secondary bonding, which is wire bonding, is performed on the bump electrodes 19 on the pads 1b of the semiconductor chip 1 by nail head bonding (also referred to as ball bonding).

【００３３】その際、マルチチップパッケージ１１に搭
載される半導体チップ１は狭パッドピッチ化が図られた
ものであり、１次ボンディングによって残留させる突起
電極１９の大きさを、例えば、最大・直径６０μｍ程度
に抑えなければならず、したがって、その上から接合す
る２次ボンディングの圧着精度についても数μｍ誤差程
度の高精度のワイヤボンディング技術が要求される。At this time, the semiconductor chip 1 mounted on the multi-chip package 11 has a narrow pad pitch, and the size of the protruding electrode 19 left by the primary bonding is set to, for example, a maximum diameter of 60 μm. Therefore, a high-precision wire bonding technique with an error of about several μm is required for the pressure bonding accuracy of the secondary bonding to be joined from above.

【００３４】そこで、本実施の形態のマルチチップパッ
ケージ１１の組み立てで行われるワイヤボンディング
（２次ボンディング）は、図５に示すワイヤボンディン
グ装置を用いて行うものであるが、本実施の形態の前記
ワイヤボンディング装置では、前記２次ボンディング時
に、図７に示すパッド１ｂ上の突起電極１９の中心位置
１９ｂを検出し、この検出結果に基づいて、図８に示す
ように、突起電極１９のほぼ中心部１９ａにワイヤ３を
押し当ててワイヤボンディングするものであり、これに
より、半導体チップ１のパッド１ｂ上の突起電極１９と
２次ボンディングによるワイヤ接合部３ａとの接合位置
精度（圧着位置精度）を±数μｍ程度の高精度の誤差と
するものである。Therefore, the wire bonding (secondary bonding) performed in assembling the multi-chip package 11 according to the present embodiment is performed using the wire bonding apparatus shown in FIG. In the wire bonding apparatus, at the time of the secondary bonding, the center position 19b of the bump electrode 19 on the pad 1b shown in FIG. 7 is detected, and based on this detection result, as shown in FIG. The wire bonding is performed by pressing the wire 3 against the portion 19a, whereby the bonding position accuracy (crimping position accuracy) between the projecting electrode 19 on the pad 1b of the semiconductor chip 1 and the wire bonding portion 3a by the secondary bonding is improved. An error of high accuracy of about ± several μm is set.

【００３５】すなわち、図５に示すワイヤボンディング
装置は、ワイヤボンディング時に、まず、ＫＧＤ取得に
よって残留した突起電極１９の位置を認識し、この突起
電極１９のほぼ中心部１９ａを狙って２次ボンディング
を行うものである（以降、このワイヤボンディング方式
をバンプ認識方式という）。That is, the wire bonding apparatus shown in FIG. 5 first recognizes the position of the protruding electrode 19 left by the KGD acquisition at the time of wire bonding, and performs the secondary bonding aiming at a substantially central portion 19 a of the protruding electrode 19. (Hereinafter, this wire bonding method is referred to as a bump recognition method).

【００３６】また、本実施の形態のマルチチップパッケ
ージ１１は、限られた外観サイズの中に４個の半導体チ
ップ１が組み込まれる構造のものであるため、ＢＧＡ基
板２においてもボンディング電極２ａの設置領域の面積
が少ない。Further, since the multi-chip package 11 of the present embodiment has a structure in which four semiconductor chips 1 are incorporated in a limited external size, the bonding electrodes 2 a are also provided on the BGA substrate 2. The area of the region is small.

【００３７】すなわち、図３に示すように、ＢＧＡ基板
２上において複数のボンディング電極２ａがそれぞれの
半導体チップ１の両脇近傍に一列となって配置されてお
り、２列に並んだ半導体チップ間に設けられた２列のボ
ンディング電極間は、例えば、数百μｍと非常に間隔が
狭く、かつこれらのボンディング電極２ａと半導体チッ
プ１の側面の距離も同様に数百μｍと近接している。That is, as shown in FIG. 3, a plurality of bonding electrodes 2a are arranged in a row on the BGA substrate 2 near both sides of each semiconductor chip 1, and between the two rows of semiconductor chips. Are very small, for example, several hundred μm, and the distance between these bonding electrodes 2a and the side surface of the semiconductor chip 1 is also close to several hundred μm.

【００３８】この状態で、図５に示すワイヤボンディン
グ装置において半導体チップ１のパッド１ｂとＢＧＡ基
板２のボンディング電極２ａとを２次ボンディングによ
って接続する際に、正ボンド（第１ボンドを半導体チッ
プ側とし、第２ボンドを基板側とするボンディング方
法）動作を行うと、キャピラリ６（ボンディングツー
ル）の移動軌跡において第２ボンド側への接地時のキャ
ピラリ６の傾斜角度が小さいため、半導体チップ１の主
面端部に衝突する。In this state, when the pad 1b of the semiconductor chip 1 and the bonding electrode 2a of the BGA substrate 2 are connected by secondary bonding in the wire bonding apparatus shown in FIG. 5, a positive bond (the first bond is connected to the semiconductor chip side). When the bonding method with the second bond on the substrate side is performed, the inclination angle of the capillary 6 at the time of grounding to the second bond side in the movement locus of the capillary 6 (bonding tool) is small. It collides with the end of the main surface.

【００３９】そこで、キャピラリ６の移動軌跡を半導体
チップ１上方に高く移動させれば半導体チップ１の端部
との衝突は回避可能ではあるが、マルチチップパッケー
ジ１１としての封止部５の高さ制限があるため、ワイヤ
ループは高く形成できず、その結果、逆ボンド（第１ボ
ンドを基板側とし、第２ボンドを半導体チップ側とする
ボンディング方法）動作で２次ボンディングを行うこと
が好ましく、図１〜図４に示すマルチチップパッケージ
１１では、図５に示すワイヤボンディング装置によっ
て、バンプ認識方式を用いるとともに、逆ボンド動作で
２次ボンディングを行っている。Therefore, if the movement trajectory of the capillary 6 is moved higher above the semiconductor chip 1, collision with the end of the semiconductor chip 1 can be avoided, but the height of the sealing portion 5 as the multi-chip package 11 can be avoided. Due to the limitation, the wire loop cannot be formed high. As a result, it is preferable to perform the secondary bonding by a reverse bonding (a bonding method in which the first bond is on the substrate side and the second bond is on the semiconductor chip side). In the multi-chip package 11 shown in FIGS. 1 to 4, the wire bonding apparatus shown in FIG. 5 uses the bump recognition method and performs the secondary bonding by the reverse bonding operation.

【００４０】したがって、逆ボンド動作を用いた際に
は、半導体チップ１側が第２ボンド側となるため、ネイ
ルヘッドボンディングによる初期ボールはＢＧＡ基板２
側に形成され、半導体チップ１のパッド１ｂの突起電極
１９には、前記初期ボールが配置されることはない。さ
らに、図８に示すように、半導体チップ１のパッド１ｂ
上の突起電極１９の中央突起部１９ｃは、２次ボンディ
ングのワイヤ３の接合によって潰れてなくなり、２次ボ
ンディング終了後の突起電極１９は、図９に示すように
比較的平坦な形状となる。Therefore, when the reverse bonding operation is used, the semiconductor chip 1 side becomes the second bonding side, so that the initial ball formed by the nail head bonding is removed from the BGA substrate 2.
The initial ball is not disposed on the protruding electrode 19 of the pad 1b of the semiconductor chip 1 formed on the side. Further, as shown in FIG.
The central protruding portion 19c of the upper protruding electrode 19 is not crushed by the bonding of the wire 3 in the secondary bonding, and the protruding electrode 19 after the completion of the secondary bonding has a relatively flat shape as shown in FIG.

【００４１】また、ＢＧＡ基板２は、図３、図４に示す
ように、例えば、各層に銅（Ｃｕ）などの金属薄膜が被
着されたガラス・エポキシ材などによる多層の配線構造
からなり、そのチップ支持面２ｂ上に設けられた各ボン
ディング電極２ａは、各層の配線パターンおよび各層を
貫通する導電材料充填のスルーホールを介して裏面２ｃ
のはんだボール接続用のランドに電気的に接続されてい
る。As shown in FIGS. 3 and 4, the BGA substrate 2 has a multi-layer wiring structure made of, for example, a glass / epoxy material having a metal thin film such as copper (Cu) applied to each layer. Each bonding electrode 2a provided on the chip supporting surface 2b is connected to a back surface 2c via a wiring pattern of each layer and a through hole filled with a conductive material penetrating each layer.
Are electrically connected to the solder ball connection lands.

【００４２】また、ワイヤ３は、例えば、金（Ａｕ）な
どの金属細線からなる。The wire 3 is made of, for example, a thin metal wire such as gold (Au).

【００４３】さらに、はんだボール４は、例えば、鉛／
すず（Ｐｂ／Ｓｎ）などからなるマルチチップパッケー
ジ１１の外部端子であり、ＢＧＡ基板２の裏面２ｃ上に
配置された複数のランドそれぞれに設けられている。Further, the solder ball 4 is made of, for example, lead /
It is an external terminal of the multi-chip package 11 made of tin (Pb / Sn) or the like, and is provided on each of a plurality of lands arranged on the back surface 2c of the BGA substrate 2.

【００４４】また、封止部５は、例えば、エポキシ樹脂
などの樹脂材料を硬化させて形成したものであり、この
樹脂材料によりＢＧＡ基板２に搭載された半導体チップ
１およびワイヤ３などの電気的な露出部分が覆われてモ
ールドされ、その結果、ＢＧＡタイプの表面実装形の半
導体パッケージとなる。The sealing portion 5 is formed, for example, by curing a resin material such as an epoxy resin, and the resin material is used to electrically connect the semiconductor chip 1 and the wires 3 mounted on the BGA substrate 2. The exposed portions are covered and molded, resulting in a BGA type surface mount type semiconductor package.

【００４５】次に、本実施の形態の半導体装置の製造方
法におけるワイヤボンディング工程で用いられるワイヤ
ボンディング装置の構造について説明する。Next, the structure of the wire bonding apparatus used in the wire bonding step in the method of manufacturing a semiconductor device according to the present embodiment will be described.

【００４６】前記ワイヤボンディング装置は、ワイヤ３
を用いて半導体チップ１のパッド１ｂとこれに対応する
ＢＧＡ基板２のボンディング電極２ａとを接続するもの
であり、本実施の形態の前記ワイヤボンディング装置
は、半導体チップ１のパッド１ｂに形成された突起電極
１９上にワイヤボンディング（２次ボンディング）を行
うことが可能なネイルヘッドボンダである。The wire bonding apparatus includes a wire 3
Is used to connect the pad 1b of the semiconductor chip 1 and the corresponding bonding electrode 2a of the BGA substrate 2. The wire bonding apparatus of the present embodiment is formed on the pad 1b of the semiconductor chip 1. This is a nail head bonder capable of performing wire bonding (secondary bonding) on the protruding electrodes 19.

【００４７】図５に示すワイヤボンディング装置の構成
について説明すると、半導体チップ１のパッド１ｂの位
置やパッド１ｂ上に形成された突起電極１９さらにＢＧ
Ａ基板２のボンディング電極２ａを撮像するカメラ７
と、カメラ７によって撮像された像からパッド１ｂおよ
びボンディング電極２ａさらにパッド１ｂ内の突起電極
１９の外形を認識（検出）し、かつこの検出結果に基づ
いて突起電極１９の中心位置１９ｂ（中心座標）を算出
して半導体チップ１のパッド１ｂ上の突起電極１９とワ
イヤ３とを電気的に接続する際の予め設定されたボンデ
ィング座標に対する補正を自動で行う制御部１７と、制
御部１７による前記補正に基づいて突起電極１９のほぼ
中心部１９ａにワイヤ３を押し当てて突起電極１９とワ
イヤ３とを接合し、かつワイヤ３とＢＧＡ基板２のボン
ディング電極２ａとを接合するボンディングツールであ
るキャピラリ６と、キャピラリ６に超音波を付与する超
音波振動子１３および超音波発振器１４と、超音波振動
子１３を介してキャピラリ６を支持するボンディングヘ
ッド１０と、それぞれに半導体チップ１が搭載された複
数のＢＧＡ基板２が連結されてなるチップマウント済み
の多連の配線基板である被処理物１６をボンディング時
に支持するヒートブロック１５とからなる。The structure of the wire bonding apparatus shown in FIG. 5 will be described. The position of the pad 1b of the semiconductor chip 1, the bump electrodes 19 formed on the pad 1b, and the BG
Camera 7 for imaging bonding electrode 2a of A substrate 2
Then, the outer shape of the pad 1b, the bonding electrode 2a, and the outer shape of the protruding electrode 19 in the pad 1b are recognized (detected) from the image picked up by the camera 7, and the center position 19b (central coordinate) of the protruding electrode 19 is ) To automatically correct the bonding coordinates set in advance when electrically connecting the protruding electrodes 19 on the pads 1b of the semiconductor chip 1 to the wires 3; Based on the correction, the capillary 3 is a bonding tool that presses the wire 3 against the substantially central portion 19a of the protruding electrode 19 to join the protruding electrode 19 and the wire 3, and also bonds the wire 3 and the bonding electrode 2a of the BGA substrate 2. 6, an ultrasonic oscillator 13 for applying ultrasonic waves to the capillary 6 and an ultrasonic oscillator 14, and a key through the ultrasonic oscillator 13. A bonding head 10 that supports the pillar 6 and a heat treatment that supports, at the time of bonding, a processing target 16 which is a chip-mounted multiple wiring substrate formed by connecting a plurality of BGA substrates 2 each having a semiconductor chip 1 mounted thereon. It consists of block 15.

【００４８】なお、前記ワイヤボンディング装置は、超
音波熱圧着によってワイヤ３と半導体チップ１のパッド
１ｂとを電気的に接続するものであり、ボンディング時
には、超音波振動子１３による超音波と、ボンディング
ヘッド１０による荷重と、ヒートブロック１５による熱
とをワイヤ３、ＢＧＡ基板２のボンディング電極２ａ、
半導体チップ１のパッド１ｂ上の突起電極１９に印加
し、これによってボンディング電極２ａとワイヤ３と
を、および、ワイヤ３と突起電極１９とを接続する。The wire bonding apparatus electrically connects the wire 3 and the pad 1b of the semiconductor chip 1 by ultrasonic thermocompression bonding. At the time of bonding, an ultrasonic wave generated by the ultrasonic vibrator 13 is used for bonding. The load from the head 10 and the heat from the heat block 15 are applied to the wire 3, the bonding electrode 2a of the BGA substrate 2,
A voltage is applied to the protruding electrode 19 on the pad 1b of the semiconductor chip 1, thereby connecting the bonding electrode 2a to the wire 3 and connecting the wire 3 to the protruding electrode 19.

【００４９】さらに、ボンディングヘッド１０には、こ
れを駆動させるリニアモータ１２が接続され、ボンディ
ング時には、例えば、０〜２５５ｇ程度の制御されたボ
ンディング荷重を先端に設けられたボンディングツール
６によって被処理物１６に付与する。Further, the bonding head 10 is connected to a linear motor 12 for driving the same. At the time of bonding, a controlled bonding load of, for example, about 0 to 255 g is applied by the bonding tool 6 provided at the tip. 16 is assigned.

【００５０】また、カメラ７は、ボンディングヘッド１
０の先端側端部に設置され、例えば、モノクロあるいは
カラーなどのＣＣＤ（Charge Coupled Device)カメラユ
ニットであり、さらに、このカメラ７の撮像側には種々
のレンズを備えた光学系８が設けられているとともに、
撮像時の光量調整機能付きの照明ユニット９が接続され
ている。The camera 7 includes the bonding head 1
0 is a CCD (Charge Coupled Device) camera unit of, for example, monochrome or color, and an optical system 8 having various lenses is provided on the imaging side of the camera 7. Along with
An illumination unit 9 having a light quantity adjustment function at the time of imaging is connected.

【００５１】なお、カメラ７は、図５に示す被処理物１
６すなわち半導体チップ１のパッド１ｂおよびこれに設
けられた突起電極１９あるいはワイヤ３さらにＢＧＡ基
板２のボンディング電極２ａなどを映し出すものであ
る。It is to be noted that the camera 7 is provided with an object 1 shown in FIG.
6, ie, the pads 1b of the semiconductor chip 1 and the projecting electrodes 19 or wires 3 provided thereon and the bonding electrodes 2a of the BGA substrate 2 and the like are projected.

【００５２】したがって、半導体チップ１のパッド１ｂ
の中心１ｃ、ＢＧＡ基板２のボンディング電極２ａまた
はパッド１ｂ上に設けられた突起電極１９の中心位置１
９ｂを検出する際には、カメラ７が映したパッド１ｂ、
ボンディング電極２ａ、突起電極１９およびワイヤ３の
像を画像処理し（例えば、白黒の２値化判定など）、こ
れによって、それぞれのパッド１ｂの中心１ｃおよび突
起電極１９の中心位置１９ｂあるいはボンディング電極
２ａを検出する。Therefore, the pad 1b of the semiconductor chip 1
Center 1c of the bump electrode 19 provided on the bonding electrode 2a or the pad 1b of the BGA substrate 2
When detecting 9b, the pad 1b projected by the camera 7
The images of the bonding electrode 2a, the protruding electrode 19, and the wire 3 are image-processed (for example, black and white binarization determination), whereby the center 1c of the pad 1b and the center position 19b of the protruding electrode 19 or the bonding electrode 2a Is detected.

【００５３】そこで、ワイヤボンディング（２次ボンデ
ィング）を行う前に、制御部１７によって実際のチップ
マウント後のパッド１ｂ上の突起電極１９の中心位置１
９ｂ（座標）を認識（検出）し、その後、予め設定され
た値（ボンディング座標）との補正を自動で行って、図
８、図９に示すように、パッド１ｂ上の突起電極１９の
ほぼ中心部１９ａにワイヤ３を押し当てて両者を接合す
るものである。Therefore, before wire bonding (secondary bonding) is performed, the control unit 17 controls the center position 1 of the projecting electrode 19 on the pad 1b after the actual chip mounting.
9b (coordinates) is recognized (detected), and thereafter, correction with a preset value (bonding coordinates) is automatically performed, and as shown in FIGS. The wire 3 is pressed against the central portion 19a to join them together.

【００５４】次に、本実施の形態によるマルチチップパ
ッケージ１１（半導体装置）の製造方法を、図６に示す
製造プロセスフロー図にしたがって説明する。Next, a method of manufacturing the multichip package 11 (semiconductor device) according to the present embodiment will be described with reference to a manufacturing process flow chart shown in FIG.

【００５５】始めに、組み立てに先立って、半導体ウェ
ハからダイシングされ、かつＳＤＲＡＭが形成された複
数の半導体チップ１、短冊状に例えば６個程度の複数個
取り用として形成された４層配線構造のＢＧＡ基板２、
金線などのワイヤ３、エポキシ樹脂などの樹脂封止用の
封止材、鉛／すずなどのはんだボール４などを準備す
る。First, prior to assembling, a plurality of semiconductor chips 1 diced from a semiconductor wafer and on which an SDRAM is formed, and a four-layer wiring structure formed in a strip shape for taking, for example, about six pieces. BGA substrate 2,
A wire 3 such as a gold wire, a sealing material for sealing a resin such as an epoxy resin, and a solder ball 4 such as lead / tin are prepared.

【００５６】なお、半導体チップ１は、ステップＳ１に
示すようにＫＧＤとして取得したものである。The semiconductor chip 1 is obtained as KGD as shown in step S1.

【００５７】つまり、半導体チップ１単体の状態でエー
ジング検査などの信頼性検査（スクリーニングテストと
もいう）を行い、良品選別を行って取得したものであ
る。That is, the semiconductor chip 1 is obtained by performing a reliability test (also referred to as a screening test) such as an aging test on the semiconductor chip 1 alone, and selecting good products.

【００５８】したがって、半導体チップ１の表面電極で
あるパッド１ｂ上には、前記信頼性検査時に使用したワ
イヤ３のワイヤ接合部３ａのみを残留させた突起電極１
９が設けられている。Therefore, on the pad 1b which is the surface electrode of the semiconductor chip 1, the protruding electrode 1 having only the wire joint 3a of the wire 3 used at the time of the reliability test is left.
9 are provided.

【００５９】続いて、ステップＳ２に示す半導体チップ
供給と、ステップＳ３に示すＢＧＡ基板供給を行い、こ
れにより、ステップＳ４に示すダイボンディングを行
う。つまり、半導体チップ１をＢＧＡ基板２に搭載す
る。Subsequently, the supply of the semiconductor chip shown in step S2 and the supply of the BGA substrate shown in step S3 are performed, whereby the die bonding shown in step S4 is performed. That is, the semiconductor chip 1 is mounted on the BGA substrate 2.

【００６０】ここでは、ダイボンディング工程におい
て、短冊状に複数個取り用として形成されたＢＧＡ基板
２上の複数の各実装領域上にダイボンディング材を介し
て複数の各半導体チップ１をそれぞれ実装する。Here, in the die bonding step, a plurality of semiconductor chips 1 are mounted via a die bonding material on a plurality of mounting regions on the BGA substrate 2 formed in a strip shape for taking a plurality. .

【００６１】その後、ステップＳ５に示すワイヤ供給を
行って、ステップＳ６に示すワイヤボンディングを行
う。Thereafter, the wire supply shown in step S5 is performed, and the wire bonding shown in step S6 is performed.

【００６２】すなわち、複数の各半導体チップ１の各パ
ッド１ｂとこれに対応するＢＧＡ基板２の各ボンディン
グ電極２ａとをワイヤ３によって接続する。その際、本
実施の形態では、ファーストボンディング（第１ボン
ド）はＢＧＡ基板２のボンディング電極２ａに行い、セ
カンドボンディング（第２ボンド）は半導体チップ１の
パッド１ｂに対して行う逆ボンド方式を用いてワイヤボ
ンディングを行う。That is, each pad 1 b of each of the plurality of semiconductor chips 1 is connected to each corresponding bonding electrode 2 a of the BGA substrate 2 by the wire 3. At this time, in this embodiment, a reverse bonding method in which first bonding (first bonding) is performed on the bonding electrode 2a of the BGA substrate 2 and second bonding (second bonding) is performed on the pad 1b of the semiconductor chip 1 is used. To perform wire bonding.

【００６３】なお、図５に示すワイヤボンディング装置
では、ボンディングツールであるキャピラリ６によって
ワイヤ３を押圧するとともに、ヒートブロック１５によ
って所定の温度に被処理物１６を加熱しつつ、超音波発
振器１４によって被処理物１６に所定の超音波を印加し
てボンディングを行う。In the wire bonding apparatus shown in FIG. 5, the wire 3 is pressed by the capillary 6 as a bonding tool, and the object 16 is heated to a predetermined temperature by the heat block 15 while the ultrasonic oscillator 14 A predetermined ultrasonic wave is applied to the workpiece 16 to perform bonding.

【００６４】すなわち、超音波熱圧着によってワイヤ３
とパッド１ｂ上の突起電極１９およびＢＧＡ基板２のボ
ンディング電極２ａとを接続する。That is, the wire 3 is formed by ultrasonic thermocompression bonding.
And the bump electrode 19 on the pad 1b and the bonding electrode 2a of the BGA substrate 2 are connected.

【００６５】まず、図５に示すワイヤボンディング装置
において、被処理物１６すなわちダイボンディングが行
われた多数個取りのＢＧＡ基板２をヒートブロック１５
上に搬送する。First, in the wire bonding apparatus shown in FIG. 5, an object 16 to be processed, that is, a multi-piece BGA substrate 2 on which die bonding has been performed, is heated.
Convey up.

【００６６】続いて、照明ユニット９によって照射する
光量を調整して、カメラ７によってＢＧＡ基板２のボン
ディング電極２ａを撮像してボンディング電極２ａの位
置を検出する。Subsequently, the amount of light emitted by the illumination unit 9 is adjusted, and the camera 7 images the bonding electrode 2a of the BGA substrate 2 to detect the position of the bonding electrode 2a.

【００６７】すなわち、カメラ７を用いて個々のボンデ
ィング電極２ａを映し出し、これを画像処理して、それ
ぞれのボンディング電極２ａの中心座標を求める。That is, the individual bonding electrodes 2a are projected using the camera 7, and image processing is performed to determine the center coordinates of each bonding electrode 2a.

【００６８】続いて、ボンディング電極２ａ上で金ボー
ル（初期ボール）を形成して第１ボンドであるＢＧＡ基
板２のボンディング電極２ａへのワイヤボンディングを
行い、これによってボンディング電極２ａとワイヤ３と
を接合する。Subsequently, a gold ball (initial ball) is formed on the bonding electrode 2a, and wire bonding is performed to the bonding electrode 2a of the BGA substrate 2 as the first bond, whereby the bonding electrode 2a and the wire 3 are connected. Join.

【００６９】その後、キャピラリ６の動作によって上方
にワイヤ３を立ち上げ、半導体チップ１側に湾曲させて
半導体チップ１のパッド１ｂの突起電極１９にセカンド
ボンディング（第２ボンド）を行う。Thereafter, the wire 3 is raised upward by the operation of the capillary 6, bent toward the semiconductor chip 1, and the second bonding (second bonding) is performed on the protruding electrode 19 of the pad 1 b of the semiconductor chip 1.

【００７０】その際、まず、カメラ７によって半導体チ
ップ１のパッド１ｂ上の突起電極１９の外形を認識し、
さらに、図７に示すように、この突起電極１９の中心位
置１９ｂを検出してバンプ認識を行う。At this time, first, the outer shape of the protruding electrode 19 on the pad 1b of the semiconductor chip 1 is recognized by the camera 7,
Further, as shown in FIG. 7, the bump position is recognized by detecting the center position 19b of the projecting electrode 19.

【００７１】その後、制御部１７によって、予め設定し
たボンディング座標と、検出（認識）した突起電極１９
の中心位置１９ｂとを自動補正し、これによって、図８
に示すように、この突起電極１９のほぼ中心部１９ａを
狙って第２ボンド側のワイヤボンディング（２次ボンデ
ィング）を行う。Thereafter, the controller 17 controls the bonding coordinates set in advance and the detected (recognized) bump electrodes 19.
Automatically corrects the center position 19b of FIG.
As shown in (2), wire bonding (secondary bonding) on the second bond side is performed aiming at a substantially central portion 19a of the protruding electrode 19.

【００７２】その結果、図８、図１０に示すように、半
導体チップ１のパッド１ｂ上の突起電極１９と２次ボン
ディングによるワイヤ接合部３ａのワイヤ接合部中心３
ｂとの接合位置精度（圧着位置精度）を±数μｍ程度の
高精度の誤差とすることができる。As a result, as shown in FIGS. 8 and 10, the projecting electrode 19 on the pad 1b of the semiconductor chip 1 and the center 3 of the wire bonding portion 3a of the wire bonding portion 3a by the secondary bonding are formed.
The bonding position accuracy (crimping position accuracy) with b can be a highly accurate error of about ± several μm.

【００７３】また、ワイヤボンディング（２次ボンディ
ング）が逆ボンド動作であるため、半導体チップ１側が
第２ボンド側となり、ネイルヘッドボンディングによる
初期ボールはＢＧＡ基板２側に形成され、半導体チップ
１のパッド１ｂの突起電極１９には、前記初期ボールが
配置されることはない。したがって、図８に示すよう
に、半導体チップ１のパッド１ｂ上の突起電極１９の中
央突起部１９ｃは、図９に示すように、２次ボンディン
グの際のワイヤ３の接合によって潰れてなくなり、２次
ボンディング終了後の突起電極１９は、比較的平坦な形
状となる。Since the wire bonding (secondary bonding) is a reverse bonding operation, the semiconductor chip 1 side is the second bonding side, and the initial ball by nail head bonding is formed on the BGA substrate 2 side, and the pad of the semiconductor chip 1 is formed. The initial ball is not arranged on the protruding electrode 19 of 1b. Therefore, as shown in FIG. 8, the central projection 19c of the projection electrode 19 on the pad 1b of the semiconductor chip 1 is not crushed by the bonding of the wire 3 at the time of the secondary bonding, as shown in FIG. After the completion of the next bonding, the protruding electrode 19 has a relatively flat shape.

【００７４】なお、同様の方法を繰り返してヒートブロ
ック１５上でＢＧＡ基板２の各ボンディング電極２ａと
半導体チップ１のパッド１ｂ上の突起電極１９とを順次
接続する。The bonding electrodes 2a of the BGA substrate 2 and the protruding electrodes 19 on the pads 1b of the semiconductor chip 1 are sequentially connected on the heat block 15 by repeating the same method.

【００７５】ワイヤボンディング終了後、被処理物１６
であるＢＧＡ基板２を搬送してワイヤボンディング装置
から取り出し、これを次工程に搬送する。After the completion of the wire bonding, the object 16
Is transported and taken out of the wire bonding apparatus, and is transported to the next step.

【００７６】その後、ステップＳ７に示す封止材供給を
行い、モールドによる封止を行う（ステップＳ８）。Thereafter, the sealing material is supplied as shown in step S7, and sealing is performed by a mold (step S8).

【００７７】ここでは、複数の半導体チップ１が実装さ
れた短冊状の複数個取りのＢＧＡ基板２を、半導体チッ
プ１およびワイヤ３などが露出しないように封止材によ
りモールドし、これによって封止部５を形成する。その
際、例えば、トランスファーモールドによって、前記封
止材を加熱して可塑化させ、加熱したモールド金型内に
圧入して成形する。Here, a plurality of strip-shaped BGA substrates 2 on which a plurality of semiconductor chips 1 are mounted are molded with a sealing material so that the semiconductor chips 1 and the wires 3 are not exposed. The part 5 is formed. At this time, the sealing material is heated and plasticized by, for example, transfer molding, and is pressed into a heated mold and molded.

【００７８】その後、ステップＳ９に示すように、基板
切断工程において、短冊状の複数個取りのＢＧＡ基板２
のフレームから１個ずつのパッケージに分けるための切
断を行う。Thereafter, as shown in step S9, in the substrate cutting step, a plurality of strip-shaped BGA substrates 2 are formed.
Is cut from the frame to separate the packages into individual packages.

【００７９】続いて、はんだボール付け工程において、
ステップＳ１０に示すはんだボール供給を行い、ＢＧＡ
基板２の裏面２ｃに外部端子となる複数のはんだボール
４を取り付ける（ステップＳ１１）。Subsequently, in the solder ball attaching step,
The solder balls shown in step S10 are supplied, and the BGA
A plurality of solder balls 4 serving as external terminals are attached to the back surface 2c of the substrate 2 (Step S11).

【００８０】最後に、ステップＳ１２に示す簡易選別を
行い、これにより、ＢＧＡタイプで、かつ表面実装形パ
ッケージである図１〜図４に示すマルチチップパッケー
ジ１１を完成させる。Finally, the simple selection shown in step S12 is performed, thereby completing the multichip package 11 shown in FIGS. 1 to 4 which is a BGA type and surface mount type package.

【００８１】なお、ステップＳ１２の簡易選別は、バー
ンイン検査などの信頼性検査を行わない検査（例えば、
簡易的外観検査や簡易的電気特性検査など）である。Incidentally, the simple sorting in step S12 is performed by an inspection without performing a reliability inspection such as a burn-in inspection (for example,
Simple appearance inspection and simple electrical characteristic inspection).

【００８２】すなわち、本実施の形態のマルチチップパ
ッケージ１１では、ＫＧＤとして取得した半導体チップ
１を搭載しているため、パッケージ組み立て後の前記信
頼性検査は省略可能になるためである。That is, in the multi-chip package 11 of the present embodiment, since the semiconductor chip 1 obtained as a KGD is mounted, the reliability inspection after assembling the package can be omitted.

【００８３】本実施の形態の半導体装置（マルチチップ
パッケージ１１）の製造方法によれば、以下のような作
用効果が得られる。According to the method of manufacturing the semiconductor device (multi-chip package 11) of the present embodiment, the following operation and effect can be obtained.

【００８４】すなわち、半導体装置の製造方法のワイヤ
ボンディング工程におけるワイヤボンディング時に、半
導体チップ１のパッド１ｂ上に形成された突起電極１９
の中心位置１９ｂを検出し、この検出結果に基づいて突
起電極１９に対してワイヤ３を押し当てるため、１次ボ
ンディング（ＫＧＤ取得用検査時のワイヤボンディン
グ）で残留した突起電極１９上に精度良く２次ボンディ
ング（マルチチップパッケージ１１組み立て時のワイヤ
ボンディング）を行うことができる。That is, at the time of wire bonding in the wire bonding step of the method of manufacturing a semiconductor device, the bump electrodes 19 formed on the pads 1b of the semiconductor chip 1 are formed.
Is detected, and the wire 3 is pressed against the protruding electrode 19 based on the detection result, so that the wire 3 is accurately placed on the protruding electrode 19 remaining in the primary bonding (wire bonding at the time of the KGD acquisition inspection). Secondary bonding (wire bonding at the time of assembling the multi-chip package 11) can be performed.

【００８５】つまり、２次ボンディング時には、突起電
極１９のほぼ中心部１９ａを狙って２次ボンディングを
行うため、半導体チップ１のパッド１ｂ内における１次
ボンディング時の突起電極１９の圧着位置に無関係に突
起電極１９のほぼ中心部に対して２次ボンディングを行
うことができ、したがって、１次ボンディングによる突
起電極１９上に精度良く２次ボンディングを行うことが
できる。That is, at the time of the secondary bonding, since the secondary bonding is performed aiming at the substantially central portion 19a of the protruding electrode 19, regardless of the crimping position of the protruding electrode 19 in the primary bonding in the pad 1b of the semiconductor chip 1. The secondary bonding can be performed on the substantially central portion of the protruding electrode 19, so that the secondary bonding can be performed on the protruding electrode 19 by the primary bonding with high accuracy.

【００８６】本実施の形態のバンプ認識を用いたワイヤ
ボンディングによれば、図１０に示すように、半導体チ
ップ１のパッド１ｂ上の突起電極１９と２次ボンディン
グによるワイヤ接合部３ａとの接合位置精度（圧着位置
精度）を±数μｍ程度とすることができ、その結果、両
者の位置合わせ精度を高精度にすることができる。According to the wire bonding using bump recognition according to the present embodiment, as shown in FIG. 10, the bonding position between the bump electrode 19 on the pad 1b of the semiconductor chip 1 and the wire bonding portion 3a by the secondary bonding. The accuracy (crimping position accuracy) can be set to about ± several μm, and as a result, the positioning accuracy of both can be made high.

【００８７】なお、図１１に示すバンプ認識を行わない
比較例のワイヤボンディングでは、半導体チップ１のパ
ッド１ｂ上の突起電極１９と２次ボンディングによるワ
イヤ接合部３ａとの前記接合位置精度の最大値が、±数
μｍ×２となり、ワイヤ接合部３ａのはみ出し量も大き
くなるが、これと比べて図１０に示す本実施の形態の位
置合わせ精度は非常に高精度であることがわかる。In the wire bonding of the comparative example in which bump recognition is not performed as shown in FIG. 11, the maximum value of the bonding position accuracy between the protruding electrode 19 on the pad 1b of the semiconductor chip 1 and the wire bonding portion 3a by the secondary bonding. However, the amount of protrusion of the wire bonding portion 3a is increased by ± several μm × 2, but the positioning accuracy of the present embodiment shown in FIG. 10 is much higher than this.

【００８８】さらに、本実施の形態のバンプ認識を行っ
たワイヤボンディングと、比較例によるバンプ認識を行
わないワイヤボンディングとで、マルチチップパッケー
ジ１１において全てのパッド１ｂに対する不圧着率を調
べたところ、バンプ認識を行わない場合の不圧着率が数
％（この際の不良製品率は１００％となる）であったの
に対して、バンプ認識を行う場合の不圧着率は０％（こ
の際の不良製品率は０％となる）であり、その差は明確
である。Further, the non-compression ratios of all the pads 1b in the multi-chip package 11 were examined by using the wire bonding with bump recognition according to the present embodiment and the wire bonding without bump recognition according to the comparative example. The non-compression ratio when bump recognition is not performed is several percent (the defective product ratio at this time is 100%), whereas the non-compression ratio when bump recognition is performed is 0% (in this case, the non-compression ratio is 100%). The defective product rate is 0%), and the difference is clear.

【００８９】したがって、本実施の形態のバンプ認識を
行うワイヤボンディング（２次ボンディング）において
も安定したボンディング性を得ることが可能になり、そ
の結果、２次ボンディングでの圧着不良を低減できると
ともに、隣接パッド間ショートの発生を防止することが
できる。Therefore, it is possible to obtain a stable bonding property also in the wire bonding (secondary bonding) for performing bump recognition according to the present embodiment, and as a result, it is possible to reduce the bonding failure in the secondary bonding, and The occurrence of a short circuit between adjacent pads can be prevented.

【００９０】これにより、２次ボンディングにおける歩
留り向上を図ることが可能になるとともに、マルチチッ
プパッケージ１１（半導体装置）の原価低減を図ること
ができる。As a result, the yield in the secondary bonding can be improved, and the cost of the multichip package 11 (semiconductor device) can be reduced.

【００９１】さらに、２次ボンディングにおいて安定し
たボンディング性を得ることが可能になるため、マルチ
チップパッケージ１１の信頼性を向上できる。Further, since it is possible to obtain a stable bonding property in the secondary bonding, the reliability of the multi-chip package 11 can be improved.

【００９２】また、２次ボンディングにおいて安定した
ボンディング性を得ることが可能になるため、ワイヤ接
合部３ａの圧着サイズをより小さく制御することが可能
になり、その結果、さらに狭パッドピッチ化を図ったマ
ルチチップパッケージ１１などの半導体装置の製造の際
にも、２次ボンディング時の圧着サイズをこれに対応さ
せることができる。Further, since it is possible to obtain a stable bonding property in the secondary bonding, it is possible to control the compression size of the wire bonding portion 3a to be smaller, and as a result, it is possible to further narrow the pad pitch. When manufacturing a semiconductor device such as the multi-chip package 11 as well, the compression size at the time of the secondary bonding can correspond to this.

【００９３】また、２次ボンディングの際の突起電極１
９の位置検出とその自動補正とを自動で行うことによ
り、ワイヤボンディング装置の自動運転が可能となり、
その作業性の向上および製造コストの低減を図ることが
可能になる。Also, the protruding electrode 1 at the time of secondary bonding
The automatic operation of the wire bonding apparatus becomes possible by automatically performing the position detection of 9 and the automatic correction thereof,
It is possible to improve the workability and reduce the manufacturing cost.

【００９４】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments of the invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

【００９５】例えば、前記実施の形態では、マルチチッ
プパッケージ１１の製造の際に、複数個取りのＢＧＡ基
板２を用いて複数のマルチチップパッケージ１１を纏め
て製造する場合を説明したが、予め、個々の半導体パッ
ケージ相当のＢＧＡ基板２を切り出し、この１枚１枚の
ＢＧＡ基板２を用いて個々にマルチチップパッケージ１
１を組み立ててもよい。For example, in the above-described embodiment, a case has been described where a plurality of multi-chip packages 11 are collectively manufactured using a plurality of BGA substrates 2 when manufacturing the multi-chip package 11. A BGA substrate 2 corresponding to each semiconductor package is cut out, and the multi-chip package 1 is individually formed using each of the BGA substrates 2.
1 may be assembled.

【００９６】また、前記実施の形態では、半導体チップ
１が長方形の場合について説明したが、半導体チップ１
は正方形であってもよい。In the above embodiment, the case where the semiconductor chip 1 is rectangular has been described.
May be square.

【００９７】さらに、半導体チップ１に設けられるパッ
ド１ｂの設置箇所についても、センタパッド配列に限定
することはなく、主面１ａの端部にパッド１ｂが設けら
れた外周パッド配列であってもよい。Further, the location of the pads 1b provided on the semiconductor chip 1 is not limited to the center pad arrangement, but may be an outer peripheral pad arrangement in which the pads 1b are provided at the ends of the main surface 1a. .

【００９８】その際、パッド１ｂの数およびはんだボー
ル４の数についても、前記実施の形態のものに限定され
るものではない。At this time, the number of pads 1b and the number of solder balls 4 are not limited to those of the above-described embodiment.

【００９９】また、ＢＧＡ基板２上に実装される半導体
チップ１の数は４個に限らず、１個、２個、３個あるい
は５個以上の複数個の半導体チップ１をＢＧＡ基板２上
に実装する半導体パッケージであってもよい。The number of semiconductor chips 1 mounted on the BGA substrate 2 is not limited to four, but one, two, three, or five or more semiconductor chips 1 are mounted on the BGA substrate 2. It may be a semiconductor package to be mounted.

【０１００】また、前記実施の形態では、ワイヤボンデ
ィングが逆ボンド方式の場合を例に取り上げて説明した
が、ワイヤボンディングは正ボンド方式であってもよ
い。Further, in the above embodiment, the case where the wire bonding is the reverse bonding method has been described as an example, but the wire bonding may be the normal bonding method.

【０１０１】さらに、前記実施の形態では、ワイヤボン
ディングがネイルヘッドボンディングの場合について説
明したが、前記ワイヤボンディングは、例えば、ウェッ
ジボンディングであってもよい。Further, in the above embodiment, the case where the wire bonding is nail head bonding has been described, but the wire bonding may be, for example, wedge bonding.

【０１０２】また、半導体チップ１に形成される回路
は、ＳＤＲＡＭに限らず、ＤＲＡＭ、ＳＲＡＭ（Static
Random Access Memory ）などの他の記憶回路を形成す
る場合にも適用可能であることはいうまでもなく、ま
た、記憶回路以外の半導体集積回路であってもよい。The circuits formed on the semiconductor chip 1 are not limited to SDRAMs, but include DRAMs, SRAMs (Static
Needless to say, the present invention can be applied to the case of forming another storage circuit such as a random access memory, and a semiconductor integrated circuit other than the storage circuit may be used.

【０１０３】さらに、ＢＧＡ基板２は４層配線構造に限
らず、４層以下あるいは５層以上の配線構造にすること
も可能である。Further, the BGA substrate 2 is not limited to a four-layer wiring structure, but may have a wiring structure of four or less layers or five or more layers.

【０１０４】また、本発明は、記憶回路が形成された複
数の半導体チップ１を実装したメモリパッケージに効果
的であるが、記憶回路の半導体チップ１とマイクロコン
ピュータの半導体チップ１などのように、異種チップを
組み合わせて１つのパッケージに実装するシステムＬＳ
Ｉなどの半導体装置についても応用可能である。The present invention is effective for a memory package in which a plurality of semiconductor chips 1 each having a memory circuit are mounted. However, the present invention is not limited to the semiconductor chip 1 of a memory circuit and the semiconductor chip 1 of a microcomputer. System LS for combining different types of chips and mounting them in one package
It is also applicable to semiconductor devices such as I.

【０１０５】[0105]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【０１０６】（１）．ワイヤボンディング時に、半導体
チップの表面電極上に形成された突起電極の中心位置を
検出し、突起電極の中心部を狙って２次ボンディングを
行うため、半導体チップの表面電極内における突起電極
の圧着位置に無関係に突起電極の中心部に対して２次ボ
ンディングを行うことができる。したがって、２次ボン
ディングにおいても安定したボンディング性を得ること
が可能になり、その結果、２次ボンディングでの圧着不
良を低減できるとともに、隣接パッド間ショートの発生
を防止することができる。(1). During wire bonding, the center position of the protruding electrode formed on the surface electrode of the semiconductor chip is detected, and the secondary bonding is performed aiming at the center of the protruding electrode. Regardless, the secondary bonding can be performed on the center of the protruding electrode. Therefore, a stable bonding property can be obtained even in the secondary bonding, and as a result, it is possible to reduce the bonding failure in the secondary bonding and to prevent the occurrence of a short circuit between adjacent pads.

【０１０７】（２）．前記（１）により、２次ボンディ
ングにおける歩留り向上を図ることが可能になるととも
に、半導体装置の原価低減を図ることができる。(2). According to the above (1), the yield in the secondary bonding can be improved, and the cost of the semiconductor device can be reduced.

【０１０８】（３）．前記（１）により、半導体装置の
信頼性を向上できるとともに、ワイヤ接合部の圧着サイ
ズをより小さく制御することが可能になり、その結果、
さらに狭パッドピッチ化を図った半導体装置の製造の際
にも、２次ボンディング時の圧着サイズをこれに対応さ
せることができる。(3). According to the above (1), the reliability of the semiconductor device can be improved, and the crimping size of the wire bonding portion can be controlled to be smaller. As a result,
Furthermore, when manufacturing a semiconductor device with a narrower pad pitch, the pressure bonding size at the time of the secondary bonding can be adapted to this.

【０１０９】（４）．２次ボンディングの際の突起電極
の位置検出を自動で行うことにより、ワイヤボンディン
グ装置の自動運転が可能となり、その作業性の向上およ
び製造コストの低減を図ることが可能になる。(4). By automatically detecting the position of the protruding electrode at the time of the secondary bonding, the automatic operation of the wire bonding apparatus can be performed, and the workability can be improved and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態の半導体装置の製造方法に
よって組み立てられるＢＧＡ形のマルチチップパッケー
ジの構造の一例を示す平面図である。FIG. 1 is a plan view showing an example of a structure of a BGA type multi-chip package assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図２】（ａ),（ｂ),（ｃ）は図１に示すマルチチップ
パッケージの構造を示す図であり、（ａ) は正面図、
（ｂ）は側面図、（ｃ）は底面図である。FIGS. 2A, 2B, and 2C are diagrams showing the structure of the multi-chip package shown in FIG. 1; FIG.
(B) is a side view, and (c) is a bottom view.

【図３】図１に示すマルチチップパッケージにおける半
導体チップの実装状態の一例を封止部を透過して示す概
略平面図である。FIG. 3 is a schematic plan view showing an example of a mounting state of a semiconductor chip in the multi-chip package shown in FIG. 1 through a sealing portion.

【図４】図１に示すマルチチップパッケージのＡ−Ａ線
に沿う断面の構造を示す断面図である。FIG. 4 is a cross-sectional view showing a structure of a cross section taken along line AA of the multi-chip package shown in FIG.

【図５】本発明の実施の形態の半導体装置の製造方法で
用いられるワイヤボンディング装置の基本構造の一例を
示す構成図である。FIG. 5 is a configuration diagram illustrating an example of a basic structure of a wire bonding apparatus used in the method for manufacturing a semiconductor device according to the embodiment of the present invention;

【図６】図１に示すマルチチップパッケージの製造手順
の一例を示すプロセスフロー図である。FIG. 6 is a process flow chart showing an example of a manufacturing procedure of the multi-chip package shown in FIG.

【図７】本発明の実施の形態の半導体装置の製造方法の
ワイヤボンディング工程における突起電極の位置の検出
状態の一例を示す平面図である。FIG. 7 is a plan view showing an example of a detection state of a position of a protruding electrode in a wire bonding step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図８】本発明による実施の形態の半導体装置の製造方
法のワイヤボンディング工程における２次ボンディング
時の状態の一例を示す部分断面図である。FIG. 8 is a partial cross-sectional view showing one example of a state at the time of secondary bonding in a wire bonding step of the method for manufacturing a semiconductor device according to the embodiment of the present invention;

【図９】本発明による実施の形態の半導体装置の製造方
法のワイヤボンディング工程における２次ボンディング
終了後のワイヤ接合部の構造の一例を示す部分断面図で
ある。FIG. 9 is a partial cross-sectional view showing an example of a structure of a wire bonding portion after a secondary bonding in a wire bonding step of the method for manufacturing a semiconductor device according to the embodiment of the present invention;

【図１０】本発明による実施の形態の半導体装置の製造
方法のワイヤボンディング終了後のワイヤ接合状態の一
例を示す部分平面図である。FIG. 10 is a partial plan view showing an example of a wire bonding state after wire bonding is completed in the method for manufacturing a semiconductor device according to the embodiment of the present invention;

【図１１】図１０に示すワイヤ接合状態に対する比較例
のワイヤ接合状態を示す部分平面図である。11 is a partial plan view showing a wire bonding state of a comparative example with respect to the wire bonding state shown in FIG. 10;

【符号の説明】[Explanation of symbols]

１ 半導体チップ １ａ 主面 １ｂ パッド（表面電極） １ｃ 中心 １ｄ パッド用開口部 ２ ＢＧＡ基板（チップ支持基板） ２ａ ボンディング電極 ２ｂ チップ支持面 ２ｃ 裏面 ３ ワイヤ ３ａ ワイヤ接合部 ３ｂ ワイヤ接合部中心 ４ はんだボール（外部端子） ５ 封止部 ６ キャピラリ（ボンディングツール） ７ カメラ ８ 光学系 ９ 照明ユニット １０ ボンディングヘッド １１ マルチチップパッケージ（半導体装置） １２ リニアモータ １３ 超音波振動子 １４ 超音波発振器 １５ ヒートブロック １６ 被処理物 １７ 制御部 １８ マーク １９ 突起電極 １９ａ 中心部 １９ｂ 中心位置 １９ｃ 中央突起部 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Main surface 1b Pad (surface electrode) 1c Center 1d Pad opening 2 BGA substrate (chip support substrate) 2a Bonding electrode 2b Chip support surface 2c Back surface 3 Wire 3a Wire joint 3b Wire joint center 4 Solder ball (External terminals) 5 Sealing part 6 Capillary (bonding tool) 7 Camera 8 Optical system 9 Lighting unit 10 Bonding head 11 Multi-chip package (semiconductor device) 12 Linear motor 13 Ultrasonic oscillator 14 Ultrasonic oscillator 15 Heat block 16 Cover Processed object 17 Control part 18 Mark 19 Projection electrode 19a Central part 19b Center position 19c Central projection

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 表面電極に突起電極が形成された半導体
チップを用いて組み立てられる半導体装置の製造方法で
あって、 前記表面電極に前記突起電極が形成された前記半導体チ
ップを準備する工程と、 前記半導体チップをチップ支持基板に搭載する工程と、 前記半導体チップの前記表面電極に形成された前記突起
電極の位置を検出する工程と、 前記検出結果に基づいてボンディングツールにより前記
突起電極の中心部にボンディング用のワイヤを押し当て
て前記突起電極と前記ワイヤとを接合して、前記突起電
極と前記チップ支持基板のボンディング電極とをワイヤ
ボンディングによって接合する工程と、 前記チップ支持基板に複数の外部端子を設ける工程とを
有することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device assembled using a semiconductor chip having a surface electrode provided with a bump electrode, comprising: preparing the semiconductor chip having the surface electrode provided with the bump electrode; A step of mounting the semiconductor chip on a chip supporting substrate; a step of detecting a position of the projecting electrode formed on the surface electrode of the semiconductor chip; and a center of the projecting electrode by a bonding tool based on the detection result. Bonding the protruding electrode and the wire by pressing a bonding wire against the wire, and bonding the protruding electrode and the bonding electrode of the chip supporting substrate by wire bonding; Providing a terminal. 【請求項２】 表面電極に突起電極が形成された半導体
チップを用いて組み立てられる半導体装置の製造方法で
あって、 信頼性検査によって良品として選別され、前記表面電極
にワイヤボンディングによって形成された前記突起電極
が設けられた前記半導体チップを準備する工程と、 前記半導体チップをチップ支持基板に搭載する工程と、 前記半導体チップの前記表面電極に形成された前記突起
電極の中心位置を検出する工程と、 前記検出結果に基づいてボンディングツールにより前記
突起電極の中心部にボンディング用のワイヤを押し当て
て前記突起電極と前記ワイヤとを接合して、前記突起電
極と前記チップ支持基板のボンディング電極とをワイヤ
ボンディングによって接合する工程と、 前記チップ支持基板に複数の外部端子を設ける工程とを
有することを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device assembled by using a semiconductor chip having a surface electrode on which a protruding electrode is formed, wherein the semiconductor device is selected as a non-defective product by a reliability test and formed on the surface electrode by wire bonding. Preparing the semiconductor chip provided with the protruding electrodes; mounting the semiconductor chip on a chip supporting substrate; and detecting a center position of the protruding electrodes formed on the surface electrodes of the semiconductor chip. A bonding tool is pressed against the center of the protruding electrode by a bonding tool based on the detection result to join the protruding electrode and the wire, and the protruding electrode and the bonding electrode of the chip supporting substrate are connected to each other. Bonding by wire bonding; and providing a plurality of external terminals on the chip supporting substrate. The method of manufacturing a semiconductor device characterized by having a degree. 【請求項３】 表面電極に突起電極が形成された半導体
チップを用いて組み立てられる半導体装置の製造方法で
あって、 信頼性検査によって良品として選別され、前記表面電極
にワイヤボンディングによって形成された前記突起電極
が設けられた前記半導体チップを準備する工程と、 前記半導体チップをチップ支持基板に搭載する工程と、 ボンディングツールを用いてボンディング用のワイヤを
前記チップ支持基板のボンディング電極にワイヤボンデ
ィングによって接合する第１ボンドを行う工程と、 前記第１ボンド後、前記半導体チップの前記表面電極に
形成された前記突起電極の中心位置を検出する工程と、 前記検出結果に基づいて前記ボンディングツールにより
前記突起電極の中心部に前記ワイヤを押し当てて前記突
起電極と前記ワイヤとをワイヤボンディングによって接
合する第２ボンドを行う工程と、 前記チップ支持基板に複数の外部端子を設ける工程とを
有することを特徴とする半導体装置の製造方法。3. A method of manufacturing a semiconductor device assembled by using a semiconductor chip having a surface electrode on which a protruding electrode is formed, wherein the semiconductor device is selected as a non-defective product by a reliability test and formed on the surface electrode by wire bonding. Preparing the semiconductor chip provided with the protruding electrodes; mounting the semiconductor chip on a chip support substrate; bonding wires for bonding to bonding electrodes of the chip support substrate by wire bonding using a bonding tool. Performing a first bond, detecting the center position of the protrusion electrode formed on the front surface electrode of the semiconductor chip after the first bond, and performing the protrusion using the bonding tool based on the detection result. The wire is pressed against the center of the electrode, and the protruding electrode and the wire The method of manufacturing a semiconductor device comprising the steps of performing a second bond joining the Ya by wire bonding, that a step of providing a plurality of external terminals on the chip supporting substrate. 【請求項４】 表面電極に突起電極が形成された半導体
チップを用いて組み立てられる半導体装置の製造方法で
あって、 信頼性検査によって良品として選別され、前記表面電極
にワイヤボンディングによって形成された前記突起電極
が設けられた複数の前記半導体チップを準備する工程
と、 複数の前記半導体チップを１つのチップ支持基板に搭載
する工程と、 それぞれの前記半導体チップの前記表面電極に形成され
た前記突起電極の中心位置を検出する工程と、 前記検出結果に基づいてボンディングツールにより前記
突起電極の中心部にボンディング用のワイヤを押し当て
て前記突起電極と前記ワイヤとを接合して、前記突起電
極と前記チップ支持基板のボンディング電極とをワイヤ
ボンディングによって接合する工程と、 前記チップ支持基板に複数の外部端子を設ける工程とを
有することを特徴とする半導体装置の製造方法。4. A method for manufacturing a semiconductor device assembled using a semiconductor chip having a surface electrode and a projection electrode formed thereon, wherein the semiconductor device is selected as a non-defective product by a reliability test, and is formed on the surface electrode by wire bonding. A step of preparing a plurality of the semiconductor chips provided with the protruding electrodes; a step of mounting the plurality of the semiconductor chips on one chip supporting substrate; and a step of forming the protruding electrodes formed on the surface electrodes of the respective semiconductor chips. Detecting the center position of, the bonding tool is pressed against the center of the protruding electrode by a bonding tool based on the detection result, and the protruding electrode and the wire are joined, and the protruding electrode and the Bonding the bonding electrode of the chip supporting substrate to the bonding electrode by wire bonding; The method of manufacturing a semiconductor device characterized by a step of providing a plurality of external terminals to the plate. 【請求項５】 表面電極に突起電極が形成された半導体
チップを用いて組み立てられる半導体装置の製造方法で
あって、 信頼性検査によって良品として選別され、前記表面電極
にネイルヘッドボンディングによるワイヤボンディング
によって形成された前記突起電極が設けられた前記半導
体チップを準備する工程と、 前記半導体チップをチップ支持基板に搭載する工程と、 前記半導体チップの前記表面電極に形成された前記突起
電極の中心位置を自動で検出する工程と、 前記検出結果に基づいてボンディングツールであるキャ
ピラリにより前記突起電極の中心部にボンディング用の
ワイヤを押し当てて前記突起電極と前記ワイヤとを接合
して、前記突起電極と前記チップ支持基板のボンディン
グ電極とをネイルヘッドボンディングによるワイヤボン
ディングによって接合する工程と、 前記チップ支持基板に複数の外部端子を設ける工程とを
有することを特徴とする半導体装置の製造方法。5. A method of manufacturing a semiconductor device assembled using a semiconductor chip having a surface electrode on which a protruding electrode is formed, wherein the semiconductor device is selected as a non-defective product by a reliability test, and is wire-bonded to the surface electrode by nail head bonding. Preparing the semiconductor chip provided with the formed protruding electrode; mounting the semiconductor chip on a chip supporting substrate; and setting a center position of the protruding electrode formed on the front surface electrode of the semiconductor chip. The step of automatically detecting, and a bonding wire is pressed against a center portion of the protruding electrode by a capillary which is a bonding tool based on the detection result to join the protruding electrode and the wire, and the protruding electrode and The bonding electrode of the chip supporting substrate is connected to a wire by nail head bonding. The method of manufacturing a semiconductor device, characterized in that it comprises a step of joining by Ya bonding, and a step of providing a plurality of external terminals on the chip supporting substrate.
JP35924199A 1999-12-17 1999-12-17 Manufacturing method of semiconductor device Pending JP2001176916A (en)

Priority Applications (1)

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JP35924199A JP2001176916A (en) 1999-12-17 1999-12-17 Manufacturing method of semiconductor device

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JP35924199A JP2001176916A (en) 1999-12-17 1999-12-17 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JP2001176916A true JP2001176916A (en) 2001-06-29

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004282056A (en) * 2003-02-27 2004-10-07 Sumitomo Bakelite Co Ltd Semiconductor device, method of manufacturing semiconductor element, and method of manufacturing semiconductor device
JP5005113B2 (en) * 2009-04-15 2012-08-22 オリンパスメディカルシステムズ株式会社 Semiconductor device and endoscope

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004282056A (en) * 2003-02-27 2004-10-07 Sumitomo Bakelite Co Ltd Semiconductor device, method of manufacturing semiconductor element, and method of manufacturing semiconductor device
JP4620366B2 (en) * 2003-02-27 2011-01-26 住友ベークライト株式会社 Semiconductor device, semiconductor element manufacturing method, and semiconductor device manufacturing method
JP5005113B2 (en) * 2009-04-15 2012-08-22 オリンパスメディカルシステムズ株式会社 Semiconductor device and endoscope

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