JP2001176806A - Method for forming semiconductor film, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor film forming method for forming a semiconductor film of high quality on a substrate. SOLUTION: This is a semiconductor forming method for forming a semiconductor film on substrate by using bias catalyst CVD, high-density bias catalyst CVD, bias pressure-reduction CVD, bias atmospheric CVD. This method has a stage where a semiconductor film containing one of tin, germanium, and lead and an insulating film are formed on the substrate, by supplying raw material gas to a vacuum chamber 1 and applying an electric field below a glow discharge start voltage between the substrate 10 and an electrode 3a arranged in the evacuated vessel 1, a stage where the semiconductor film and insulating film are irradiated with laser light and annealed, and a stage where annealing is carried out with stream after the annealing stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor film and a method of manufacturing a thin film semiconductor device, and more particularly to a method of manufacturing a high quality thin film semiconductor device and to a large display device or solid-state imaging device. The present invention relates to a semiconductor film forming method capable of manufacturing an applicable thin film semiconductor device and a method of manufacturing a thin film semiconductor device.

[0002]

2. Description of the Related Art An insulated gate polysilicon TFT used in a conventional liquid crystal display device or the like is formed by forming an amorphous silicon film on a low heat-resistant substrate by a plasma CVD method or the like, and excimer laser annealing. Generally, a film is formed. After the formation of the polysilicon film, a gate insulating film (such as a silicon oxide film) is formed by a plasma CVD method or the like. Positive charges due to defects (plasma damage) and impurities in the gate insulating film are generated by the gate insulating film. If it exists near the interface with the semiconductor, a shift (movement) of the flat band voltage occurs. This is n-ch M
Depletion of IS transistor, p-ch M
Causing the on-voltage of the IS transistor to increase,
This leads to a phenomenon of an increase in threshold voltage, and a circuit using these transistors has a problem that there is a problem in integration into a circuit.

It is considered that the positive charges are generated by dangling bonds of silicon in a gate insulating film, for example, a silicon oxide film. To prevent the generation of this positive charge, a post-annealing method has been developed to compensate for defects by performing a heat treatment in an oxygen atmosphere such as air or a reducing gas containing hydrogen gas after forming the gate insulating film. Have been. However, this post-annealing method has a problem that high-temperature heating of 400 ° C. or higher is generally required. Further, the post-annealing method has a disadvantage that the shift of the flat band voltage may be increased depending on the quality of the insulating film.

Therefore, a method has been developed in which an amorphous silicon film is formed by a plasma CVD method or the like, followed by excimer laser annealing to form a polysilicon film, and then annealing the polysilicon film in water vapor. . The effect of using this method is to modify the insulating film and the semiconductor, improve the mobility in the case of forming a TFT, improve the ohmic contact, suppress the hot electron deterioration, and improve the integrated circuit. Effects such as realization of high-speed operation have been reported.

[0005] In this method, steam annealing is performed after the aluminum electrode is formed. One of the reasons is that it is difficult to obtain an ohmic contact if a water vapor annealing treatment is performed before forming an aluminum electrode. However, if steam annealing is performed after the aluminum electrode is formed, an aluminum oxide and aluminum hydroxide film is formed on the surface of the aluminum electrode, making it difficult to remove the electrode to the outside. That is,
Ohmic contact between the gold wire bonding and the electroless Ni / Au plating and the solder bumps tends to be insufficient, which causes problems in the quality and reliability of the formed TFT.

On the other hand, from the viewpoint of improving the mobility of the polysilicon film, the amorphous / polysilicon film formed by plasma CVD, low pressure CVD or the like is simply subjected to high temperature or excimer laser annealing (ELA) treatment (hereinafter referred to as "ELA"). In this case, the mobility of the polysilicon film has been improved. As a result, the polysilicon TF formed by this method
The electron mobility of T is about 80 to 120 cm ² / Vsec, which can cope with high definition. Recently, a polysilicon TFT LCD integrated with a driving circuit has attracted attention.

However, the polysilicon T
In the FT manufacturing method, the limit is to obtain an electron mobility of about 80 to 120 cm ² / Vsec. In addition, there are problems that the excimer laser output is unstable, the productivity is low, the apparatus becomes expensive due to the increase in the size of the apparatus, the yield is low, and improvement in quality is desired. . In particular,
In the case of a large glass substrate measuring 1 m square, these problems are magnified, and the performance, quality, and cost of the semiconductor are more remarkably reduced.

On the other hand, in each of the above-mentioned methods, since the plasma CVD method is used, non-uniformity of the electric field of the plasma, non-uniformity of the electric field on the substrate due to fluctuation, plasma-induced electric charge, etc. occur, and these influences affect the substrate. In addition, there is a problem that a transistor may be damaged, a short circuit or the like (charge-up or discharge breakdown of a gate oxide film or the like, discharge between wirings or the like) may occur. This phenomenon tends to occur particularly when plasma is turned on / off. In addition, there is a possibility that ultraviolet rays may be damaged by light emission from the plasma, plasma discharge in a large area is difficult, standing waves are generated, uniformity is difficult to obtain, the equipment is complicated and expensive, and maintenance is required. Is also a problem.

Therefore, in recent years, a kind of catalyst CV of thermal CVD has been developed.
An excellent method called the D method has been developed, and studies on its practical use have been promoted. This catalytic CVD method is a method capable of forming a polysilicon film and a silicon nitride film on an insulating substrate such as a glass substrate at a low temperature. In the catalytic CVD method, the electron mobility of the Hall element of about 20 to 50 cm ² / Vsec is obtained without annealing.

However, the above-mentioned catalytic CVD method has the following problems. That is, a high quality TFT device cannot be obtained with the electron mobility of the Hall element of about 20 to 50 cm ² / Vsec obtained by the above-described catalytic CVD. In order to manufacture a high quality TFT device, it is necessary to improve the mobility. When a polysilicon film is formed on a glass substrate, an initial amorphous silicon transition layer (5 to 10 nm) is easily formed depending on the film forming conditions. There is a problem that it is difficult to obtain. In general, as a drive circuit integrated type polysilicon TFT LCD, since the bottom gate type TFT is easy to manufacture in terms of yield and productivity, it is difficult to obtain the desired electron / hole mobility. Become. In addition, this catalytic CVD method
At present, there are many problems in the characteristics, quality, reliability, and the like of the formed film.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems in each of the above methods.
An object of the present invention is to provide a semiconductor film forming method for forming a high quality semiconductor film on a substrate. Another object of the present invention is to provide a method of manufacturing a thin film semiconductor device which can be applied to a high-quality and large-sized display device, a solid-state imaging device, and the like.
Still another object of the present invention is to provide a method of forming a semiconductor film and a thin film semiconductor device capable of forming a high-quality semiconductor film and manufacturing a thin film semiconductor device and obtaining sufficient electron / hole mobility. It is to provide a manufacturing method of.
Still another object of the present invention is to provide a method for forming a semiconductor film and a method for manufacturing a thin film semiconductor device, which can prevent deterioration of a thermal catalyst.

[0012]

According to the first aspect of the present invention, there is provided a method of forming a semiconductor film on a substrate by using a bias catalyst CVD or a high density bias catalyst CVD. Supplying at least a source gas to a vacuum container, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum container, and applying at least tin, germanium, and lead on the substrate. A semiconductor film forming step including forming a semiconductor film containing any one or more of the above, a laser annealing step of irradiating the formed semiconductor film with a laser and annealing the formed semiconductor film with a laser; , Is solved.

As described above, since an electric field equal to or lower than the glow discharge starting voltage is applied between the substrate and the electrode, the reaction species is accelerated by the above-described voltage in addition to the catalytic action of the catalyst and its thermal energy. Since an electric field is applied, the kinetic energy of the directivity increases, and the reactive species can be efficiently guided onto the substrate, and the electrophoresis on the substrate and the diffusion in the film during the generation process become sufficient. Therefore, the conventional catalyst CV
Compared with Method D, the kinetic energy and directivity of the reaction species generated by the catalyst can be controlled independently by the electric field, so that the adhesion of the generated film to the substrate, the density of the generated film, and the uniformity of the generated film are improved. Or, it is possible to improve the smoothness, improve the embedding property in via holes and the like, improve the step coverage, control the stress of the generated film, etc., improve the film formation speed, improve the productivity by using the raw material gas, etc., and realize a high quality film. I do. In addition, since the substrate temperature can be lowered, it becomes possible to adopt a low strain point glass and a heat resistant resin substrate,
Cost can be reduced.

In the present invention, since at least one of tin, germanium and lead is used, for example, even if tin, germanium or lead, which is a Group IV element, is mixed into the obtained silicon layer. These are elements of the fourth group of the periodic table and do not become carriers in the silicon layer, so that the silicon layer has a high resistance. Therefore, _Vth adjustment and resistance value adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin, germanium, and lead remaining in the silicon layer electrically inactivate crystal vacancies, so that the resulting silicon layer has reduced junction leakage and increased mobility. Also,
Since the crystal irregularities existing at the crystal grain boundaries are reduced and the stress of the film is reduced, the electron / hole mobility is increased, and the characteristics of the thin film transistor are improved.

Further, since a low-temperature process is made possible, an inexpensive low-strain-point glass substrate or a heat-resistant resin substrate can be used as the substrate. In addition, a long roll glass or a heat-resistant resin film substrate formed of low strain point glass can be used as the substrate.

Further, since the semiconductor film is configured to be annealed by a laser, only the semiconductor film is instantaneously heated, the influence of the heat on the substrate is hardly affected, and the substrate is not deformed, and The silicon or microcrystalline silicon semiconductor film can be crystallized, and the contained carrier impurities can be activated. For example, the semiconductor film can be changed to a semiconductor film having high mobility. In addition, the crystallization and activation can be performed at a low temperature without increasing the temperature of the entire substrate.

At this time, before the semiconductor film forming step,
Supply a carrier gas containing hydrogen to the vacuum vessel
And activated hydrogen gas generated by the supplied carrier gas.
On H ^*Cleaning on the substrate with
A cleaning step; and
It is preferable to perform the forming step.

As described above, since the carrier gas containing hydrogen is constantly supplied when the semiconductor film layer is formed on the substrate, the activated hydrogen ions H generated by the carrier gas are generated.
^* Can clean the substrate surface and form a high-quality semiconductor film on the substrate. Activated hydrogen ion H ^*
Cleaning becomes more effective by applying an electric field. In addition, a hydrogen gas as a carrier gas is supplied, and the thermal catalyst is heated to be in a catalysable state. When a film is continuously formed, at least the gate channel portion can be made low in stress and low in contamination. Furthermore, since the carrier gas containing hydrogen is constantly introduced during the film formation on the substrate, the thermal catalyst is protected from the influence of other gases, and the degradation of the thermal catalyst can be prevented.

The semiconductor film containing at least one of tin, germanium, and lead contains oxygen, carbon,
The smaller the content of nitrogen, the better the flow of carriers (electrons / holes), which is preferable. For example, each content of oxygen, carbon, and nitrogen in a semiconductor film such as a polysilicon film containing at least one of tin, germanium, and lead is 1 × 10 ¹⁹ atoms / cm.
³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and the hydrogen content is 0.01 atomic% / cm ^3.
Although the above is preferable, the present invention achieves the above numerical values because the semiconductor film is efficiently exposed to activated hydrogen ions H ^* during film formation by application of an electric field, thereby reducing oxidation and contamination of the semiconductor film. It is possible to do.

Further, before the semiconductor film forming step, a carrier gas containing hydrogen is supplied to the vacuum vessel, and the substrate is cleaned with activated hydrogen ions H ^* generated by the supplied carrier gas. And supplying the carrier gas before the semiconductor film forming step.
It is preferable to perform the step of increasing or decreasing at least one in the middle or later and the step of forming the semiconductor film.

With this, when performing various types of film formation, the introduction of the carrier gas can be reduced after a lapse of a predetermined time from the start of the film formation. Semiconductor film formation is performed at high speed, and workability can be improved. In addition, since a carrier gas containing hydrogen is supplied when a semiconductor film is formed on a substrate, activated hydrogen ions H ^* generated by the thermal catalyst clean the surface of the substrate and form a high-quality semiconductor on the substrate. A film can be formed. Further, a hydrogen gas is supplied as a carrier gas, and the thermal catalyst is heated so as to be capable of catalysis. When a film is continuously formed, at least the gate channel portion can be made low in stress and low in contamination.

In addition, when various types of film formation are performed, the introduction of the carrier gas can be increased before and after the semiconductor film formation step. Therefore, before and after the film formation, the activated hydrogen ions H * are activated by the thermal catalyst. Can be generated in a large amount to promote contamination reduction, film stress reduction, and the like by cleaning. At this time, since the electrolysis is applied, these effects can be obtained efficiently. In addition, oxygen, carbon, and the like at the interface of the semiconductor film such as the polysilicon film with the insulating film.
The smaller the content of each nitrogen, the lower the carrier (electron /
The flow of holes) becomes favorable, which is preferable. For example, at least the content of each of oxygen, carbon, and nitrogen in a semiconductor film such as a polysilicon film in a carrier channel region is 1 × 1.
0 ¹⁹ atoms / cm ³ or less, preferably 5 × 10
^{At 18} atoms / cm ³ or less, the hydrogen content is less than 0.1 atom / cm ³ .
Although it is preferable that the concentration is not less than 01 atomic% / cm ³ , in the present invention, a hydrogen gas is introduced before the semiconductor film forming step, and activated hydrogen ions H ^* are caused to act efficiently by applying an electric field. Therefore, this numerical value can be achieved.

Further, the semiconductor film forming step is performed in a film forming chamber in the vacuum vessel, and the laser annealing step is performed in a laser annealing chamber in the vacuum vessel, and the semiconductor film forming step and the laser annealing step are performed. It may be performed continuously in the vacuum vessel. With such a configuration, the semiconductor film forming step and the laser annealing step can be continuously performed without taking out from the vacuum apparatus, and a thin film semiconductor device or the like can be manufactured by simpler steps.

In the film forming chamber, an insulating film is formed on the semiconductor film annealed with the laser, and the semiconductor film forming step, the laser annealing step, and the forming of the insulating film are performed in the vacuum chamber. It is also preferable that the configuration is such that the processing is performed continuously within the processing. With this configuration, the semiconductor film forming step, the laser annealing step, and the formation of the insulating film can be continuously performed without taking out from the vacuum apparatus, and the thin film semiconductor device and the like can be manufactured by simpler steps. It becomes possible.

According to a sixth aspect of the present invention, there is provided a semiconductor film forming method for forming a semiconductor film on a substrate by using a bias catalytic CVD or a high density bias catalytic CVD. At least a raw material gas is supplied to the container, and an electric field equal to or lower than a glow discharge starting voltage is applied between the substrate and the electrode arranged in the vacuum container, so that at least tin, germanium, or lead A semiconductor film containing at least one of the above, an insulating film, and a semiconductor film and insulating film forming step including forming the semiconductor film and the insulating film, and irradiating the formed semiconductor film and the insulating film with a laser; A laser annealing step of annealing the film and the insulating film with a laser.

As described above, since an electric field equal to or lower than the glow discharge starting voltage is applied between the substrate and the electrode, the reaction species is accelerated by the above-described voltage in addition to the catalytic action of the catalyst and its thermal energy. Since the electric field is applied, the kinetic energy of the directivity increases, and the reactive species can be efficiently guided onto the substrate, and the migration on the substrate and the diffusion in the film during the generation process become sufficient. Therefore, as compared with the conventional catalytic CVD method, the kinetic energy and directivity of the reaction species generated by the catalyst body can be independently controlled by the electric field,
It is possible to improve the adhesion of the generated film to the substrate, increase the density of the generated film, improve the uniformity or smoothness of the generated film, improve the embedding into via holes and the like, improve the step coverage, and control the stress of the generated film. Higher productivity and higher quality film can be realized by improving the speed and the utilization efficiency of raw material gas. Further, since the substrate temperature can be lowered, low strain point glass and a heat resistant resin substrate can be employed, and cost reduction can be achieved.

Further, in the present invention, since at least one of tin, germanium and lead is used, for example, tin, germanium and lead which are Group 4 elements are mixed in the obtained silicon layer. However, these are elements of Group 4 of the periodic table and do not become carriers in the silicon layer, so that the silicon layer has a high resistance. Therefore, _Vth adjustment and resistance value adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin, germanium, and lead remaining in the silicon layer electrically inactivate crystal vacancies, so that the resulting silicon layer has reduced junction leakage and increased mobility.
In addition, since the crystal irregularities existing at the crystal grain boundaries are reduced and the stress of the film is reduced, the electron / hole mobility is increased, and the characteristics of the thin film transistor are improved.

As a result, a low-temperature process can be performed, so that an inexpensive low-strain-point glass substrate or a heat-resistant resin substrate can be used as the substrate. In addition, a long roll glass or a heat-resistant resin film substrate formed of low strain point glass can be used as the substrate.

Further, since the semiconductor film is configured to be annealed with a laser, only the semiconductor film is instantaneously heated, the influence of the heat on the substrate is hardly affected, and the substrate is not deformed. A silicon or microcrystalline silicon semiconductor film can be crystallized, and a contained carrier impurity can be activated. For example, a semiconductor film having high mobility can be changed. In addition, the crystallization and activation can be performed at a low temperature without increasing the temperature of the entire substrate.

At this time, it is preferable that the laser annealing step is performed in a laser annealing apparatus different from the vacuum vessel. Further, a semiconductor film and an insulating film forming step is performed in a film forming chamber in the vacuum vessel, and the laser annealing step is performed in a laser annealing chamber in the vacuum vessel, and the semiconductor film and insulating film forming step and the laser annealing step are performed. May be continuously performed in the vacuum vessel.

Further, a semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the laser film is formed in a laser annealing chamber in the vacuum vessel. Preferably, an annealing step is performed, and the formation of the semiconductor film, the formation of the insulating film, and the laser annealing step are sequentially performed in the vacuum vessel.

In the step of forming the semiconductor film or the step of forming the semiconductor film and the insulating film, the concentration of each of oxygen, carbon and nitrogen in at least the carrier channel region in the semiconductor film is 1 × 10 ¹⁹ at.
oms / cm ³ or less, hydrogen concentration of 0.01 atomic% / cm
³ or more at which the semiconductor film is formed, the laser annealing step, the semiconductor film by laser annealing, oxygen in at least the carrier channel region of the semiconductor film, carbon, each concentration of ¹ × 10 1 ⁹ ato nitrogen
ms / cm ³ or less, hydrogen concentration is 0.01 atomic% / cm ³
It is preferable to use the above semiconductor film.

In the case where the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD, the semiconductor film is used as the semiconductor film in the semiconductor film forming step or the semiconductor film and the insulating film forming step. Each concentration of oxygen, carbon, and nitrogen in at least the carrier channel region in the film is 1
× 10 ¹⁹ atoms / cm ³ or less, hydrogen concentration of 0.0
Forming a semiconductor film having a concentration of 1 atomic% / cm ³ or more, and performing the laser annealing on the semiconductor film in the laser annealing step so that the respective concentrations of oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film are reduced; 1 ×
10 ¹⁹ atoms / cm ³ or less, hydrogen concentration 0.01
It is preferable that the thickness of the semiconductor film be at least atomic% / cm ³ .

As described above, since the respective concentrations of oxygen, carbon, and nitrogen at least in the carrier channel region in the semiconductor film are 1 × 10 ¹⁹ atoms / cm ³ or less, the flow of carriers (electrons and holes) is good. Thus, there is no hysteresis in the gate voltage / drain current characteristics, and good switching characteristics can be obtained at high frequencies. Further, the hydrogen concentration in at least the carrier channel region in the semiconductor film is set to 0.01 atomic% / c.
Since the m ³ or more, it is possible to increase the conductivity of the carrier channel region.

According to a twelfth aspect of the present invention, there is provided a semiconductor film forming method for forming a semiconductor film on a substrate by utilizing a bias catalytic CVD or a high density bias catalytic CVD. Supplying at least a source gas to the container, applying an electric field equal to or less than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum container,
On the substrate, at least tin, germanium, a semiconductor film containing at least one of lead, an insulating film, and a semiconductor film and insulating film forming step including forming an insulating film, the formed semiconductor film and And a steam annealing step of annealing the insulating film with steam.

As described above, since an electric field equal to or lower than the glow discharge starting voltage is applied between the substrate and the electrode, the reaction species is accelerated by the above-described voltage in addition to the catalytic action of the catalyst and its thermal energy. Since an electric field is applied, the kinetic energy of the directivity increases, and the reactive species can be efficiently guided onto the substrate, and the electrophoresis on the substrate and the diffusion in the film during the generation process become sufficient. Therefore, the conventional catalyst CV
Compared with Method D, the kinetic energy and directivity of the reaction species generated by the catalyst can be controlled independently by the electric field, so that the adhesion of the generated film to the substrate, the density of the generated film, and the uniformity of the generated film are improved. Or, it is possible to improve the smoothness, improve the embedding property in via holes and the like, improve the step coverage, control the stress of the generated film, etc., improve the film formation speed, improve the productivity by using the raw material gas, etc., and realize a high quality film. I do. In addition, since the substrate temperature can be lowered, it becomes possible to adopt a low strain point glass and a heat resistant resin substrate,
Cost can be reduced.

In order to perform the steam annealing step,
The semiconductor and the insulating film can be effectively modified by the heat treatment at a low temperature of 00 ° C. or less. In addition, by modifying the insulating film, that is, reducing water and OH groups in the insulating film, an effect of suppressing hot electron deterioration of the gate insulating film or the semiconductor film can be obtained.

By reducing water and OH groups in the insulating film, hot electron degradation is suppressed in, for example, a gate insulating film. Further, since a positive charge caused by a defect or an impurity in the gate insulating film is neutralized and a negative flat band voltage can be brought closer to the 0 V side, n-
The shift to the depletion type in the channel MIS transistor is avoided to be the enhancement type, and the p-ch
In the MIS transistor, a reliable operation can be performed while avoiding an increase in the threshold voltage _Vth , so that an integrated circuit such as a CMOS can be easily formed. Since variations in element characteristics in the same semiconductor substrate can be reduced, circuit integration is easy. Further, the effect of improving the interface characteristics between the semiconductor and the insulating film, that is, lowering the threshold voltage _Vth to increase the on-current and reducing the off-current, is obtained.
High-speed operation of the integrated circuit can be realized. In addition, an increase in carrier mobility can be expected.

At this time, it is preferable to perform the steam annealing step in a steam annealing apparatus different from the vacuum vessel. With this configuration, it is possible to prevent the inside of the vacuum vessel from being deteriorated by water vapor. Further, when a thermal catalyst that is easily oxidized and deteriorated by the presence of oxygen is used, it is possible to prevent the thermal catalyst from being oxidized and deteriorated by steam.

Further, a semiconductor film and an insulating film forming step is performed in a film forming chamber in the vacuum vessel, and the steam annealing step is performed in a steam annealing chamber in the vacuum vessel. The steam annealing step may be performed continuously in the vacuum vessel. With this configuration, the semiconductor film and insulating film forming step and the steam annealing step can be performed continuously without taking out from the vacuum apparatus, and the thin film semiconductor device and the like can be manufactured with a simpler process and with high productivity. It is possible to do.

Further, a semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the steam is formed in a steam annealing chamber in the vacuum vessel. Preferably, an annealing step is performed, and the formation of the semiconductor film, the formation of the insulating film, and the water vapor annealing step are sequentially performed in the vacuum vessel.

In the step of forming the semiconductor film and the insulating film,
As the semiconductor film, a semiconductor in which the concentration of each of oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less and the hydrogen concentration is 0.01 atom% / cm ³ or more. A film is formed, and in the steam annealing step, the semiconductor film is steam-annealed so that at least the concentration of oxygen, carbon, and nitrogen in at least the carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less. It is preferable that the semiconductor film has a hydrogen concentration of 0.01 atomic% / cm ³ or more.

In the case where the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD, the semiconductor film is used as the semiconductor film in the semiconductor film forming step or the semiconductor film and the insulating film forming step. Each concentration of oxygen, carbon, and nitrogen in at least the carrier channel region in the film is 1
× 10 ¹⁹ atoms / cm ³ or less, hydrogen concentration of 0.0
Forming a semiconductor film having a concentration of 1 atomic% / cm ³ or more, and performing the water vapor annealing on the semiconductor film in the water vapor annealing step, so that each concentration of oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film is 1 × 10
It is preferable that the semiconductor film has a thickness of ¹⁹ atoms / cm ³ or less and a hydrogen concentration of 0.01 atom% / cm ³ or more.

As described above, since the respective concentrations of oxygen, carbon, and nitrogen at least in the carrier channel region in the semiconductor film are set to 1 × 10 ¹⁹ atoms / cm ³ or less, the flow of carriers (electrons and holes) is good. Thus, there is no hysteresis in the gate voltage / drain current characteristics, and good switching characteristics can be obtained at high frequencies. Further, the hydrogen concentration in at least the carrier channel region in the semiconductor film is set to 0.01 atomic% / c.
Since the m ³ or more, it is possible to increase the conductivity of the carrier channel region.

When the semiconductor film is single crystal silicon, it is preferable that a step is formed at least in the silicon film formation region, and a single crystal silicon film is grown by grapho-epitaxial growth in the silicon film formation region including the step. That is, since a step is provided on the substrate and a single crystal silicon film is grapho-epitaxially grown on the substrate including the step, a single crystal semiconductor film having high electron / hole mobility and excellent operability can be obtained. it can.

When the semiconductor film is single crystal silicon, a material layer having good lattice matching with the single crystal semiconductor is formed at least in the silicon film formation region, and the single crystal silicon film is heterogeneously formed in the silicon film formation region including the material layer. It is preferable that the epitaxial growth is performed. This allows
A single crystal silicon film having high electron / hole mobility and excellent operability can be obtained.

At this time, the material layer having good lattice matching with the single crystal silicon may be formed of at least one material selected from the group including sapphire or spinel structure or calcium fluoride.

According to a twenty-first aspect of the present invention, there is provided a semiconductor film forming method for forming a semiconductor film on a substrate by using bias catalytic CVD or high-density bias catalytic CVD. Supplying at least a source gas to the container, applying an electric field equal to or less than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum container,
On the substrate, at least tin, germanium, a semiconductor film containing at least one of lead, an insulating film, and a semiconductor film and insulating film forming step including forming an insulating film, the formed semiconductor film and Irradiate the insulating film with a laser,
This problem is solved by providing a laser annealing step of annealing the formed semiconductor film and insulating film with a laser, and a steam annealing step of annealing after the laser annealing step with steam.

As described above, since an electric field equal to or less than the glow discharge starting voltage is applied between the substrate and the electrode, the reaction species is accelerated by the above-mentioned voltage in addition to the catalytic action of the catalyst and its thermal energy. Since an electric field is applied, the kinetic energy of the directivity increases, and the reactive species can be efficiently guided onto the substrate, and the electrophoresis on the substrate and the diffusion in the film during the generation process become sufficient. Therefore, the conventional catalyst CV
Compared with Method D, the kinetic energy and directivity of the reaction species generated by the catalyst can be controlled independently by the electric field, so that the adhesion of the generated film to the substrate, the density of the generated film, and the uniformity of the generated film are improved. Or, it is possible to improve the smoothness, improve the embedding property in via holes and the like, improve the step coverage, control the stress of the generated film, etc., improve the film formation speed, improve the productivity by using the raw material gas, etc., and realize a high quality film. I do. In addition, since the substrate temperature can be lowered, it becomes possible to adopt a low strain point glass and a heat resistant resin substrate,
Cost can be reduced. Further, by using the bias catalyst CVD, the source gas introduced into the vacuum vessel can be efficiently formed as a thin film.

If the laser annealing step and the water vapor annealing step are performed after the semiconductor film is formed, for example, when the amorphous silicon film or the microcrystalline silicon film is used as the semiconductor film, polysilicon having a large grain size is used in the laser annealing step. By forming a film, a polysilicon film having high mobility can be formed. As described above, since the laser annealing step and the steam annealing step are performed after the semiconductor film forming step, the semiconductor film can be effectively modified by a low-temperature heat treatment.

At this time, before the step of forming the semiconductor film and the insulating film, a carrier gas containing hydrogen is always supplied to the vacuum container, and the activated hydrogen ions H ^* generated by the supplied carrier gas are used to supply the substrate with the activated hydrogen ions H ^*. It is preferable to provide a cleaning step of cleaning the upper part, and to perform the cleaning step and the semiconductor film and insulating film forming step.

As described above, since the carrier gas containing hydrogen is constantly supplied when the semiconductor film layer is formed on the substrate, the activity generated by the thermal decomposition and catalytic reaction of the thermal catalyst from the hydrogen-based carrier gas. Hydrogen hydride ions H ^* are efficiently collected on the substrate by applying an electric field equal to or lower than the glow discharge starting voltage, the substrate surface can be efficiently cleaned, and a high quality semiconductor film can be formed on the substrate. In addition, a hydrogen gas as a carrier gas is supplied, and the thermal catalyst is heated so as to be capable of catalysis, and a plurality of films are continuously formed to form a specific film such as a silicon film and a gate insulating film. For example, when a film is continuously formed, the gate channel portion can have low stress and low contamination. Furthermore, since the carrier gas containing hydrogen is constantly introduced during the film formation on the substrate, the thermal catalyst is protected from the influence of other gases, and the degradation of the thermal catalyst can be prevented. Also,
In the case of using a thermal catalyst which is easily oxidized and degraded due to the presence of oxygen, for example, a thermal catalyst having a high melting point metal (tungsten, tungsten containing thoria, tantalum, molybdenum, silicon, etc.) exposed on the surface, the residual oxygen Oxidation degradation of the thermal catalyst can be reduced.

Further, before the step of forming the semiconductor film and the insulating film, a carrier gas containing hydrogen is supplied to the vacuum vessel, and activated hydrogen ions H ^* generated by the supplied carrier gas are applied on the substrate. A cleaning step of cleaning, a step of increasing or decreasing the supply of the carrier gas at least one before, during, or after the step of forming the semiconductor film and the insulating film; and a step of forming the semiconductor film and the insulating film. May be configured.

Thus, when performing various film formations, the introduction of the carrier gas can be reduced or stopped depending on the type of the catalyst 5 after a predetermined time has elapsed after the start of the film formation. Since the ratio of the gas is increased, the semiconductor film is formed on the substrate at a high speed, and the workability can be improved. In addition, since a carrier gas containing hydrogen is supplied when a semiconductor film is formed on a substrate, activated hydrogen ions H ^* generated by the thermal catalyst clean the surface of the substrate and form a high-quality semiconductor on the substrate. A film can be formed. Further, a hydrogen gas as a carrier gas is supplied, and the thermal catalyst is heated so as to be capable of catalysis, and a plurality of films are continuously formed to form a specific film, for example, a silicon film and a gate insulating film. For example, when a film is continuously formed, the gate channel portion can have low stress and low contamination.

When various types of film are formed, a semiconductor film type
Increase carrier gas introduction before and after the forming process
Activated hydrogen ions generated by the carrier gas
H ^*Cleans the substrate surface and provides high quality
A semiconductor film can be formed. Also carrier gas
Hydrogen gas, and heat the thermal catalyst to
In a state where medium action is possible, multiple films are continuously formed.
A specific film, for example, a silicon film and a gate insulating film
If a film is formed, lower the gate channel area
And low contamination. In addition, hydrogen
Carrier gas is constantly introduced during the deposition of the substrate
This protects the thermal catalyst from the effects of other gases.
Deterioration of the thermal catalyst can be prevented.

When a polysilicon film containing at least one of tin, germanium and lead is formed by bias catalytic CVD, the content of oxygen, carbon and nitrogen in the polysilicon film is reduced. The smaller the amount, the better the flow of carriers (electrons / holes), which is preferable. For example, the oxygen in the semiconductor film of the polysilicon film or the like at least a carrier channel region, the carbon content of each ^{nitrogen, 1 × 10 1 9 atoms /} cm 3 or less, preferably 5 × ¹⁰ 18 atoms / cm ³ or less Is preferable, and the hydrogen content is 0.01 atomic% / cm.
^Although it is preferable that the number is ³ or more, in the present invention, by introducing a hydrogen gas, the semiconductor film is constantly exposed to activated hydrogen ions H ^* efficiently by applying an electric field during film formation, so that oxidation and contamination of the semiconductor film are reduced. Therefore, the above numerical values can be achieved. Further, it is preferable that the numerical value is maintained even after performing the laser annealing treatment. However, in the present invention, since the hydrogen gas is introduced and the electric field is applied,
This value can be achieved even after laser annealing.

According to the present invention, the activation hydrogen ions H are always efficiently supplied during the film formation by introducing hydrogen gas and applying an electric field.
Because it is exposed to ^*, at least tin, germanium, even when forming a single crystal silicon film containing one or more of lead, it is possible to achieve the above values by epitaxial growth or the like. Further, in the present invention,
Due to the introduction of hydrogen gas and the application of an electric field, the amorphous silicon film or the microcrystalline silicon film containing at least one of tin, germanium, and lead is always efficiently exposed to activated hydrogen ions H ^* during film formation. This numerical value can be achieved even when a large-grain polysilicon film is obtained by forming these films and performing laser annealing on these films, or after laser annealing. In particular, in the case of the MISFT, it is desired that the above numerical value is achieved at the interface between the polysilicon film serving as the channel region and the gate insulating film. The oxygen content at the interface can be set to the above value.

Further, it is preferable that the laser annealing step is performed in a laser annealing apparatus different from the vacuum vessel, and the steam annealing step is performed in a steam annealing apparatus different from the vacuum vessel.

A semiconductor film and insulating film forming step is performed in a film forming chamber in the vacuum vessel, the laser annealing step is performed in a laser annealing chamber in the vacuum vessel, and the steam annealing is performed in a steam annealing chamber in the vacuum vessel. And a step of forming the semiconductor film and the insulating film, the laser annealing step, and the water vapor annealing step may be sequentially performed in the vacuum vessel.

Further, a semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the laser film is formed in a laser annealing chamber in the vacuum vessel. Performing an annealing step, performing the steam annealing step in a steam annealing chamber in the vacuum vessel, and continuously forming the semiconductor film, the insulating film, the laser annealing step, and the steam annealing step in the vacuum vessel. It is preferable that the configuration is such that the operation is performed.

With such a configuration, the formation of the semiconductor film, the formation of the insulating film, the laser annealing step and the steam annealing step can be continuously performed without taking out from the vacuum apparatus, and the simpler steps can be performed. It becomes possible to manufacture a thin film semiconductor device and the like.

In the step of forming the semiconductor film and the insulating film,
Represents at least a key in the semiconductor film as the semiconductor film.
Of oxygen, carbon and nitrogen in the carrier channel region
Each concentration is 1 × 10¹⁹atoms / cm³Below, water
Elemental concentration is 0.01 atomic% / cm³The above semiconductor film
And forming the semiconductor film in the steam annealing step.
By steam annealing, at least the carrier in the semiconductor film is
Oxygen, carbon and nitrogen in the channel region
Concentration of 1 × 10¹⁹atoms / cm³Below, hydrogen concentration
The degree is 0.01 atomic% / cm³With the above semiconductor film,
In the laser annealing step, the semiconductor film is
Neal, at least a carrier channel in the semiconductor film.
The concentration of oxygen, carbon, and nitrogen in the tunnel region
1 × 10 ¹⁹atoms / cm³Hereinafter, when the hydrogen concentration is 0.
01 atomic% / cm³It is preferable to use the above semiconductor film.
You.

In the case where the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD, the semiconductor film is used as the semiconductor film in the semiconductor film forming step or the semiconductor film and the insulating film forming step. Each concentration of oxygen, carbon and nitrogen in at least the carrier channel region in the film is 1
× 10 ¹⁹ atoms / cm ³ or less, hydrogen concentration of 0.0
A semiconductor film having a concentration of 1 atomic% / cm ³ or more is formed, and in the steam annealing step, the semiconductor film is steam-annealed so that the concentration of each of oxygen, carbon, and nitrogen in at least the carrier channel region of the semiconductor film is 1; × 10
A semiconductor film having a density of ¹⁹ atoms / cm ³ or less and a hydrogen concentration of 0.01 atomic% / cm ³ or more, and performing the laser annealing on the semiconductor film in the laser annealing step so that oxygen in at least a carrier channel region in the semiconductor film is formed; , Carbon, and nitrogen each have a concentration of 1 × 10 ^{19 at}
ms / cm ³ or less, hydrogen concentration is 0.01 atomic% / cm ³
It is preferable to use the above semiconductor film.

As described above, since the respective concentrations of oxygen, carbon, and nitrogen in at least the carrier channel region in the semiconductor film are set to 1 × 10 ¹⁹ atoms / cm ³ or less, the flow of carriers (electrons and holes) is good. Thus, there is no hysteresis in the gate voltage / drain current characteristics, and good switching characteristics can be obtained at high frequencies. Further, the hydrogen concentration in at least the carrier channel region in the semiconductor film is set to 0.01 atomic% / c.
Since the m ³ or more, it is possible to increase the conductivity of the carrier channel region.

In the above case, it is preferable that the bias catalyst CVD or the high-density bias catalyst CVD is bias reduced pressure CVD or bias normal pressure CVD.

According to a thirty-first aspect of the present invention, there is provided a method for manufacturing a top gate type TFT by using a bias catalyst CVD or a high-density bias catalyst CVD, wherein at least a raw material is contained in a vacuum vessel. A gas is supplied, and an electric field equal to or lower than a glow discharge starting voltage is applied between the substrate and the electrode arranged in the vacuum vessel, so that a protective film, at least tin, A semiconductor film containing at least one of germanium and lead;
A gate insulating film and a polycrystalline semiconductor film formed continuously,
After that, the problem is solved by subjecting the semiconductor film to a laser annealing treatment and then forming a source / top gate / drain electrode. With such a configuration, the performance of the thin-film semiconductor device can be improved and the manufacturing thereof can be facilitated.

Further, according to the present invention, there is provided a method of manufacturing a bottom gate type TFT by using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate type TFT is formed on a substrate. Forming an electrode, supplying at least a raw material gas to a vacuum vessel, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a bottom in the vacuum vessel. A protective film on the gate electrode, a bottom gate insulating film,
A semiconductor film containing at least one of tin, germanium, and lead and a protective film are continuously formed, and thereafter, the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. The problem is solved by forming a drain electrode.

According to a thirty-second aspect of the present invention, there is provided a method of manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate TFT is formed on a substrate. Forming an electrode, supplying at least a raw material gas to a vacuum vessel, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a bottom in the vacuum vessel. A protective film on the gate electrode, a bottom gate insulating film,
A semiconductor film containing at least one of tin, germanium and lead and a top gate insulating film are continuously formed, and then the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. / Top gate /
The problem is solved by forming a drain electrode.

At the time of the above, it is preferable that the laser annealing is performed in a laser annealing apparatus different from the vacuum vessel. Further, the semiconductor film and the insulating film are formed in a film forming chamber in the vacuum vessel, and the laser annealing is performed in a laser annealing chamber in the vacuum vessel,
The semiconductor film and the insulating film may be formed and the laser annealing process may be continuously performed in the vacuum vessel.

Further, the semiconductor film is formed in the semiconductor film forming chamber in the vacuum vessel, the insulating film is formed in the insulating film forming chamber in the vacuum vessel, and the laser annealing chamber in the vacuum vessel is formed. It is preferable that the laser annealing process is performed in such a manner that the formation of the semiconductor film, the formation of the insulating film, and the laser annealing process are continuously performed in the vacuum vessel.

According to a thirty-sixth aspect of the present invention, there is provided a method of manufacturing a top gate type TFT by using a bias catalyst CVD or a high density bias catalyst CVD, wherein at least a raw material is contained in a vacuum vessel. Supplying a gas, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a protective film on the substrate in the vacuum vessel; A semiconductor film containing at least one of, germanium, and lead, and a gate insulating film are continuously formed.
The problem is solved by forming a top gate / drain electrode, then performing a steam annealing process at a low pressure or a high temperature or a high pressure and a high temperature, and then performing plasma cleaning or sputter cleaning of the source / top gate / drain electrode.

Further, according to the present invention, there is provided a method of manufacturing a bottom gate type TFT by using a bias catalytic CVD or a high density bias catalytic CVD, wherein a bottom gate type TFT is formed on a substrate. Forming electrodes,
At least a source gas is supplied to a vacuum vessel, and an electric field equal to or lower than a glow discharge starting voltage is applied between the substrate and the electrode disposed in the vacuum vessel, so that the electric field is protected on the bottom gate electrode in the vacuum vessel. A film, a bottom gate insulating film, a semiconductor film containing at least one of tin, germanium and lead, and a protective film are successively formed, and then a source / drain electrode is formed. The problem can be solved by performing a steam annealing process at a high temperature or a high pressure and a high temperature, and then performing a plasma cleaning or a sputter cleaning of the bottom gate electrode and the source / drain electrodes.

According to a thirty-eighth aspect of the present invention, there is provided a method of manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate TFT is formed on a substrate. Forming an electrode, supplying at least a raw material gas to a vacuum vessel, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a bottom in the vacuum vessel. A protective film on the gate electrode, a bottom gate insulating film,
A semiconductor film containing at least one of tin, germanium and lead and a top gate insulating film are successively formed, and then a source / top gate / drain electrode is formed. The above problem can be solved by performing a steam annealing process and then performing plasma cleaning or sputter cleaning of the bottom gate electrode and the source / top gate / drain electrodes.

According to a thirty-ninth aspect of the present invention, there is provided a method of manufacturing a top-gate type TFT by using a bias catalyst CVD or a high-density bias catalyst CVD, wherein at least a raw material is contained in a vacuum container. Supplying a gas, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a protective film, at least tin, A semiconductor film containing at least one of germanium and lead;
And a gate insulating film are continuously formed, and thereafter, the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film, and then a source / top gate / drain electrode is formed. The problem is solved by performing a process, and then performing plasma cleaning or sputter cleaning of the source / top gate / drain electrodes.

Further, according to the present invention, there is provided a method of manufacturing a bottom gate type TFT by using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate type TFT is formed on a substrate. Forming electrodes,
At least a source gas is supplied to a vacuum vessel, and an electric field equal to or lower than a glow discharge starting voltage is applied between the substrate and the electrode arranged in the vacuum vessel, so that the electric field is protected on the bottom gate electrode in the vacuum vessel. A film, a bottom gate insulating film, a semiconductor film containing at least one of tin, germanium, and lead, and a protective film are successively formed. By forming a crystalline semiconductor film, then forming source / drain electrodes, and then performing low-temperature high-temperature or high-pressure high-temperature steam annealing treatment, and then performing plasma cleaning or sputter cleaning of the bottom gate electrode and the source / drain electrodes. Will be resolved.

Further, according to the present invention, there is provided a method for manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate TFT is formed on a substrate. Forming an electrode, supplying at least a raw material gas to a vacuum vessel, applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode disposed in the vacuum vessel, and forming a bottom in the vacuum vessel. A protective film on the gate electrode, a bottom gate insulating film,
A semiconductor film containing at least one of tin, germanium and lead and a top gate insulating film are continuously formed, and then the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. / Top gate /
The problem is solved by forming a drain electrode and then performing a steam annealing process at a low pressure and a high temperature or a high pressure and a high temperature, and then performing plasma cleaning or sputter cleaning of the bottom gate electrode and the source / top gate / drain electrode. .

In the above case, it is preferable that the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD.

A cleaning step of constantly supplying a carrier gas containing hydrogen to the vacuum vessel and cleaning the substrate with activated hydrogen ions H ^* generated by the supplied carrier gas is provided. It is preferable that the film and the cleaning step are repeated, or the film formation of the film is repeated after the cleaning step.

A cleaning step of supplying a carrier gas containing hydrogen to the vacuum vessel and cleaning the substrate with activated hydrogen ions H ^* generated by the supplied carrier gas; It is preferable that the step of increasing or decreasing at least one of before, during and after the formation of the film and the formation of the film be performed.

[0080]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of a method for forming a semiconductor film and a method for manufacturing a thin film semiconductor device according to the present invention will be described with reference to the drawings. In FIGS. 10 to 16 and 21, argon is Ar and silicon is S
i, H _{2 for} hydrogen gas, O ₂ for oxygen gas, N _{2 for} nitrogen gas, NH _{3 for} ammonia gas, and Si for silane gas
H ₄ , helium gas is He, neon gas is Ne, silicon nitride is SiN, and silicon oxide is SiO ₂ . The present invention relates to a bias catalyst CVD or a high density bias catalyst C.
This is a semiconductor film forming method for forming a semiconductor film on the substrate 10 using VD.

The bias catalytic CVD is a method for performing catalytic CVD by applying an electric field. In the bias catalytic CVD, a reactive gas composed of a hydrogen-based carrier gas and a source gas such as a silane gas is brought into contact with a heated catalyst such as tungsten based on the catalytic CVD method, and a radical deposition species or a radical deposition species generated thereby is produced. An electric field equal to or lower than the glow discharge starting voltage is applied to the precursor and the activated hydrogen ions H ^* to give directional kinetic energy, and a predetermined film such as polycrystalline silicon is vapor-phase grown on the substrate. The radical deposition species or the precursor thereof and the activated hydrogen ions H ^* are applied between the substrate and the counter electrode by a DC voltage equal to or lower than a glow discharge starting voltage,
Alternatively, the light is directed toward the substrate by applying a voltage obtained by superimposing an AC voltage on a DC voltage.

Catalytic CVD (Catalytic CV)
D, CAT-CVD) is described, for example, in JP-A-63-40.
No. 314, for example. Catalyst C
In the VD method, silicon atoms or a group of atoms having high energy are formed by a catalytic reaction or a thermal decomposition reaction by a thermal catalyst and deposited on an insulating substrate.
The silicon film can be deposited in a low temperature region that is significantly lower than the deposition possible temperature in the VD method.

The high-density catalytic CVD is a combination of high-density plasma CVD and catalytic CVD as appropriate.
This high-density plasma CVD is based on plasma CVD.
This is performed by activating the source gas in a plasma having a high density by microwaves under a low pressure of 10 ⁻³ Pa level. As a high-density plasma CVD apparatus, basically the apparatus described in this specification can be used, but ECR (El) using microwaves (about 2.45 GHz) can be used.
electron Cyclotron Resonac
e), ICP (In) using RF (13.56 MHz)
ductile Coupled Plasm
a) Generate high-density plasma in the chamber using helicon wave plasma or the like. Therefore, since a high vacuum is required, a turbo molecular pump is used as a vacuum pump, a high bias voltage is applied from the substrate side, and an electrostatic chuck and a cooling means (for example, He) are used for cooling.

High-density bias catalytic CVD used in the present invention
Is for increasing the density of plasma by microwaves. An apparatus for performing high-density bias catalytic CVD will be briefly described. In a high-density bias catalytic CVD apparatus, an electrode and a substrate are arranged in a vacuum container in parallel, and a waveguide is provided on a side wall of the vacuum container, that is, a wall perpendicular to the electrode and the substrate. The waveguide extends perpendicular to the side wall, and the waveguide is provided with a magnetron. In high-density bias catalytic CVD, the waveguide is configured to generate microwave plasma. With such a configuration, unlike RF plasma CVD or the like, in which the substrate is affected by plasma because an electric field is applied between the susceptor and the electrode to generate plasma, the high-density bias catalytic CVD does not The plasma generated in the wave tube hits the wall of the vacuum vessel and weakens, and the substrate is less likely to be damaged by the microwave plasma. In addition, when the waveguide is provided at a position between the electrode and the substrate on the side wall of the vacuum vessel, the thermal catalyst between the electrode and the substrate reduces the plasma from reaching the substrate, Are less susceptible to damage by microwave plasma. In the case where the electrode is provided far from the substrate outside the electrode on the side wall of the vacuum vessel, the plasma reaches the substrate by the thermal catalyst and the electrode, and the substrate is damaged by the microwave plasma. It is hard to receive.

In the present invention, at least the raw material gas is supplied to the vacuum vessel 1, and an electric field equal to or lower than the glow discharge starting voltage is applied between the substrate 10 and the electrode 3a arranged in the vacuum vessel 1 to apply the electric field to the substrate. A semiconductor film forming step including forming a semiconductor film containing at least one of tin, germanium, and lead, and irradiating the formed semiconductor film with a laser, and forming the formed semiconductor film with a laser. Laser annealing for annealing. The semiconductor film is, for example, an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film. Thus, the substrate 10 and the electrode 3a
Since an electric field equal to or lower than the glow discharge starting voltage is applied to the reaction species, an accelerating electric field is applied to the reactive species by the above-described voltage in addition to the catalytic action of the catalyst body 5 and its thermal energy. The energy is increased and the energy can be efficiently guided on the substrate, and the migration in the substrate and the diffusion in the film during the generation process are sufficient. Therefore, the conventional catalyst CV
Compared with Method D, the kinetic energy and directivity of the reaction species generated by the catalyst body 5 can be independently controlled by an electric field, so that the adhesion of the generated film to the substrate 10 is improved, and the density of the generated film is improved. In addition, the uniformity and smoothness of the formed film are improved. In addition, the embedding property into a via hole and the like and the step coverage are improved, the stress control of the generated film becomes possible, and a high quality film is realized. Further, since the substrate temperature can be lowered, low strain point glass and a heat resistant resin substrate can be employed, and cost reduction can be achieved.

A DC voltage lower than the glow discharge starting voltage or a voltage obtained by superimposing an AC voltage on the DC voltage is applied between the substrate 10 and the electrode 3a. This AC voltage is 1 MH
At least one of a high-frequency voltage having a frequency greater than z and equal to or less than 1000 MHz and a low-frequency voltage having a frequency equal to or less than 1 MHz. Further, only the high-frequency AC voltage whose absolute value is equal to or less than the glow discharge starting voltage, or only the low-frequency AC voltage whose absolute value is equal to or less than the glow discharge starting voltage, or a voltage obtained by superimposing the high-frequency AC voltage on the low-frequency AC voltage Alternatively, a configuration in which a low-frequency AC voltage and a high-frequency AC voltage are superimposed on a DC voltage may be applied. As the voltage, the entire voltage or the voltage of each component may be varied during film formation. However, the absolute value of each voltage is set to be within the range of the glow discharge starting voltage or less.

Also, during the film formation or during the film formation, reactive species such as ions are generated from the reaction gas by the catalytic action of the catalyst body, which may charge up the substrate and degrade the performance of the film or device. is there. In order to prevent this, it is desirable to neutralize ions by irradiating the reactive species with charged particles (such as an electron beam or proton, particularly an electron beam) for preventing charge. That is, it is preferable that a charged particle irradiation unit is provided near the susceptor.

In the present invention, a silicon-based film immediately after film formation is defined as follows. The amorphous silicon film is made of silicon (a-S) having an amorphous structure containing hydrogen.
i: H). The microcrystalline silicon film is microcrystalline silicon containing amorphous silicon {nc-Si
(Abbreviation of nanocrystalline silicon) A film in which｝ gathers. The polysilicon film is a polysilicon having a relatively small particle diameter containing amorphous silicon and microcrystalline silicon (nc-Si), which is formed by using a polysilicon film having a relatively small grain size.
(Microcrystalline Silicon
(Abbreviation of と す る) What is a single crystal silicon film?
A single crystal silicon film including a single crystal containing subgrain boundaries and dislocations is used. Amorphous silicon with high absorption of laser light and easy to melt, and nc- of crystal growth seed
The present invention is characterized in that Si and μc-Si are well combined to promote recrystallization by laser annealing such as excimer laser annealing, thereby forming a polysilicon film having a large grain size.

The laser annealing step may be performed after forming the semiconductor film and the insulating film instead of after the semiconductor film forming step. The insulating film is, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a composite film thereof.

In the present invention, at least one of tin, germanium, and lead is used, so that the obtained semiconductor layer (amorphous silicon layer, microcrystalline silicon layer, polycrystalline silicon layer) Even if the group elements tin, germanium, and lead are mixed, they are elements of group 4 of the periodic table and do not become carriers in the silicon layer, so that the silicon layer has a high resistance. Therefore, _Vth adjustment and resistance value adjustment of the TFT by ion doping (implantation) or the like become easy. Further, since the crystal irregularities existing at the crystal grain boundaries are reduced and the internal stress is reduced, high electron / hole mobility becomes possible, and a high-performance circuit configuration becomes possible.

As described above, since the thin film is configured to be subjected to the annealing treatment by the laser, only the film is instantaneously heated, and the influence of the heat on the substrate 10 is hardly affected.
The amorphous silicon or microcrystalline silicon thin film can be crystallized and the carrier impurities can be activated without causing the deformation of the amorphous silicon or microcrystalline silicon thin film. Moreover, the crystallization and activation can be performed at a low temperature without increasing the temperature of the entire substrate 10. Further, the present invention improves the performance of the thin film semiconductor device and facilitates manufacturing.

At this time, in order to enhance the laser annealing effect, the substrate 10 is heated to 200 ° C. or more and less than 500 ° C., and the formed film is excimer laser or argon having a beam shape of a line beam or an area beam. Annealing may be performed with a laser such as a laser.

Since amorphous silicon has a high light energy absorption of laser light, the polysilicon film is
By implanting silicon ions or the like and implanting a seed (seed) for crystal growth and simultaneously forming amorphous silicon, it becomes easier to form a large grain polysilicon film. This implantation of silicon ions or the like can be performed, for example, as follows. (1) As needed, 1-2E15 at 20-30 keV
After implanting atoms / cm ² of silicon ions (SiF ₄ ), laser annealing is performed. (2) If necessary, 20E to 30K eV of 1.0E13
After implanting tin ions at 1.0E14 atoms / cm ² , laser annealing is performed. (3) If necessary, after the same silicon ion implantation as in the above (1), 1.0E13-1.0 of 20-30 keV.
After implanting tin ions at E14 atoms / cm ² ,
Perform laser annealing. (4) If necessary, other group 4 elements (germanium,
After implanting lead (ion) ions, laser annealing is performed. (5) If necessary, after the same silicon ion implantation as in the above (1), another group IV element (germanium, lead) ions are implanted, and then laser annealing is performed.

Polysilicon is difficult to be dissolved by laser annealing. Therefore, when laser annealing is performed after injecting tin ions, germanium ions, or lead ions to form amorphous, polysilicon having a large grain size is formed and the grain boundary is formed. Since the internal stress is reduced by reducing the existing crystal irregularity, the mobility can be improved.

The tin, germanium,
The content of any one or more of the lead is 1 × 10 ^{15 in} total.
atoms / cm ³ or more, preferably 1 × 10 ¹⁸ at
oms / cm ³ or more and 1 × 10 ²⁰ atoms / cm
It is preferable that it is ³ or less.

The thermal catalyst 5 is preferably heated to a temperature lower than the melting point of the thermal catalyst 5 and 800 ° C. or more and 2000 ° C. or less. At this time, it is preferable that the temperature of the substrate 10 be 200 ° C. or more and 500 ° C. or less.

As described above, when the thermal catalyst 5 is heated, activated hydrogen ions H ^* are generated from the hydrogen gas introduced into the vacuum vessel 1, so that the substrate surface can be cleaned. For example, when a silicon oxide film and a polysilicon film are formed, a transition layer of amorphous silicon is not formed at the interface between these thin films, and a high-quality thin film layer can be formed. In addition, by using the heated thermal catalyst 5, most of the raw material gas can be formed as a thin film, a thin film can be efficiently formed using the raw material gas, and the cost can be reduced.
The thermal catalyst 5 is made of at least one material selected from the group consisting of tungsten, thoria-containing tungsten, platinum, molybdenum, palladium, metal-deposited ceramics, silicon, alumina, and silicon carbide.

The substrate 10 is made of silicon, germanium, silicon germanium, silicon carbide,
Gallium arsenide, gallium aluminum arsenide, gallium phosphorus, indium phosphorus, zinc selenide, cadmium sulfide,
The material may be selected from quartz glass, borosilicate glass, aluminosilicate glass, a semiconductor including a heat-resistant resin, or an insulating material.

In the present invention, before the semiconductor film forming step,
A cleaning step of constantly supplying a carrier gas containing hydrogen to the vacuum container 1 and cleaning the surface of the substrate 10 with activated hydrogen ions H ^* generated by the supplied carrier gas is performed. Then, the cleaning step and the semiconductor film forming step are performed.

As described above, when a thin film is formed on the substrate 10, a carrier gas containing hydrogen is supplied, so that a part of the supplied carrier gas becomes activated hydrogen ions H ^* , The ions H ^* clean the substrate surface and form a high-quality thin film on the substrate 10. And supply hydrogen gas as carrier gas,
By heating the thermal catalyst 5 to make it possible to perform a catalytic action and continuously forming at least a silicon film and a gate insulating film, the gate channel portion has low stress, low contamination, and low interface state, thereby improving characteristics. It is possible to do. Further, when a thin film semiconductor device is manufactured by using the semiconductor film forming method according to the present invention, the performance of the thin film semiconductor device is improved and the manufacturing is facilitated.

Here, “continuous film formation” has been described. In this specification, “continuous film formation” includes the following three types. First, the case where the gate insulating film and the semiconductor film are continuously formed in the film forming apparatus 1 has the meaning described herein. Next, the insulating film is made of SiN-SiON-
This is a case where the film is formed as a gradient composite film of SiO ₂ or the like. Further, there is a case where different insulating films are successively formed.

Before the semiconductor film forming step, a carrier gas containing hydrogen is supplied to the vacuum vessel 1 and a cleaning step of cleaning the substrate 10 with activated hydrogen ions H ^* generated by the supplied carrier gas. And a step of increasing or decreasing the supply of the carrier gas at least one before, during, or after the semiconductor film forming step, and the semiconductor film forming step. A thin film is formed on the cleaned substrate 10 by introducing at least a source gas into the vacuum vessel 1. At this time, for example,
As shown by the dashed line in FIG. 3, by reducing the supply of the carrier gas in the middle, the ratio of the source gas in the vacuum vessel 1 increases, and a thin film can be formed at a high speed. When the thermal catalyst 5 that does not deteriorate by oxidation is used as the thermal catalyst 5, the supply of the carrier gas into the vacuum chamber 1 during the semiconductor film forming process is performed as shown by the solid line in FIGS. Can also be stopped. That is, when the thermal catalyst 5 is a thermal catalyst that does not undergo oxidative degradation even in the presence of oxygen, the thermal catalyst 5 does not undergo oxidative degradation or disconnection due to residual oxygen even when the supply of hydrogen gas is stopped. The thermal catalyst that does not deteriorate by oxidation is, for example, a material obtained by coating a high-melting point metal (tungsten, tungsten containing tria, tantalum, molybdenum, silicon, or the like) with ceramics or silicon carbide, or silicon whose surface is oxidized or nitrided.

Further, when performing various film formations, for example,
As shown by the dotted line in FIG. 3, by increasing the introduction of the carrier gas before and after the semiconductor film forming step, a large amount of activated hydrogen ions H ^* are generated by the thermal catalyst 5 before and after the film formation. , Cleaning, film stress reduction and the like can be promoted.

In the present invention, a semiconductor film and an insulating film are formed in the vacuum vessel 1, and a laser annealing step is performed in a laser annealing apparatus outside the vacuum vessel 1. At this time, the semiconductor film and the insulating film can be formed by either the single-chamber or multi-chamber vacuum vessel 1. However, in the vacuum chamber 1, a film forming chamber 46,
The laser annealing chamber 44 may be provided. The semiconductor film forming step is performed in the film forming chamber 46 in the vacuum vessel 1, the laser annealing step is performed in the laser annealing chamber 44, and the semiconductor film forming step and the laser annealing step are continuously performed in the vacuum vessel. At this time, an insulating film forming chamber 47 may be provided in the vacuum apparatus 1 separately from the film forming chamber 46, and the insulating film may be formed in the insulating film forming chamber 47.

The semiconductor film and the insulating film are formed in the same deposition chamber 43.
It can also be formed within. In a film forming chamber 43 for forming a semiconductor film, an insulating film is formed on the semiconductor film annealed by the laser, and the semiconductor film forming step, the laser annealing step, and the forming of the insulating film are continuously performed in the vacuum chamber 1. Do it.

In the present invention, a semiconductor film containing at least one of tin, germanium and lead and an insulating film are formed on the substrate 10 by supplying at least a source gas to the vacuum vessel 1. And a water vapor annealing step of annealing the formed semiconductor film and insulating film with water vapor.

In the steam annealing step, the partial pressure is 1 × 10
²In an atmosphere containing water vapor that is not less than Pa and not more than the saturated vapor pressure
At a time of 10 seconds or more and 20 hours or less, at normal temperature or more and 400 ° C.
The film formed by heating to the temperature below
Anneal. At this time, oxygen, nitrogen, hydrogen,
Nitrogen oxide or carbon dioxide gas
The partial pressure of any one or more of the gases is 1 × 1
0²Pa or more 1 × 10 ⁶Steam in an atmosphere of Pa or less
Annealing is performed. Thus, low pressure to high pressure containing steam
Low-temperature heat treatment to perform annealing in the atmosphere of
And interfacial properties between semiconductor film and insulating film and insulation
The film can be modified.

In the present invention, a semiconductor film is formed in the vacuum vessel 1, and a steam annealing step is performed in a steam annealing apparatus outside the vacuum vessel 1. However, the film forming chamber 4 is provided in the vacuum vessel 1.
3 and a steam annealing chamber 45 may be provided. A semiconductor film and insulating film forming step is performed in the film forming chamber 43 in the vacuum vessel 1, a steam annealing step is performed in the steam annealing chamber 45, and the semiconductor film and insulating film forming step and the steam annealing step are continuously performed in the vacuum vessel 1. Do it.

Further, an insulating film forming chamber 47 may be provided in the vacuum apparatus 1 separately from the film forming chamber 46, and the insulating film may be formed in the insulating film forming chamber 47. At this time, a semiconductor film is formed in the semiconductor film forming chamber 46 in the vacuum vessel 1, an insulating film is formed in the insulating film forming chamber 47 in the vacuum vessel 1, and steam is formed in the steam annealing chamber 45 in the vacuum vessel 1. An annealing step is performed, and the formation of the semiconductor film, the formation of the insulating film, and the steam annealing step are continuously performed in a vacuum vessel.

In the present invention, single crystal silicon can be formed as the semiconductor film. When the semiconductor film is single crystal silicon, a step is formed at least in a silicon film formation region, and a single crystal silicon film is grapho-epitaxially grown in the silicon film formation region including the step. That is, since a step is provided on the substrate, and a single crystal silicon film is grapho-epitaxially grown on the substrate including the step,
A single crystal silicon film having high electron / hole mobility and excellent operability can be obtained. In the present invention, the single crystal includes a single crystal containing sub-grain boundaries and dislocations. In addition, it goes without saying that not only single crystal silicon but also compound semiconductors such as single crystal gallium / arsenic and single crystal silicon / germanium can be epitaxially grown.

In the case where the semiconductor film is single crystal silicon, a material layer having good lattice matching with single crystal silicon is formed at least in the silicon film formation region, and the single crystal silicon film is heterogeneously formed in the silicon film formation region including the material layer. Epitaxial growth can also be performed. That is, since a material layer having good lattice matching with single crystal silicon is formed on the substrate, and the single crystal silicon film is heteroepitaxially grown on the substrate including the material layer, high electron / hole mobility and high operability are obtained. A single-crystal silicon film having excellent characteristics can be obtained. The material layer having good lattice matching with the single crystal silicon is made of at least one material selected from a group including sapphire or spinel structure, or calcium fluoride.

Further, in the present invention, a semiconductor film and an insulating film forming step, a laser annealing step, a steam annealing step as a step subsequent to the laser annealing step, and a cleaning step for cleaning by plasma or sputtering are provided. You can also.

In the present invention, a semiconductor film and an insulating film are formed in the vacuum vessel 1, and a laser annealing step is performed in a laser annealing apparatus outside the vacuum vessel 1, and a steam annealing step is performed in a steam annealing apparatus outside the vacuum vessel 1. Do. However,
A film forming chamber 43 and a laser annealing chamber 4
4 and a steam annealing chamber 45 may be provided. A semiconductor film and an insulating film forming step are performed in a film forming chamber 43 in the vacuum vessel 1, a laser annealing step is performed in a laser annealing chamber 44 in the vacuum vessel 1, and a steam annealing step is performed in a steam annealing chamber 45 in the vacuum vessel 1. Do
The semiconductor film forming step, the laser annealing step, and the steam annealing step are continuously performed in the vacuum vessel 1.

Further, an insulating film forming chamber 47 may be provided in the vacuum apparatus 1 separately from the film forming chamber 46, and an insulating film may be formed in the insulating film forming chamber 47. A semiconductor film is formed in a semiconductor film forming chamber 46 in the vacuum vessel 1, a laser annealing process is performed in a laser annealing chamber 44 in the vacuum vessel 1, and an insulating film is formed in an insulating film forming chamber 47 in the vacuum vessel 1. Then, a steam annealing step is performed in the steam annealing chamber 45 in the vacuum vessel 1, and the formation of the semiconductor film, the laser annealing step, the formation of the insulating film, and the steam annealing step are continuously performed in the vacuum vessel 1.

The method of forming a semiconductor film according to the present invention can be performed not only by bias catalyst CVD or high-density bias catalyst CVD, but also by bias low pressure CVD or bias normal pressure CVD. Bias reduced pressure CVD, bias normal pressure C
VD is a method of performing low pressure CVD and normal pressure CVD by applying an electric field. Atmospheric pressure CVD means NPCVD (Norm
al Pressure CVD), which is CVD performed at normal pressure without using a vacuum device. It is characterized in that the substrate is directly heated by high frequency or infrared rays.
d Use a wall-shaped container. Low pressure CVD means LPCVD (Low Pressure CVD).
CV performed by reducing the pressure to about 10 to 10 ³ Pa
Method D. It is characterized in that the substrate is heated by resistance heating, and a Hot Wall type container is used. Normal pressure CV
D. Low-pressure CVD differs from plasma CVD, catalytic CVD, and the like in that a thin film is formed by heating a substrate to a high temperature of several hundred degrees Celsius or more.

In the present invention, the semiconductor film forming step or the semiconductor
Semiconductor film immediately after formed in body film and insulating film forming process
Is at least a carrier channel region in the semiconductor film.
Concentration of oxygen, carbon and nitrogen at 1 × 10
¹⁹atoms / cm³Below, the hydrogen concentration is 0.01 atom
% / Cm³The semiconductor film is as described above. Ma
In the laser annealing process and the steam annealing process,
After the semiconductor film is cooled, at least the carrier channel
The concentration of oxygen, carbon, and nitrogen in the tunnel region
1 × 10¹⁹atoms / cm³Hereinafter, when the hydrogen concentration is 0.
01 atomic% / cm ³So that

Further, the method of manufacturing a thin film semiconductor device according to the present invention is a method of manufacturing a top gate type TFT using bias catalytic CVD or high density bias catalytic CVD. At least the raw material gas is supplied to the vacuum vessel 1,
In a vacuum vessel 1, a protective film, a semiconductor film containing at least one of tin, germanium, and lead, and a gate insulating film are continuously formed on a substrate 10. afterwards,
This semiconductor film is subjected to laser annealing, and then source / top gate / drain electrodes are formed.

Further, the method of manufacturing a thin film semiconductor device according to the present invention is a method of manufacturing a bottom gate type TFT by utilizing bias catalytic CVD or high density bias catalytic CVD. A bottom gate electrode is formed on a substrate 10, and at least a source gas is supplied to the vacuum vessel 1. In the vacuum vessel 1, a protective film, a bottom gate insulating film, and at least tin, germanium, and lead are formed on the bottom gate electrode. A semiconductor film containing at least one of the above and a protective film are successively formed, and thereafter, the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film, and then a source / drain electrode is formed.

The method for manufacturing a thin-film semiconductor device according to the present invention is a method for manufacturing a dual-gate TFT using bias catalytic CVD or high-density bias catalytic CVD. A bottom gate electrode is formed on a substrate 10, and at least a source gas is supplied to the vacuum vessel 1.
In the above, a protective film, a bottom gate insulating film, a semiconductor film containing at least one of tin, germanium, and lead, and a top gate insulating film are successively formed on the bottom gate electrode, The semiconductor film is laser-annealed into a polycrystalline semiconductor film, and then source / top gate / drain electrodes are formed.

At this time, hydrogen gas, monosilane gas and
Raw material gas consisting of ammonia gas and
To form a silicon nitride film. Also,
Hydrogen gas, monosilane gas and helium diluted oxygen gas
Is supplied into the vacuum vessel to produce silicon oxide.
A cone film can be formed. In addition, hydrogen gas,
Silane gas and at least one of tin, germanium, and lead
And supplying a source gas consisting of:
An alloy containing at least one of tin, germanium, and lead
Morphous silicon film or microcrystalline silicon film or
A silicon film can be formed. At this time,
Phosphorus, arsenic, or antimony in monosilane gas
Amorphous silicon mixed with N-type impurity carrier concentration
Silicon film or microcrystalline silicon film or polysilicon film.
It is good to do. Further, the monosilane gas or the silicon
P type impurity carrier concentration by mixing boron into run gas
Amorphous silicon film or microcrystalline silicon film
It is preferable to form a polysilicon film. At this time,
If the source gas for tin is SnCl₄, SnH₄, (C
H₃) ₄It is preferable to use an organotin compound containing Sn.
Furthermore, tin is 1 × 10^Fifteenatoms / cm³that's all,
Preferably, 1 × 10¹⁸atoms / cm³~ 1 × 1
0²⁰atoms / cm³Added or doped
Good to do.

In the above-described method of manufacturing a thin film semiconductor device, laser annealing is performed after forming a semiconductor film and an insulating film. Thereafter, electrodes are formed, and then steam annealing and plasma cleaning and sputter cleaning of the electrodes are performed. You can also do so. Further, it is also possible to perform the steam annealing process and the plasma cleaning and sputter cleaning of the electrode after the electrode formation without performing the laser annealing process.

According to the method of forming a thin film and the method of manufacturing a thin film semiconductor device according to the present invention, a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, and a compound Semiconductor integrated circuit device, silicon carbide semiconductor device, silicon carbide semiconductor integrated circuit device, liquid crystal display device, organic / inorganic electroluminescence display device,
Manufactures field emission display devices, plasma display panel (PDP) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, high dielectric constant films and ferroelectric memory devices, solar cells, etc. can do.

Since not only the top gate type but also the bottom gate and dual gate type TFTs can obtain a high electron / hole mobility tin or lead, germanium-containing polysilicon film or single crystal silicon film, this high performance It is possible to manufacture a high-speed and high-current-density semiconductor device, an electro-optical device, a solar cell device, and the like using a polysilicon film semiconductor or a single crystal silicon film semiconductor. Other details, functions, effects, and the like of the present invention will be more apparent in the following embodiments.

[0124]

An embodiment of the present invention will be described below with reference to the drawings. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. FIG. 1 is a schematic view showing one embodiment of a thin film forming apparatus S used in the present invention.

(DC bias catalytic CVD method and its apparatus)
In this example, based on the catalytic CVD method, a reactive gas composed of a hydrogen-based carrier gas and a raw material gas such as a silane gas is brought into contact with a heated catalyst such as tungsten, and the radical deposition species generated thereby or a precursor thereof is generated. A kinetic energy is applied to the body and radical hydrogen ions by applying an electric field equal to or lower than the glow discharge initiation voltage, and when a predetermined film such as polycrystalline silicon is vapor-phase grown on the substrate, a glow discharge is generated between the substrate and the counter electrode. DC voltage equal to or less than the starting voltage (DC voltage determined by Paschen's law, for example, voltage of 1 kV or less)
To direct the radical deposition species or its precursor and radical hydrogen ions toward the substrate. Hereinafter, the CVD method of this example is referred to as a DC bias catalytic CVD method. The DC bias catalytic CVD method of the present embodiment is performed using a film forming apparatus as shown in FIGS.

According to this film forming apparatus (DC bias catalytic CVD apparatus), a hydrogen-based carrier gas and a source gas 40 such as silicon hydride (for example, monosilane) (and B ₂ H ₆ or PH ₃ if necessary) are used. A reaction gas composed of a doping gas is introduced from the supply conduit 61 into the film forming apparatus 1 through the supply port 43 of the gas shower head 3a. Inside the film forming apparatus 1, a susceptor 2 for supporting a substrate 10 such as glass, and a gas shower head having good heat resistance (preferably a material having a melting point equal to or higher than that of the thermal catalyst 5) are provided. 3a, a coil-shaped thermal catalyst 5 such as tungsten, and a shutter 67 that can be opened and closed.
And are arranged respectively. In addition, a magnetic seal 72 is provided between the susceptor 2 and the film forming apparatus 1. Also,
The film forming apparatus 1 is followed by a pre-chamber 73 for performing a pre-process, and is evacuated via a valve 75 by a turbo molecular pump 74 or the like.

The substrate 10 is heated by a heating means such as a heater 2b in the susceptor 2. The thermal catalyst 5 is, for example, a resistance wire having a melting point or less (especially 800 to 2000 ° C., and about 1600 to 1700 ° C. in the case of tungsten). ) Is activated by heating. Both terminals of the thermal catalyst 5 are connected to a DC or AC catalyst power supply 68, and are heated to a predetermined temperature by power supply from the power supply. Gas shower head 3a
Is connected to the positive electrode side of a variable DC power supply (1 kV or less, for example, 500 V) 69 via a conduit 61 as an accelerating electrode, and has a DC bias voltage of 1 kV or less between itself and the susceptor 2 (therefore, the substrate 10) on the negative electrode side. Is applied.

The DC bias catalytic CVD method is performed.
The vacuum degree in the film forming apparatus 1 is 10 ^-4-10^-6Pa
For example, a hydrogen-based carrier gas of 100 to 200 SCC
M (Standard cc per minute:
The same applies hereinafter) to heat the catalyst 5 to a predetermined temperature.
After activation, silicon hydride (eg, monosilane)
Gas 1-20 SCCM (and B if necessary₂H₆And
PH₃Doping gas. Reaction consisting of
The gas 40 is supplied from the supply conduit 61 to the gas shower head 3a.
The gas is introduced through the supply port 43 and the gas pressure is 10 to 10^-1
Pa, for example, 1 Pa. Here, hydrogen carrier gas
Are hydrogen, hydrogen + argon, hydrogen + helium, hydrogen +
Hydrogen such as neon, hydrogen + xenon, hydrogen + krypton
Any gas that is a mixture of an appropriate amount of inert gas
(The same applies hereinafter). Depending on the type of source gas
Does not necessarily require a hydrogen-based carrier gas. Immediately
In other words, the catalytic reaction of only silane without hydrogen-based carrier gas
A method of forming a poly-Si film (called a Hot Wire method)
ing. ) Is known, and the present invention is also applied to this method.
Because it is possible.

At least a part of the reaction gas 40 is catalytically decomposed by contacting the thermal catalyst 5 and a group of reactive species such as ions and radicals such as silicon having high energy by a catalytic decomposition reaction or a thermal decomposition reaction. (Ie, deposited species or precursors thereof and radical hydrogen ions). A kinetic energy is applied to the reaction species 70 such as ions and radicals thus generated by applying a DC electric field from a DC power supply 69 of a glow discharge starting voltage (about 1 kV) or less, for example, 500 V, and the kinetic energy is directed to the substrate 10 side. A predetermined film such as polycrystalline silicon is vapor-phase grown on the substrate 10 maintained at a temperature of 550 ° C. (for example, 200-300 ° C.).

Thus, without generating plasma,
The catalytic action of the thermal catalyst 5 and the directional kinetic energy obtained by adding the acceleration energy by the DC electric field to the thermal energy are given to the reactive species, so that the reactive gas is efficiently converted into the reactive species, and the substrate 10 is converted by the DC electric field. Thermal CVD uniformly on top
Method. The deposited species 56 is
Since it migrates on the top and diffuses in the thin film, it is possible to form a flat and uniform thin film with high density and good step coverage.

Therefore, the DC bias catalytic CVD according to the present embodiment is independent of the control factors of the conventional catalytic CVD, such as the substrate temperature, the catalyst temperature, the gas pressure (reaction gas flow rate), and the type of the source gas. The feature is that the control of thin film formation by a DC electric field is added. For this reason, including the adhesion of the generated film to the substrate,
The density of the formed film, the uniformity or smoothness of the formed film, the embedding property in the via hole and the like, and the step coverage are improved, the substrate temperature is further lowered, and the stress control of the formed film becomes possible. Physical properties of a silicon film or a metal film). Moreover, since the reactive species generated by the thermal catalyst 5 can be independently controlled by a DC electric field and can be efficiently deposited on the substrate, the utilization efficiency of the reaction gas is high, the generation speed is increased, the productivity is improved, and the reaction gas is improved. Cost can be reduced by reduction.

Further, even if the substrate temperature is lowered, the kinetic energy of the deposited species is large, so that a desired high-quality film can be obtained. Therefore, the substrate temperature can be further lowered as described above. An insulating substrate (a glass substrate such as borosilicate glass or aluminosilicate glass, a heat-resistant resin substrate such as polyimide, or the like) can be used, and the cost can be reduced in this regard. In addition, since the gas shower head 3a for supplying the reaction gas can be used as an electrode for accelerating the reaction species, the structure is simplified.

Also, needless to say, since no plasma is generated, a plasma-damage-free, low-stress generating film can be obtained, and a much simpler and less expensive apparatus can be realized as compared with the plasma CVD method. I do.

In this case, under reduced pressure (for example, 10 ^{-1 to} 1P)
a) Or operation can be performed under normal pressure, but the normal pressure type realizes a simpler and less expensive device than the reduced pressure type. And even the normal pressure type applies the above electric field,
A high quality film with good density, uniformity and adhesion can be obtained. Also in this case, the normal pressure type has higher throughput, higher productivity, and cost reduction than the reduced pressure type.

In the case of the decompression type, the DC voltage depends on the gas pressure (reaction gas flow rate), the kind of the source gas and the like, but in any case, it is necessary to adjust the voltage to an arbitrary voltage equal to or lower than the glow discharge starting voltage. . In the case of the normal pressure type, no discharge is performed, but it is desirable to adjust the exhaust gas so that the exhaust gas flow does not come into contact with the substrate so that the flow of the raw material gas and the reactive species does not adversely affect the film thickness and the film quality. In this example, as shown in FIG.
However, as shown in FIG. 4, the substrate 10 may be arranged below the shower head 3a.

One of the features of the present invention is that, when a semiconductor film is formed by CVD, at least one of tin, germanium and lead is mixed or introduced simultaneously with a raw material gas to form at least tin, germanium, This is at the point of forming a semiconductor film containing at least one of lead.
That is, as an example of a gas containing monosilane, disilane, or trisilane and tin, germanium, or a lead element as a raw material gas, a gas containing tin hydride (SnH ₄ ) or an organic compound of tin (CH ₃ ) ₄ Sn is introduced. Then, a polysilicon film or the like containing another group 4 element other than carbon is formed.

A feature of the present invention lies in that an electric field is applied when a thin film is formed by the catalytic CVD method. In the present invention, when a thin film is formed by the catalytic CVD method, a DC voltage equal to or lower than a glow discharge starting voltage (that is, equal to or lower than a plasma generation voltage determined by Paschen's law, for example, 1 kV).
Hereinafter, several tens of volts or more are applied, and the reactive species are directed toward the substrate 10 to efficiently deposit the reactive species.

As the electric field, a voltage lower than the glow discharge starting voltage and a voltage obtained by superimposing an AC voltage on a direct current voltage (DC) (that is, a voltage lower than a plasma generation voltage determined by Paschen's law, for example, 1 kV or less, several tens V or more) is used. It may be applied. In this case, the kinetic energy of the directivity due to the subtle electric field change can be given to the reactive species by the AC voltage superimposed on the DC voltage. A step (uniform step, via hole with a high aspect ratio, or the like) has good step coverage on the surface, and a uniform film having high adhesion and density can be formed. The same operation and effect as described above can be obtained by converting the electric field to a voltage (however, the absolute value thereof is equal to or lower than the glow discharge starting voltage) to a high frequency AC voltage only, a low frequency AC voltage only, or a low frequency AC voltage. It is also obtained when applying a voltage on which a high-frequency AC voltage is superimposed.

In the above case, the AC voltage may be a high frequency voltage (RF) and / or a low frequency voltage (AC).
The frequency of the high frequency voltage is greater than 1 MHz and 1000 MH
It is preferable that the frequency of z or less and the frequency of the low frequency voltage be 1 MHz or less.

An RF / DC bias catalytic CVD method using the AC voltage as a high frequency voltage (RF) will be described. (RF / DC Bias Catalytic CVD Method and Apparatus) In this example, based on the catalytic CVD method, a reaction gas comprising a hydrogen-based carrier gas and a raw material gas such as silane gas is brought into contact with a heated catalyst such as tungsten. A kinetic energy is applied by applying an electric field equal to or less than the glow discharge starting voltage to the radical deposition species or precursor thereof and radical hydrogen ions generated by the above, to give kinetic energy, and to vapor-grow a predetermined film such as polycrystalline silicon on the insulating substrate. At this time, a voltage (a voltage determined by Paschen's law, for example, a voltage of 1 kV or less) obtained by superimposing a high-frequency voltage on a DC voltage and being equal to or lower than a glow discharge starting voltage between the substrate and the counter electrode is applied to the radical. It directs the deposited species or its precursor and radical hydrogen ions to the side of the substrate, and gives kinetic energy in subtle electric field changes. It may be. Hereinafter, this CVD method is referred to as an RF / DC bias catalytic CVD method.

The RF / DC bias catalytic CVD method
This is performed using a film forming apparatus as shown in FIG. The gas shower head 3 a is connected as an acceleration electrode to the positive electrode side of a variable DC power supply (1 kV or less, for example, 500 V) 69 from a conduit 61 via a low-pass (high-frequency) filter 113, and a high-frequency power supply 115 via a matching circuit 114. (1
00-200V _pp and 1-100MHz, for example 1
50 Vp _-p , 13.56 MHz), and a DC bias voltage of 1 kV or less of a high-frequency voltage superimposed is applied between the susceptor 2 (therefore, the substrate 10). The other configurations of the RF / DC bias catalytic CVD method and its apparatus are the same as those of the DC bias catalytic CVD method and the apparatus described above.

An AC / DC bias catalytic CVD method using the AC voltage as a high frequency voltage (RF) will be described. (AC / DC Bias Catalytic CVD Method and Apparatus) In this example, based on the catalytic CVD method, a reaction gas comprising a hydrogen-based carrier gas and a raw material gas such as silane gas is brought into contact with a heated catalyst such as tungsten. A kinetic energy is applied by applying an electric field equal to or less than the glow discharge starting voltage to the radical deposition species or precursor thereof and radical hydrogen ions generated by the above, to give kinetic energy, and to vapor-grow a predetermined film such as polycrystalline silicon on the insulating substrate. At this time, a voltage (a voltage determined by Paschen's law, for example, a voltage of 1 kV or less) which is lower than a glow discharge starting voltage and is superimposed on a DC voltage and which is lower than a glow discharge start voltage is applied between the substrate and the counter electrode, To direct the deposition species or its precursor and radical hydrogen ions to the substrate side, and to give kinetic energy by electric field change. Good. Hereinafter, this CVD method is referred to as AC
/ DC bias catalytic CVD method.

This AC / DC bias catalytic CVD method
This is performed using a film forming apparatus as shown in FIG. The shower head 3 a is connected as an acceleration electrode to the positive electrode side of a variable DC power supply (1 kV or less, for example, 500 V) 69 via a conduit 61 (the above-mentioned low-pass filter 113 can be omitted), and via a matching circuit 114. Low frequency power supply 125 (1
00~200V _P-P and 1MHz or less, for example 150
VP _-P , 26 kHz), and a DC bias voltage of 1 kV or less superimposed with a low-frequency voltage is applied between the susceptor 2 and the substrate 10.

As shown in FIG. 7, the electric field was applied to the accelerating electrode 3a by connecting the positive electrode of the power source to the susceptor 2 (substrate 10).
(A) applying the negative electrode side (or ground potential) to the susceptor 2 (substrate 1)
Any method (B) of applying the negative electrode side to 0) may be used.
This may be determined according to the device structure, the type of power supply, the bias effect, and the like.

The thermal catalyst and the electrode for applying an electric field may be provided between the substrate 10 or the susceptor 2 and the reaction gas supply means. This electrode is desirably formed of a highly heat-resistant material, for example, a material having a melting point equal to or higher than that of the thermal catalyst.

The thermal catalyst or the electrode 3 for applying an electric field
a may be formed in a coil shape, a wire shape, a mesh shape or a perforated plate shape, and a plurality or a plurality may be arranged along the gas flow. For example, the shape of the electrode 3a can be a perforated plate shape in FIG. 8A and a mesh shape in FIG. 8B. Thereby, while effectively forming the gas flow, the contact area between the catalyst body and the gas can be increased, and the catalytic reaction can be sufficiently generated. When a plurality or a plurality of sheets are arranged along the gas flow, the catalyst or the electrode 3a may be made of the same material or different materials. Also, different electric fields are applied to each of a plurality of or a plurality of catalyst bodies, for example, DC and AC / DC, DC and RF / DC, and AC / DC.
And RF / DC may be applied for independent control.

Further, during the film formation or during the film formation, reactive species such as ions are generated from the reaction gas by the catalytic action of the catalyst body, thereby charging up the substrate and deteriorating the performance of the film or device. is there. In order to prevent this, it is desirable to neutralize ions by irradiating the reactive species with charged particles (such as an electron beam or proton, particularly an electron beam) for preventing charge. That is, the charged particle irradiation means is preferably provided near the susceptor 2.

For example, in the RF / DC bias catalytic CVD method and its apparatus, a charged particle or ion (for example, electron) shower 100 may be provided near the substrate 10 or the susceptor 2 as shown in FIG.

One of the features of the present invention is that the bias catalyst CV
In addition to forming a film using the thermal catalyst 5 for D, there is also a point that a hydrogen-based carrier gas is introduced into the chamber to perform a surface treatment for reducing interface defects. This will be described in detail below. In the above-described bias catalytic CVD method, by changing the type of gas to be introduced, a surface treatment for modifying or cleaning the surface of the substrate can be performed.
As described above, when the film is formed after the substrate surface is processed, a high-quality film with extremely few interface defects can be formed.

In this example, a hydrogen-based gas as a carrier gas is introduced from the gas shower head 3a in order to perform reforming and cleaning on the surface of the substrate 10. Examples of the hydrogen-based gas include hydrogen gas and hydrogen gas containing an inert gas such as argon, helium, and neon.
In this embodiment, an example using only hydrogen gas will be described. The hydrogen gas is activated by a catalytic decomposition reaction with the thermal catalyst 5, and the activated hydrogen ions H ^* can perform cleaning for removing a natural oxide film, moisture, and dirt on the substrate surface.
Further, the activated hydrogen ions H ^* can prevent the thermal catalyst 5 from being oxidized and prevent the thermal catalyst 5 from deteriorating. At this time, by applying an electric field, the cleaning action by the activated hydrogen ions H ^* becomes efficient.

One of the features of the present invention is that the bias catalyst CV
When a semiconductor film and an insulating film are formed by D, the film can be formed at a desired quality and at a desired speed depending on the introduction time and timing of the carrier gas and the source gas. Hereinafter, a method of introducing the carrier gas and the source gas in the apparatus of FIG. 1 will be described with reference to FIGS. 10 to 15, as an example, a silicon nitride film and a silicon oxide film for a protective film, a polysilicon film containing at least one of tin, germanium, and lead on a substrate, and a gate insulating film The case where the silicon oxide film is formed will be described.

The gas introduction modes shown in FIGS. 10 to 12 are as follows.
It is assumed that a predetermined amount of hydrogen gas as a carrier gas is continuously introduced into the film forming apparatus 1. First, the gas introduction mode shown in FIG. 10 will be described. FIG. 10 shows a case where the surface of the substrate 10 is cleaned each time before performing various kinds of film formation. In this case, an introduction form of a hydrogen gas and a source gas as a carrier gas is shown. .

First, the substrate 10 is carried into the film forming apparatus 1 through a gate valve (not shown), and is placed on the susceptor 2.
Next, the evacuation system 1a is operated to exhaust the inside of the film forming apparatus 1 to a predetermined pressure, and the heater 2a built in the susceptor 2 is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introduction system 3 is operated, and first, 150 SCCM of hydrogen gas is introduced into the film forming apparatus 1. Part of the introduced hydrogen gas becomes activated hydrogen ions H ^* by the catalytic decomposition reaction and the catalytic reaction by the thermal catalyst 5, and reaches the substrate surface efficiently by applying an electric field, thereby cleaning the surface of the substrate 10.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. DC voltage equal to or lower than the glow discharge starting voltage (that is, equal to or lower than the plasma generation voltage determined by Paschen's law, for example, equal to or lower than 1 kV,
(0 V or more) is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of reactive species reaches the substrate 10 and
A silicon nitride film is formed as a thin film on the substrate surface.

Thereafter, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1. In the present example, the second source gas is introduced after a lapse of a predetermined time after the discharge of the first source gas. At this time, the hydrogen gas is continuously introduced into the film forming apparatus 1. Accordingly, by the activated hydrogen ions H ^* , adhesion of molecules such as water and oxygen on the surface of the substrate on which the first film is formed is removed, and the interface state can be reduced.

As described above, after the surface of the substrate on which the first film is formed is cleaned by the activated hydrogen ions H ^* , the second source gas (monosilane 15 SCCM and helium diluted oxygen 1-2 SCCM) is introduced. I do. DC voltage equal to or lower than the glow discharge starting voltage (for example, 1 kV or lower,
V or more) is applied between the susceptor 2 and the gas shower head 3a. Thus, a group of high energy reactive species formed from the second source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of reactive species reaches the substrate 10 and a silicon oxide film is formed on the surface of the substrate 10.

Thereafter, the introduction of the second source gas is stopped, and the second source gas is exhausted from the processing chamber 1. Second
After the exhaust of the raw material gas, the surface of the substrate on which the silicon oxide film is formed is cleaned by the activated hydrogen ions H ^* by the hydrogen gas which is constantly introduced, and then the third raw material gas (monosilane 15 SCCM, tin hydride A gas containing (SnH ₄ ) or a tin organic compound (CH ₃ ) ₄ Sn or the like containing 15 SCCM is introduced. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thus, a group of high energy reactive species formed from the third source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10 and a tin-containing polysilicon film is formed on the surface of the substrate 10.

In the same manner as in the above step, the introduction of the third source gas is stopped, and the third source gas is discharged from the inside of the film forming apparatus 1. After evacuation of the third source gas, after the surface of the substrate on which the semiconductor film is formed is cleaned by activated hydrogen ions H ^* by the continuously introduced hydrogen gas,
A fourth source gas (monosilane 15 SCCM and helium diluted oxygen 1-2 SCCM) is introduced. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. As a result, a group of high energy reactive species formed from the fourth source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10, and a silicon oxide film is formed on the substrate surface.

As described above, according to the gas introduction method shown in FIG. 10, the surface of the substrate 10 is cleaned by the activated hydrogen ions H ^{* for} a predetermined time after various kinds of film formation, so that a high quality A semiconductor film can be formed. Further, since hydrogen gas is always introduced into the film forming apparatus 1, it is possible to prevent the thermal catalyst 5 from being oxidized and deteriorated.

Next, as shown in FIG. 11, the case where the substrate surface is first cleaned for a predetermined time, and thereafter various source gases are continuously introduced to form a film will be described.
First, the substrate 10 is carried into the film forming apparatus 1 through a gate valve (not shown), and is placed on the susceptor 2. Next, the evacuation system 1a is operated to exhaust the inside of the film forming apparatus 1 to a predetermined pressure, and the heater 2a built in the susceptor 2 is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introducing system 3 is operated to first introduce 150 SCCM of hydrogen gas into the film forming apparatus 1. Part of the introduced hydrogen gas becomes activated hydrogen ions H ^* by catalytic decomposition reaction by the thermal catalyst 5 and reaches the substrate surface to clean the surface of the substrate 10.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10, and a first silicon nitride film is formed on the surface of the substrate 10.

Thereafter, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1. In this example, after discharging the first source gas, the second source gas (monosilane 15 SCCM and helium diluted oxygen 1 to 2 SCCM) is introduced without a pause. After the formation of the silicon oxide film and the evacuation of the second source gas, a third source gas is introduced without a pause, and then a fourth source gas is introduced. Since the film is formed continuously as described above, it is possible to shift to each film forming step more quickly and form a film. In addition,
At this time, the hydrogen gas is still introduced into the film forming apparatus 1. Therefore, it is possible to prevent deterioration of the thermal catalyst due to oxidation.

In the above gas introducing method, at least before the formation of the tin-containing polysilicon film, the surface is cleaned with activated hydrogen ions H ^*, thereby reliably obtaining a high-quality tin-containing polysilicon film. It is possible and preferable.

Further, as shown in FIG. 12, a description will be given of a mode of introducing a hydrogen gas and a source gas when forming a gradient bonding film. First, the substrate 10 is carried into the film forming apparatus 1 through a gate valve (not shown), and is placed on the susceptor 2. Next, the evacuation system 1a is operated to exhaust the inside of the film forming apparatus 1 to a predetermined pressure, and the heater 2a built in the susceptor 2 is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introduction system 3 is operated, and first, hydrogen gas is introduced into the film forming apparatus 1. The introduced hydrogen gas becomes activated hydrogen ions H ^* by a catalytic decomposition reaction by the thermal catalyst 5, reaches the substrate surface, and
Perform surface cleaning.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of reactive species reaches the substrate 10, and a first silicon nitride film is formed on the substrate surface.

Thereafter, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1. In this example, the second source gas (monosilane 15 SCCM and helium diluted oxygen 1-2 SCCM) is introduced before the first source gas is completely exhausted. As described above, by gradually decreasing the introduction amount of the first source gas and gradually increasing the introduction amount of the second source gas, the first source gas is kept in the film forming apparatus 1 for a predetermined time. The gas and the second source gas are mixed while changing the occupancy. In this manner, a so-called inclined junction film in which the boundary between the first thin film and the second thin film is not clearly divided, for example, a silicon nitride-silicon oxynitride-silicon oxide film can be obtained. . However, since the MOSTFT characteristics deteriorate, the silicon oxide film as the gate insulating film and the tin-containing silicon film (polysilicon, single-crystal silicon, amorphous silicon, microcrystalline silicon, etc.) are not formed as the inclined junction. At this time, the hydrogen gas is still introduced into the film forming apparatus 1. Therefore, it is possible to prevent deterioration of the thermal catalyst due to oxidation.

As described above, activated hydrogen ions H ^* are always generated, and the surface of the substrate 10 is always cleaned. Therefore, the silicon oxide film and at least one of tin, germanium and lead are used. A transition layer of amorphous silicon is not formed at the interface of the polysilicon film containing one or more, and a high-quality semiconductor film layer can be formed.

Further, if necessary, the surface of the substrate 10 is constantly cleaned with activated hydrogen ions H ^* before the film is formed, and the surface is modified, so that molecules such as water and oxygen on the surface of the substrate 10 are formed. The adhesion is removed, the interface state is reduced, the stress between the films is low, and a high-quality thin film (silicon nitride film, silicon oxide film, tin-containing polysilicon film, or the like) can be formed. In particular, when the gate insulating film and the tin-containing polysilicon film are continuously formed, the activated hydrogen ions H
^* , The hydrogen annealing effect
A high-quality semiconductor device having a semiconductor-insulator junction structure with a low interface state density can be manufactured.

Next, the gas introduction modes shown in FIGS. 13 to 15 will be described. The gas introduction modes shown in FIGS. 13 to 15 form a film at high speed by stopping or reducing the amount of hydrogen gas as a carrier gas. First, the gas introduction mode shown in FIG. 13 will be described. FIG. 13 shows a case where the surface of the substrate 10 is cleaned each time before performing various kinds of film formation.
In this case, an introduction form of a hydrogen gas and a source gas as a carrier gas is shown.

First, the substrate 10 is carried into the film forming apparatus 1 through a gate valve (not shown), and is placed on the susceptor 2.
Next, the inside of the film forming apparatus 1 is lowered to a predetermined pressure by operating the exhaust system 1a, and the heater 2a built in the susceptor 2 is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introducing system 3 is operated to first introduce 150 SCCM of hydrogen gas into the film forming apparatus 1. A part of the introduced hydrogen gas becomes activated hydrogen ions H ^* by catalytic decomposition reaction by the thermal catalyst 5, reaches the substrate surface, and cleans the surface of the substrate 10.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10, and the formation of the silicon nitride film as the first thin film is started on the substrate surface.

After that, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. Thus, the rate of the first source gas in the film forming apparatus 1 increases, so that the formation speed of the silicon nitride film on the substrate 10 increases. After the formation of the first thin film, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1.

When the first source gas is discharged from the film forming apparatus 1, the hydrogen gas 150SCC is again used as a carrier gas.
M is introduced, and activated hydrogen ions H ^* are used to remove adhesion of molecules such as water and oxygen on the surface of the substrate 10 on which the first thin film is formed, thereby reducing the interface state. After introducing only hydrogen gas for a predetermined time, the second raw material gas (monosilane 15SC
CM and helium diluted oxygen 1-2 SCCM) are introduced. DC voltage equal to or lower than the glow discharge starting voltage (for example, 1 kV
Hereinafter, several tens of volts or more) is applied between the susceptor 2 and the gas shower head 3a. As a result, a group of high-energy reactive species formed from the second raw material gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is transferred to the substrate 10.
To the side of The group of the reactive species reaches the substrate 10, and the formation of the silicon oxide film is started on the substrate surface.

After that, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. Thus, the rate of the second source gas in the film forming apparatus 1 increases, so that the formation speed of the silicon oxide film on the substrate 10 increases. After the formation of the silicon oxide film is completed, the introduction of the second source gas is stopped, and the second source gas is discharged from the inside of the film forming apparatus 1.

When the second source gas is discharged from the film forming apparatus 1, the hydrogen gas 150SCC is again used as a carrier gas.
By introducing M and activating hydrogen ions H ^* , adhesion of molecules such as water and oxygen on the surface of the substrate 10 on which the insulating film is formed is removed, and the interface state is reduced. After introducing only hydrogen gas for a predetermined time, the third raw material gas (monosilane 15SCC) is used.
M, a gas containing tin hydride (SnH ₄ ) or a gas containing tin (CH ₃ ) ₄ Sn which is an organic compound (15 SCCM) is introduced. DC voltage equal to or lower than the glow discharge starting voltage (for example, 1 kV
Hereinafter, several tens of volts or more) is applied between the susceptor 2 and the gas shower head 3a. As a result, a group of high-energy reactive species formed from the third raw material gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is transferred to the substrate 10.
To the side of The group of the reactive species reaches the substrate 10, and the formation of the third tin-containing polysilicon film as a semiconductor film containing at least one of tin, germanium, and lead is started on the substrate surface.

After that, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. As a result, the rate of the third source gas in the film forming apparatus 1 increases, so that the formation speed of the semiconductor film on the substrate 10 increases. When the formation of the semiconductor film is completed, the introduction of the third source gas is stopped, and the third source gas is discharged from the inside of the film forming apparatus 1.

When the third source gas is discharged from the film forming apparatus 1, the hydrogen gas 150SCC is again used as a carrier gas.
M is introduced, and the activated hydrogen ions H ^* remove molecules such as water and oxygen from the surface of the substrate on which the third thin film is formed, thereby reducing the interface state. After introducing only hydrogen gas for a predetermined time, the fourth raw material gas (monosilane 15 SCCM
And helium diluted oxygen 1-2 SCCM). DC voltage equal to or lower than the glow discharge starting voltage (for example, 1 kV or lower,
Susceptor 2 and gas shower head 3a
And between them. As a result, a group of high energy reactive species formed from the fourth source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The population of the reactive species reaches the substrate 10,
The formation of the silicon oxide film is started on the surface of the substrate 10.

Thereafter, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. Thus, the ratio of the fourth source gas in the film forming apparatus 1 increases, so that the formation speed of the silicon oxide film on the substrate 10 increases. After the formation of the fourth thin film, the introduction of the fourth source gas is stopped, and the fourth source gas is discharged from the inside of the film forming apparatus 1.

As described above, according to the gas introduction method shown in FIG. 13, the surface of the substrate 10 is cleaned by the activated hydrogen ions H ^{* for} a predetermined period of time after the various kinds of film are formed. It is possible to form a semiconductor film and an insulating film. Further, in each of the thin film forming steps, since the introduction of the hydrogen gas is reduced or stopped to increase the concentration of the source gas, the thin film can be formed on the substrate 10 at a high speed, and the workability can be improved. Becomes

Next, as shown in FIG.
The case where the surface of No. 0 is cleaned for a predetermined time, and thereafter, various source gases are continuously introduced to form a film will be described. First, the film forming apparatus 1 is passed through a gate valve (not shown).
The substrate 10 is carried into the susceptor 2 and placed on the susceptor 2. Next, the inside of the film forming apparatus 1 is lowered to a predetermined pressure by operating the exhaust system 1a, and the heater 2a built in the susceptor 2 is operated.
Is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introducing system 3 is operated to first introduce 150 SCCM of hydrogen gas into the film forming apparatus 1. The introduced hydrogen gas becomes activated hydrogen ions H ^* by a catalytic decomposition reaction by the thermal catalyst 5, reaches the surface of the substrate 10, and cleans the surface of the substrate 10.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10 and the formation of the silicon nitride film is started on the substrate surface.

After that, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. As a result, the rate of the first source gas in the film forming apparatus 1 increases, so that the formation speed of the silicon nitride film on the substrate 10 increases. After the formation of the silicon nitride film, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1.

In this example, after discharging the first raw material gas, the hydrogen gas and the second raw material gas (monosilane 1
5 SCCM and 1-2 SCCM of helium diluted oxygen) are introduced. Similarly, after evacuation of the second source gas, a third source gas (tin hydride (SnH ₄ ) or an organic compound of tin (CH ₃ ) ₄ as an example of a Group 4 element) is immediately used.
A monosilane gas (15 SCCM containing Sn or the like) is introduced, and then a fourth raw material gas (monosilane 15 SCCM)
And helium diluted oxygen 1-2 SCCM) are introduced.
Since the film is formed continuously as described above, it is possible to shift to each film forming step more quickly and form a film.

In the above gas introducing method, at least before the formation of the polysilicon film, the activated hydrogen ions H ^*
By performing the surface cleaning by the method described above, it is possible to reliably obtain a high-quality polysilicon film, which is preferable.

Further, as shown in FIG. 15, a description will be given of an introduction mode of a hydrogen gas and a source gas when forming a gradient bonding film. First, the substrate 10 is carried into the film forming apparatus 1 through a gate valve (not shown), and is placed on the susceptor 2. Next, the inside of the film forming apparatus 1 is lowered to a predetermined pressure by operating the exhaust system 1a, and the heater 2a built in the susceptor 2 is operated to heat the substrate 10 to a predetermined temperature.

Then, the gas introducing system 3 is operated to first introduce 150 SCCM of hydrogen gas into the film forming apparatus 1. The introduced hydrogen gas becomes activated hydrogen ions H ^* by a catalytic decomposition reaction by the thermal catalyst 5, reaches the surface of the substrate 10, and cleans the surface of the substrate 10.

As described above, while the hydrogen gas is being supplied into the film forming apparatus 1, the gas introduction system 3 is operated to
Raw material gas (50 SCCM ammonia and monosilane 1
5 SCCM) is introduced into the film forming apparatus 1. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. Thereby, a group of high energy reactive species formed from the first source gas by the thermal decomposition reaction and the catalytic reaction of the thermal catalyst 5 is directed to the substrate 10 side. The group of the reactive species reaches the substrate 10 and the formation of the silicon nitride film as the first thin film is started on the surface of the substrate 10.

After that, the mass flow controller M is controlled to reduce or stop the supply of the hydrogen gas. As a result, the ratio of the first source gas in the film forming apparatus 1 increases, so that the rate of forming a thin film on the substrate 10 increases. After the formation of the silicon nitride film, the introduction of the first source gas is stopped, and the first source gas is discharged from the inside of the film forming apparatus 1.

In this example, before the first source gas is completely exhausted, a second source gas (15 SCCM of monosilane and 1-2 SCCM of helium diluted oxygen) is introduced and an electric field is applied. As described above, by gradually decreasing the introduction amount of the first source gas and gradually increasing the introduction amount of the second source gas, the first source gas is kept in the film forming apparatus 1 for a predetermined time. The gas and the second source gas are mixed while changing the occupancy. Thus, a so-called inclined junction insulating film in which the boundary between the silicon nitride film and the silicon oxide film is not clearly divided, for example, a silicon nitride-silicon oxynitride-silicon oxide film can be obtained. Next, a third source gas (tin hydride (SnH ₄ ) as an example of one or more of tin, germanium, and lead)
Alternatively, a monosilane gas (15 SCCM) containing (CH ₃ ) ₄ Sn, which is an organic compound of tin, and a fourth raw material gas (monosilane 15 SCCM and helium diluted oxygen 1 to 2 SCCM) same as the second raw material gas are introduced, and an electric field is generated. A continuous film is formed by applying the voltage. By stacking the insulating films by inclined bonding, the stress between the films can be reduced,
Further, by continuously forming a semiconductor film, a semiconductor device having a higher quality semiconductor-insulator junction structure can be manufactured.

In the above gas introducing method, at least before the formation of the tin-containing polysilicon film, the surface is cleaned with activated hydrogen ions H ^*, whereby a high-quality tin-containing polysilicon film is reliably obtained. It is possible and preferable.

As described above, when an insulating film or a semiconductor film is formed on the substrate 10, the film is cleaned with activated hydrogen ions H ^* at least before film formation, and a film is started by supplying a source gas. Reduce hydrogen carrier gas after film thickness,
Alternatively, since the insulating film or the semiconductor film is formed at high speed by cutting, the productivity is high and the cost can be reduced.

Before forming a film, activated hydrogen ions H ^*
The surface of the substrate 10 is constantly cleaned and the surface modification treatment is performed, so that the adhesion of molecules such as water and oxygen on the substrate surface is removed, the interface state is reduced, the stress between the films is low, and the quality is high. Film formation (silicon nitride film, silicon oxide film,
A silicon oxynitride film, a polysilicon film containing at least one of tin, germanium, and lead). In particular, when a gate insulating film and a polysilicon film containing at least one of tin, germanium, and lead are continuously formed, a hydrogen annealing effect is obtained by performing a process of exposing the film to activated hydrogen ions H ^*. Accordingly, a high-quality semiconductor device having a semiconductor-insulator junction structure with a low interface state density can be manufactured. Note that even when the hydrogen carrier gas is cut, the activated hydrogen ions H ^* are generated simultaneously with the high energy silicon atoms due to the catalytic decomposition reaction of monosilane, so that the thermal catalyst 5 is less likely to be oxidized and deteriorated.

FIG. 16 shows the configuration of the gas supply system 3 for enabling the above gas introduction in detail. In the gas supply system 3, a manual gas 3c and an automatic valve 3d are opened and closed from a supply source of hydrogen gas as a carrier gas and various source gases, so that a predetermined gas is supplied to the inside of the film forming apparatus 1 according to the situation. It is configured to lead to.

The gas supply system 3 shown in FIG. 16 has a plurality of types of carrier gas supply sources, and is configured so that a desired gas can be selected from various hydrogen-based gases as the carrier gas. That is, the manual valve 3c or the automatic valve 3d of the selected carrier gas is opened, and the film forming apparatus 1 is opened via the mass flow controller (MFC) M.
It leads to the inside. In this example, a three-way valve 3e is provided, and it is configured such that whether the selected gas is introduced into the film forming apparatus 1 or evacuated is finally determined. An inert gas, for example, a helium-diluted oxygen gas is exhausted from a separate exhaust means.

As an example of the technique for increasing the film formation speed, a technique of increasing the concentration of the source gas during the film formation has been described. However, the technique for increasing the overall gas pressure is used to perform high-speed film formation. It is also possible.

That is, in the above embodiment, a gas pressure of about 1 Pa to 20 Pa, particularly about 10 Pa is selected.
Therefore, a low gas pressure (for example, around 1 Pa) is required in the initial stage of the film formation for dense film formation (particularly, when forming a polysilicon film containing at least one of tin, germanium, and lead, prevention of formation of a transition layer of amorphous silicon). ), And by changing the gas pressure to a high value (10 to 20 Pa) in the middle, high-speed film formation can be performed.

At this time, the mixing ratio of each source gas may be constant or may be arbitrarily changed. For example, taking the case of polysilicon as an example, initially, the gas pressure is set to about 1 Pa, monosilane (1-2 SCCM) and hydrogen gas (15-20 SCCM) are set, and the gas pressure is set to 10 Pa or more halfway, and the monosilane (15- 20 SCC
M) and hydrogen gas (50 to 100 SCCM) can be formed at a high speed.

[0203] One of the greatest features of the present invention is that a semiconductor film formed continuously or at high speed, for example, a gate insulating film and a semiconductor film is subjected to laser annealing. In the laser annealing treatment of this example, when a tin-containing amorphous silicon thin film, a tin-containing microcrystalline silicon thin film, and a tin-containing polysilicon thin film that are to be crystallized are irradiated with a short-wavelength pulse laser, the laser light is applied to the tin-containing amorphous silicon thin film. Or tin-containing microcrystalline silicon thin film, absorbed only on the very surface of the tin-containing polysilicon thin film,
Thereafter, the inside of the semiconductor film is melted and recrystallized by heat conduction, or annealing is performed to make crystal grains larger.

For example, as an amorphous silicon thin film, a
When an XeCl excimer laser beam having a wavelength of 308 nm is irradiated to a -Si: H film using this film, the absorption coefficient for this wavelength reaches 10 ⁶ cm ^-1, and
Å) and is converted to heat. This heat is immediately transmitted to the inside of the semiconductor film by heat conduction. Since the surface or inside of the film is instantaneously heated to a high temperature as described above, the a-Si: H film is crystallized, and a large-grain polysilicon film is formed. For example, the mobility of the film increases significantly and the photoconductivity decreases. In addition, the impurity in the ion-implanted film is activated.

The short-wavelength pulsed laser light used in this example has a laser wavelength of 100 to 400 nm, a practical range of 150 to 350 nm, and a pulse width of 100 ns or less, specifically 10 to 50 ns, especially 20 ns.
ec. The peak intensity of the pulse is 1
0 ⁶ W / cm ² or more and ^{~10 8} W / cm ² or less, fluence (one pulse energy) of 1 J / cm ²
Or less, preferably 50 to 500 mJ / cm ² or less, specifically, a 200~300mJ / cm ^2. In this example, excimer laser annealing (ELA) is performed, but the present invention is not limited to this, and argon laser annealing (ALA) may be performed.

In this example, the shape of the laser beam is a line beam (for example, 275 × 0.3 to 0.4 m).
m ² ) is used. In addition, the area beam (for example,
A laser beam of 100 × 100 mm ² ) may be used. As described above, the gate insulating film and the semiconductor film formed continuously or at a high speed by the bias catalyst CVD method or the like are subjected to the laser annealing treatment, so that the amorphous silicon can be formed at a low temperature (room temperature) without increasing the temperature of the entire substrate 10. Large-grain polysilicon crystallization of a thin film, microcrystalline silicon, or polysilicon film, activation of carrier impurities, and the like can be performed to improve performance. Further, the manufacture of the semiconductor device becomes easy.

[0207] The laser annealing is performed on the substrate 10
Bias catalytic CVD on gate insulating film and semiconductor film
After forming a film in a film forming apparatus such as the above, the substrate 10 is introduced into a laser annealing apparatus. Laser annealing is performed under vacuum or nitrogen gas or so-called forming gas,
That is, the annealing is performed in a laser annealing apparatus into which a mixed gas of nitrogen gas and hydrogen gas is introduced.

When formed by bias catalytic CVD, the amorphous silicon film usually contains 1 to 3% of hydrogen. The film containing this amount of hydrogen is directly subjected to laser annealing without dehydrogenation. As described above, since the amorphous silicon film formed by the bias catalyst CVD contains only about 1 to 3% of hydrogen, the amorphous silicon film and the silicon oxide film for the gate insulating film are stacked. Even when laser annealing is performed directly, bumping of hydrogen does not occur. Therefore, polysilicon crystallization can be smoothly performed by laser annealing, and the interface state between the polysilicon film and the gate insulating film can be easily improved, so that characteristics such as mobility can be easily improved. It can be aimed at. In the bias catalyst CVD, the crystal structure of the film is changed from amorphous silicon to amorphous / microcrystalline silicon to
There is a feature that it is possible to control any of microcrystalline silicon to polysilicon mixed with amorphous / microcrystalline silicon. Therefore, the bias catalyst C
When a film is formed by VD, a seed (seed) for crystal growth is easily formed, and thus, there is a characteristic that silicon deposited by excimer laser treatment is easily increased in particle size.

[0209] Further, one of the greatest features of the present invention is that after an insulating film, a semiconductor film, and an electrode are formed on the substrate 10, the interface between the insulating film and the semiconductor film or the insulating film is subjected to steam annealing. There is also. This water vapor annealing treatment can be performed either when the laser annealing treatment is performed or not. Conversely, the laser annealing may be performed and the steam annealing may not be performed. In the present invention, after an insulating film and a semiconductor film are formed on the substrate 10 by a bias catalytic CVD device or the like, source / top gate / drain electrodes are formed and placed in the steam annealing chamber 31.
The inside of the steam annealing chamber 31 is set at a normal temperature to 400
Temperature, a partial pressure of 1 × 10 ² Pa or more and 1 × 10 ⁶ Pa or less, and an atmosphere containing water vapor having a saturated vapor pressure of not more than 10 seconds to 20 seconds.
Heat for less than an hour.

Hereinafter, an apparatus and a processing method for performing the steam annealing will be described. FIG. 17 shows a configuration diagram of an example of an apparatus for performing the above-described steam annealing treatment. In this case, a susceptor 32 on which the substrate 10 is arranged is arranged in a steam annealing chamber 31. The susceptor 32 is provided with a heater 32b so that the substrate 10 held on the susceptor 32 can be heated to a predetermined temperature.

[0211] The steam annealing chamber 31 is provided with an exhaust system 31a, which is connected to exhaust means (not shown) via a valve V1. The steam annealing chamber 31 is provided with a pressure gauge 34 for observing the internal pressure.

On the other hand, outside the steam annealing chamber 31, a constant temperature bath 36 having a water storage section 35 is provided, and the storage section 35 is connected by a connection pipe 37 provided with valves V2 and V3. In addition, a carrier gas supply pipe 37 to which a carrier gas is supplied is connected between the valves V2 and V3 of the connection pipe 37 via a valve V4, and the water in the thermostat 36 is connected via a valve V5. It is configured to be connected to the storage unit. Note that, in this example, the steam annealing chamber 3 is connected from the connecting pipe 37 via the valve V3.
Although the configuration is such that steam is introduced into 1, it is needless to say that a mass flow controller may be provided and introduced from the gas supply system 33 into the steam annealing chamber 31 via this controller.

In this manner, in the steam annealing chamber 31 evacuated to a high vacuum in advance, for example, while the valves V4 and V5 are closed, the valves V2 and V3 are opened.
The amount of steam set by the saturated steam pressure at the heating temperature set by the thermostat 36 is supplied to the valves V3 and V5.
A predetermined amount is sent into the steam annealing chamber 31 by vacuum suction while monitoring with the pressure gauge 34 by the opening and closing adjustment of. And in this case, the steam annealing chamber 31
Although not shown, this steam annealing chamber 31
By providing a heating means for heating the entirety, the entire steam annealing chamber 31 is heated to a dew point or more with respect to the introduced steam amount so that the steam fed into the steam annealing chamber 31 does not dew. It is desired to keep.

A method for performing a steam annealing process using the steam annealing device will be described. Substrate 10
A semiconductor film containing at least one of tin, germanium, and lead, a gate insulating film, and an electrode are formed thereon. Thereafter, the substrate 10 is placed on the susceptor 32 in the steam annealing chamber 31 shown in FIG. After the inside of the steam annealing chamber 31 is evacuated to a high degree of vacuum, the valves V2, V3 and V5 are opened, 6.5 × 10 ³ Pa of steam is introduced, and the substrate temperature is 200 to 300 ° C. and 30 to 6
Heat treatment for 0 minutes, that is, steam annealing is performed to modify the gate insulating film and modify the interface between the gate insulating film and the semiconductor film containing at least one of tin, germanium, and lead.

As described above, by performing the steam annealing, the characteristics of the interface between the gate insulating film and the semiconductor film containing at least one of tin, germanium, and lead can be effectively reduced at a low temperature. Thus, defects in the insulating film are improved, mobility is improved, and high-speed operation is realized. The effect of the steam annealing does not affect the semiconductor film itself containing at least one of tin, germanium, and lead.

The method of introducing steam for performing steam annealing is not limited to the vacuum suction described above.
Steam annealing chamber 31 pre-filled with various gases
Alternatively, steam can be introduced. As described above, when a gas other than water vapor is mixed, the heat conduction in the water vapor annealing chamber 31 is improved, and the variation in the temperature distribution is reduced. This has the effect of avoiding the disadvantage of lowering the annealing effect.

As shown in FIG. 17, the water vapor supply method includes a bubbling method in which various carrier gases are passed through the water in the storage section 35 to supply a carrier gas containing moisture into the water vapor annealing chamber 31. Can also be taken. The steam annealing is performed in the steam annealing chamber 31.
Can be performed in a sealed state, or can be performed in a carrier gas stream.

Further, the introduction of steam into the steam annealing chamber 31 for the heat treatment in steam may be performed by a spraying method using a sprayer or by applying ultrasonic vibration to generate a pulse jet water. Can be. This method has an advantage that the water droplet particles are extremely small and can be easily gasified in the steam annealing chamber 31.

Further, various gases such as oxygen, nitrogen, hydrogen, nitric oxide and nitrous oxide may be used as the gas to be mixed with water vapor. In particular, when oxygen is used, heat treatment in a single gas has an effect of modifying an insulating film having a large dielectric dispersion. Therefore, by using this as a mixed gas, the effect of reforming can be more effectively improved. Can be.

In this case, the partial pressure is set to 1.3 × 10 ² Pa
The value is set to 1.0 × 10 ⁵ Pa or less. 1.3
The reason why the pressure is set to × 10 ² Pa or more is that 1.3 × 10 ² Pa or more is necessary for improving the dielectric dispersion of the insulating film by oxygen.
Although the these nitrogen or the like is mixed with water vapor is caused an effect of preventing the resulting condensation in a portion has a lower temperature distribution within the heat treatment container, 1.0 × 10 ⁵ P
Below a (less than or equal to the water vapor pressure), the effect is reduced. The reason why the pressure is set to 1.0 × 10 ⁵ Pa or less is that if the pressure exceeds 1.0 × 10 ⁵ Pa, the apparatus becomes complicated in securing the pressure resistance of the heat treatment vessel, and a large-scale apparatus is required, which is not practical. Also, the partial pressure of steam is 1.3 × 10
^In the region of ² Pa or less, increasing the pressure can shorten the annealing time. However, if the pressure is exceeded, the effect of increasing the pressure gradually decreases.

The semiconductor to be modified by the steam annealing treatment of the present invention is not limited to silicon. When the semiconductor is a laminated thin film such as germanium, a SiGe solid solution, or a SiGe superlattice, it may be a single crystal, an amorphous ( The same effect can be obtained by applying the present invention to obtain amorphous, polycrystalline and the like. The insulating film is not limited to the gate insulating film described above, but may be an interlayer insulating film, a surface protective insulating film,
The present invention can be applied to a case where a semiconductor layer device having a planarization insulating film or the like is obtained. The insulating film is not limited to the silicon oxide film. For example, a silicon oxynitride film, a silicon nitride film formed at a substrate temperature of 600 ° C. or less at the time of film formation, or a silicon oxide film described above. When the present invention is applied to the case of obtaining a semiconductor device having two or more kinds of laminated structures, similar effects can be obtained. Further, in an interlayer insulating film or the like, SOG (silicon on gray) is used.
The present invention can be applied to a case where a semiconductor device having an insulating film by ss) or the like is obtained. That is, in each of these insulating films, the stabilization of the characteristics of the element may be impaired by the defects and moisture in the film. However, in the case of obtaining a semiconductor device having these structures, the characteristics of the characteristics can be reduced by applying the manufacturing method of the present invention. A stabilized semiconductor device can be obtained.

After forming the source, top gate, and drain electrodes, the above-described steam annealing is performed, and the substrate 10 is carried into the plasma apparatus. 10Pa inside the plasma device
A high-frequency voltage (or a DC voltage) is applied between the substrate 10 and the counter electrode at a pressure of about several hundred Pa to generate a plasma discharge, thereby cleaning the surface of the substrate 10, particularly the electrode surface. In this case, the plasma generation voltage is 1 kV or more, especially several kV to several tens kV, for example, 1 kV.
0 kV. As a gas to be introduced, an argon gas, a mixed gas of argon and hydrogen, a mixed gas of argon and nitrogen, and a mixed gas of argon, hydrogen, and nitrogen are used.
At this time, the amount of hydrogen, nitrogen, or hydrogen and nitrogen mixed with argon is about 5 to 10 mol% of argon. Hereinafter, the cleaning for removing the oxide film and the hydroxide film on the surfaces of the source, top gate, and drain electrodes by using plasma is referred to as “plasma cleaning”.

In this example, the substrate 10 is configured to be subjected to plasma cleaning, but may be configured to be cleaned by sputtering. In the present invention, the term “sputter cleaning” means that after the above-described steam annealing is performed on the substrate 10 after the electrode is formed, the inside of the sputtering apparatus is set to a predetermined gas pressure, a gas is introduced, and the surface of the substrate 10, particularly, the electrode surface is cleaned by sputtering. To do. In this example, the predetermined pressure is
0.5 to 1.0 Pa. As a gas to be introduced, an argon gas, a mixed gas of argon and hydrogen, a mixed gas of argon and nitrogen, and a mixed gas of argon, hydrogen, and nitrogen are used. At this time, the amount of hydrogen, nitrogen, or hydrogen and nitrogen mixed with argon is 5 to 10 mol% of argon.
Degree.

By the plasma cleaning or the sputter cleaning, the oxide film or the hydroxide film formed on the thin film by the annealing treatment in the atmosphere containing water vapor after the formation of the electrode can be removed. External extraction (gold wire bonding, electroless Ni
/ Au plating + solder bump) is improved, and the characteristics, quality, reliability, etc. are improved.

In this embodiment, the semiconductor film formation on the substrate 10, laser annealing, water vapor annealing, and plasma cleaning or sputter cleaning of the electrodes are performed in different containers. .
However, if steam annealing is performed before electrode formation,
The vacuum container may be configured as a container having a plurality of chambers as shown in FIGS. 18 to 20, and semiconductor film deposition, laser annealing, and steam annealing may be performed in different chambers in the container. . As described above, when the steam annealing is performed before the electrode is formed, the electrode is not corroded by the steam, and therefore, it is not necessary to perform the plasma cleaning or the sputter cleaning of the electrode.

The vacuum chamber 1 shown in FIG. 18 has a load lock chamber 41 as an entrance for introducing the substrate 10 into the vacuum chamber 1, a separation chamber 42, a film forming chamber 43, a laser annealing chamber 44, And an annealing chamber 45. The separation chamber 42 is located at the center of the vacuum vessel 1, and has a load lock chamber 41 and a laser annealing chamber 4.
4, provided so as to be adjacent to each of the steam annealing chambers 45, and configured such that when the substrate 10 is introduced into each chamber, it temporarily passes through the separation chamber 42.

A procedure for forming a semiconductor film containing at least one of tin, germanium, and lead using a vacuum vessel shown in FIG. 18 and then performing laser annealing to form an insulating film. explain. First, the interiors of the separation chamber 42, the film forming chamber 43, the laser annealing chamber 44, and the steam annealing chamber 45 are evacuated until a predetermined pressure is reached, and the doors between the chambers are closed.

The door on the lower side of the load lock chamber 41 is opened, and the substrate 10 is introduced into the load lock chamber 41. Thereafter, the door is closed, and the load / lock chamber 41 is evacuated until a predetermined pressure is reached. When the pressure inside the load lock chamber 41 reaches a predetermined pressure, the door between the load lock chamber 41 and the separation chamber 42 is opened, and the substrate 10 is transferred to the separation chamber 42.

Thereafter, the door between the load / lock room 41 and the separation room 42 is closed, and the separation room 42 is closed.
The door between the separation chamber 42 and the film formation chamber 43 is opened, the substrate 10 is transferred to the film formation chamber, and the door between the separation chamber 42 and the film formation chamber 43 is closed. In the film forming chamber 43, the semiconductor film and the insulating film containing at least one of tin, germanium, and lead are formed on the substrate 10 by the bias catalyst CVD or the like of the present invention.
In this embodiment, a polysilicon film containing silicon, a silicon nitride film, and a silicon oxide film are formed. Thereafter, the door between the separation chamber 42 and the film forming chamber 43 and the door between the separation chamber 42 and the laser annealing chamber 44 are opened, and the substrate 10 is transferred to the laser annealing chamber 44.

The door between the separation chamber 42 and the laser annealing chamber 44 is closed, and the formed film is subjected to laser annealing. When the laser annealing process is completed, the door between the separation chamber 42 and the film forming chamber 43 and the door between the separation chamber 42 and the laser annealing chamber 44 are opened again, and the substrate 10 is transferred to the film forming chamber 43.

The door between the separation chamber 42 and the film forming chamber 43 is closed. In the film forming chamber 43, an insulating film, in this example, a silicon oxide film is formed on the substrate 10 by bias catalyst CVD or the like. When the film formation is completed, the door between the separation chamber 42 and the film formation chamber 43 and the door between the separation chamber 42 and the steam annealing chamber 45 are opened, and the substrate 10 is transferred to the steam annealing chamber 45.

The door between the separation chamber 42 and the steam annealing chamber 45 is closed, and the formed film is subjected to steam annealing. After the steam annealing process is completed, the door between the separation chamber 42 and the steam annealing chamber 45 and the door between the separation chamber 42 and the load lock chamber 41 are opened, and the substrate 10 is transferred to the load lock chamber 41. I do. The door between the separation chamber 42 and the load lock chamber 41 is closed, and the inside of the load lock chamber 41 is returned to the atmospheric pressure.

When the inside of the load lock chamber 41 returns to the atmospheric pressure, the lower door of the load lock chamber 41 is opened, and the substrate 10 is taken out of the vacuum vessel. In the case where film formation, laser annealing, and steam annealing are performed in a multi-chamber vacuum vessel shown in FIG. 18, the feature is that film formation, laser annealing, and steam annealing can be performed continuously. is there.

The vacuum vessel shown in FIG.
VD, high density bias catalytic CVD, bias decompression CV
The method can be used in forming a semiconductor film by any of D and bias normal pressure CVD. Each of these C
The semiconductor film and the insulating film (silicon nitride film,
When a silicon oxide film, a silicon oxynitride film, or a silicon-based film containing at least one of tin, germanium, and lead) is formed, different source gases are used depending on the type of thin film to be formed. 43.

When the steam annealing step is not performed, a semiconductor film formation, a laser annealing process, and an insulation film formation using the vacuum container shown in FIG. 18 are performed using the vacuum container shown in FIG. Similarly to the above, steps by each CVD can be performed. The vacuum vessel shown in FIG.
Lock chamber 41, separation chamber 42, film forming chamber 43
And a vacuum annealing chamber shown in FIG. 18 except that a laser annealing chamber 44 and a steam annealing chamber 45 are not provided. The vacuum vessel shown in FIG. 19 may be provided with a steam annealing chamber 45 instead of the laser annealing chamber 44. The vacuum container thus configured can be used when laser annealing is not performed.

The vacuum vessel shown in FIG.
A lock chamber 41, a separation chamber 42, a semiconductor film deposition chamber 46, an insulating film deposition chamber 47, and a laser annealing chamber 44 are provided. When the vacuum container shown in FIG. 20 is used, a semiconductor film containing at least one of tin, germanium, and lead is formed in the semiconductor film formation chamber 46, and the insulating film is formed. This is performed in the membrane chamber 47. Except for these points, it is the same as semiconductor film formation, laser annealing, and insulation film formation containing at least one of tin, germanium, and lead when the vacuum vessel shown in FIG. 18 is used. The semiconductor film can be formed by the respective steps of CVD. The vacuum vessel shown in FIG. 20 may be provided with a steam annealing chamber 45 instead of the laser annealing chamber 44. Further, both the laser annealing chamber 44 and the steam annealing chamber 45 may be provided.

In this way, various thin films are formed on the substrate 10. The formation of the thin film is not limited to the thin film forming apparatus S shown in FIG. In FIG. 21, another embodiment of the thin film forming apparatus S will be described. In this embodiment, the same members as those in the above embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 21 shows a multi-chambered CVD.
1 is a schematic view of a thin film forming apparatus S. The thin-film forming apparatus S including a multi-chamber according to the present embodiment includes, for example, three chambers (A, B, and C), a cassette station CS, and a robot R. , C. And
In each of the chambers (A, B, C), a thermal catalyst 5 is disposed between the susceptor 2 and the gas supply side so that an electric field can be applied between the susceptor 2 and the gas supply side. Have been.

In the multi-chamber shown in FIG. 21, a thin film is formed by bias catalytic CVD as follows. Here, an example in which a silicon nitride film and a silicon oxide film for a protective film, a polysilicon film containing tin, and a silicon oxide film and a silicon nitride film for a gate insulating film are formed is described as an example. First, each chamber (A, B,
In C), hydrogen as a carrier gas is supplied to heat the thermal catalyst to a predetermined temperature (for example, 1700 to 1800 ° C.) and stand by. For example, in chamber A, ammonia is mixed with monosilane as a raw material gas. The substrate 10 is applied with a DC voltage (for example, 1 kV or less, several tens of V or more) equal to or lower than the glow discharge starting voltage.
A silicon nitride film having a predetermined thickness is formed thereon. Next, substrate 1
0 is transferred to a B chamber, a mixture of monosilane and helium-diluted oxygen is introduced as a raw material gas, and a DC voltage (for example, 1 kV or less, several tens of V or more) equal to or less than a glow discharge starting voltage is applied, and a predetermined A silicon oxide film having a thickness is formed. Next, the substrate 10 is transferred to a C chamber, and monosilane and tin hydride (SnH ₄ ) or an organic compound of tin (CH ₃ ) ₄ Sn are introduced as source gases,
A tin-containing polysilicon film having a predetermined thickness is formed on the substrate 10 by applying a DC voltage (for example, 1 kV or less, several tens V or more) equal to or less than the glow discharge starting voltage. Furthermore, substrate 1
0 is transferred to the B chamber to form a silicon oxide film of a predetermined thickness on the substrate 10, and if necessary, the substrate 10 is transferred to the A chamber to form a silicon nitride film of a predetermined thickness.

When the gas introduction mode shown in FIGS. 10 to 12 is adopted and a fixed amount of hydrogen gas as a carrier gas is continuously introduced into the film forming apparatus 1 and a multi-chamber is used, Activated hydrogen ions H
^In order to expose to ^* , a room for temporarily disposing the substrate 10 while moving from one chamber to the other chamber may be separately provided.

In this embodiment, a bias catalytic CVD apparatus as described below can be used in addition to the bias catalytic CVD apparatus shown in FIGS. 1 to 3 or 21. Except for the hot wall LPCVD method, each CVD apparatus is basically configured such that the substrate is placed flat on a susceptor or a hot plate, and the reaction gas uniformly contacts the surfaces thereof.

As a bias catalytic CVD device, for example,
It is possible to use a horizontal bias catalytic CVD apparatus in which the susceptor 2 is disposed substantially horizontally in the apparatus, the substrate is mounted on the surface of the susceptor, and gas is supplied from the lateral direction. In order to increase the chance of each substrate contacting the gas flow, the susceptor may be inclined so that the side supplying the gas is lower. The thermal catalyst 5 is disposed on the susceptor so as to cover the upper surface of the substrate, and is configured to be able to apply an electric field between the susceptor and the gas supply side.

A vertical (pancake-type) CVD apparatus in which a horizontally arranged disk-shaped susceptor is rotated around the center of the susceptor and gas is supplied vertically from above the susceptor to the susceptor. It can also be used. The thermal catalyst is disposed on the upper surface of the substrate, and is configured to be able to apply an electric field between the susceptor and the gas supply side.

A cylinder type (barrel type, drum type) CVD apparatus in which a substrate (a wafer in this example) is loaded on the outside or inside of a cylinder as a susceptor can be used. The cylinder has a vertical surface on which the substrate is mounted, and is configured to be rotatable around the vertical direction as an axis. The substrate is mounted on the cylinder so as to be vertical, and the reaction gas is supplied from above the cylinder. When performing the bias catalytic CVD, the position above the cylinder,
That is, a thermal catalyst is provided at a predetermined position on the side where the reaction gas is introduced, and is configured so that an electric field can be applied between the cylinder and the gas supply side.

A radial type bias catalytic CVD apparatus using a susceptor having a radial cross section can also be used. The susceptor has a shape in which a vertical plate-like body is joined so as to have a radial cross section, and is configured to be rotatable around the center of the radial shape. The substrate is mounted vertically on the vertical plate, and the reaction gas is supplied from above the susceptor. A thermal catalyst is arranged at a position above the susceptor, that is, at a predetermined position on the side where the reaction gas is introduced, so that an electric field can be applied between the susceptor and the gas supply side.

Further, a hot wall type bias catalytic CVD apparatus in which a CVD apparatus is disposed in a predetermined space in a furnace can be used. The holding of the substrate is performed by various known means such as hanging by a jig or using a susceptor such as a multi-stage cassette for holding the substrates side by side. A thermal catalyst is disposed at a predetermined position on the side where the reaction gas is introduced, and is configured to be able to apply an electric field between the susceptor and the gas supply side.

According to the above-described bias catalyst CVD thin film forming apparatus, a silicon thin film containing at least one of tin, germanium, and lead, such as polycrystalline silicon, single crystal silicon, amorphous silicon, and microcrystalline silicon, Silicon germanium, silicon carbide, semiconductor thin films of compound semiconductors (gallium arsenide, gallium phosphide, gallium nitride, etc.), silicon oxide, impurities (phosphorus silicate glass (PSG), boron silicate glass (B
SG), boron phosphorus silicate glass (BPSG), etc.)
Containing silicon oxide, silicon nitride, silicon oxynitride,
Insulator thin films such as molybdenum oxide, titanium oxide, tantalum oxide, aluminum oxide, and indium oxide; refractory metals (tungsten, titanium, tantalum, molybdenum, etc.);
Conductive nitride film (tungsten nitride, titanium nitride, tantalum nitride, molybdenum nitride, etc.), metal thin film (metal silicide, copper, aluminum, etc.), alloy thin film (aluminum
Silicon or aluminum-silicon-copper).

The relationship between the thin films formed by the various CVD thin film forming apparatuses and the source gases (reactive gases) is as follows. As the carrier gas, a helium gas, a hydrogen gas, an argon gas, a mixed gas of a hydrogen gas and a helium gas, a mixed gas of a hydrogen gas and an argon gas, or the like is suitably used.

[0249] 1. For the film formation of Si, SiH ₄ , SiHC
_{l 3, SiH 2 Cl 2,} SiCl 4, the SiH ₆ is used.

[0250] 2. SiO₂The film of SiH₄, Si
HCl₂, SiH₂Cl₂, SiCl ₄, SiBr₄,
SiI₄, SiF₄, Si (OC₂H₄)₄, Si (O
C₂H ₅)₄, (C₂H₅) Si (OC₂H₅)₃, C
₅H₁₁Si (OC₂H₅)₃, C₆H₅Si (OC₂
H₅)₃, (CH₃)₂Si (OC₂H₃)₂as well as
O₂, NO, N₂O, NO₂, CO₂+ H₂, H₂O
Used.

[0251] 3. BPSG, BSG, PSG, AsSG
The film of the above-mentioned 2 source gas (SiH₄, SiHCl
₂, SiH₂Cl₂, SiCl₄, SiBr₄, SiI
₄, SiF₄, Si (OC₂H₄)₄, Si (OC₂H
₅)₄, (C₂H₅) Si (OC₂H₅)₃, C₅H
₁₁Si (OC₂H₅)₃, C₆H₅Si (OC
₂H₅) ₃, (CH₃)₂Si (OC₂H₃)₂And O
₂, NO, N₂O, NO₂, CO ₂+ H₂, H₂O)
, PH₃, B₂H₆, AsH₃, PO (OC
H₃)₃, B (OCH₃)₃, B (OC₃H₇)₃Etc.
Mix gas.

[0252] 4. For film formation of SiN _X , SiH ₄ , Si
H ₆ , SiHCl ₃ , SiHCl ₂ , SiH ₃ Cl, S
A source gas in which NH ₃ , N ₂ H ₄ , and N ₂ are mixed with iCl ₄ , SiBr _4, or the like is used. The carrier gas is A
r, He, etc. are preferred.

[0253] 5. SiO_XN_YThe above 2, 4
The same source gas as that used in Example 1 is used. That is, SiH₄, SiH
Cl₂, SiH₂Cl₂, SiCl₄, SiBr₄, S
iI₄, SiF₄, Si (OC₂H₄)₄, Si (OC
₂H₅)₄, (C₂H₅) Si (OC₂H₅)₃, C₅
H₁₁Si (OC₂H₅)₃, C₆H₅Si (OC₂H
₅)₃, (CH₃)₂Si (OC₂H₃)₂And O₂,
NO, N₂O, NO₂, CO₂+ H₂, H₂Each raw material of O
Gas, SiH₄, SiH₆, SiHCl₃, SiHCl
₂, SiH₃Cl, SiCl₄, SiBr₄Etc. N
H₃, N₂H₄, N₂Using raw material gas mixed with
Can be.

[0254] 6. For Al film formation, use AlCl₃, Al
(CH₃)₃(TMA), Al (C₂H ₅)₃(TE
A), Al (OC₃H₇)₃Can be used. What
Contact, H as reducing gas₂Is preferred.

[0255] 7. For the film formation of Al ₂ O _3-X , the above 6 source gases (AlCl ₃ , Al (CH ₃ ) ₃ (TMA),
Al (C ₂ H ₅ ) ₃ (TEA), Al (OC
₃ H ₇ ) A raw material gas obtained by adding CO ₂ + H ₂ , O ₂ , and H ₂ O to ₃ ) can be used.

[0256] 8. For the film formation of In ₂ O ₃ , In (C
A source gas to which H ₃ ) ₃ (TMI), In (C ₂ H ₅ ) ₃ (TEI), O ₂ , H ₂ O, and CO ₂ are added can be used.

[0257] 9. For film formation of high melting point metal, for example, fluoride
Classification by fluoride, chloride and organic compound, fluoride film formation
MoF₆, WH₆M for raw material gas and chloride film formation
oCl ₅, WCl₆, TaCl₅, TiCl₄, ZrC
l₄Ta (OC)₂H
₅)₅, (PtCl₂)₂(CO)₃, W (CO)₆,
Mo (CO)₆Raw material gas can be used.

[0258] 10. For the silicide film formation, the source gas of the above 9 ９ MoF ₆ , WH ₆ source gas for the fluoride film formation, and MoCl ₅ , WCl ₆ , TaCl for the chloride film formation.
₅ , TiCl ₄ , ZrCl ₄ source gas, and Ta (OC ₂ H ₅ ) ₅ , (PtCl ₂ ) ₂ (C
O) ₃ , W (CO) ₆ , and Mo (CO) ₆ are mixed with a silane-based gas such as SiH ₄ or SiH ₆ as a raw material gas.

(11) For TiN film formation, TiCl ₄ + N
₂ (+ NH ₃ ) source gas and TiON
A source gas obtained by adding O ₂ and N ₂ O to Cl ₄ + N ₂ (+ NH ₃ ) can be used.

[0260] 12. Hexafluoroa
Cetyl acetonate copper Cu (HFA) ₂And C (HF
A)₂+ H₂O, chelate compound material (Cu (DP
M)₂, Cu (AcAc)₂, Cu (FOD)₂, Cu
(PPM)₂, Cu (HFA) TMVS) and other source gases
Can be used.

13. Formation of Al-Si, Al-Si-Cu
In the film, the above 6 source gases (AlCl ₃, Al (C
H₃)₃(TMA), Al (C₂H₅)₃(TEA),
Al (OC ₃H₇)₃) To one source gas (SiH₄, S
iHCl₃, SiH₂Cl₂, SiCl₄, SiH₆)
And 12 source gases (hexafluoroacetylacetone)
Copper copper (HFA)₂And C (HFA)₂+ H₂O,
Chelate compound material (Cu (DPM)₂, Cu (Ac
Ac)₂, Cu (FOD)₂, Cu (PPM)₂, Cu
(HFA) TMVS), etc.) as raw material gas
Can be used. Due to the above source gases,
Thus, it becomes possible to form each of the thin films described above.

In the above-described thin film forming apparatus, by appropriately using each of the above-mentioned source gases, a silicon semiconductor device, a silicon semiconductor integrated circuit device,
Germanium semiconductor device, silicon-germanium semiconductor integrated circuit device, compound semiconductor device, compound semiconductor integrated circuit device, silicon carbide semiconductor device, silicon carbide semiconductor integrated circuit device, liquid crystal display device, organic / inorganic electroluminescence display device, plasma display panel (PD
P) device, field emission display (FE)
D) It is possible to manufacture devices, light emitting polymer displays, light emitting diode displays, CCD sensor devices, MOS sensor devices, high dielectric constant and ferroelectric memory devices, solar cells and the like.

Next, a method of forming a thin film according to the present invention and further forming a semiconductor thin film semiconductor using the formed thin film layer will be described based on specific examples. In each specific embodiment, the film formation is performed at a desired quality and speed by changing the introduction time and timing of the carrier gas and the source gas as described above.

(Embodiment 1) As Embodiment 1, an embodiment of a method of manufacturing a top gate type polysilicon CMOS TFT using a vacuum chamber having a single chamber will be described. In this example, a polysilicon film formed by a bias catalytic CVD method is subjected to an excimer laser annealing treatment and / or a steam annealing treatment.

In this embodiment, the thin film is formed by the bias catalyst CVD. However, the present invention is not limited to this.
VD and bias normal pressure CVD are also applicable to this embodiment.

The material of the substrate 10 is selected according to the substrate temperature during the TFT forming process. When the bias catalytic CVD method is adopted, the substrate temperature in the process of forming the polysilicon film and the insulating film is maintained at a relatively low temperature of about 200 to 400C. Therefore, in the case where a glass substrate such as borosilicate glass or aluminosilicate glass can be used in the TFT forming apparatus, a borosilicate glass substrate or an aluminosilicate glass substrate can be used. At this time,
It is possible to increase the size of the substrate in terms of cost, for example, a size of 500 × 600 mm, 0.5 to 1.1
mm thickness. In the case of a low temperature, a heat-resistant organic resin substrate may be used. Further, an insulating substrate such as ceramics can be used.

In the case where the substrate temperature becomes relatively high at about 600 to 1000 ° C. in the TFT forming process,
A heat-resistant glass substrate such as quartz glass or crystallized glass is used. The heat-resistant glass substrate has, for example, a diameter of 15 to 30 cm.
And a thickness of 700 to 800 μm. Also,
Orientation similar to general silicon wafer
A flat (ori flat) is formed.

Next, a description will be given of a process of manufacturing a top gate type polysilicon CMOSTFT comprising the first to thirteenth steps. First, in the first step, the substrate 10 is set in the film forming apparatus 1 which is a bias catalytic CVD apparatus having a single chamber, and the exhaust system 1a is operated to exhaust the inside of the film forming apparatus 1 to a predetermined pressure. Then, the substrate 10 is heated to a predetermined temperature (about 200 ° C.) by operating the heater 2 a built in the susceptor 2. Next, 50-100 SCCM of hydrogen gas as a carrier gas is formed in the film forming apparatus 1.
Supply. Instead of the hydrogen gas, a mixed gas of argon and hydrogen, helium and hydrogen, or neon and hydrogen and containing 80 to 90 mol% of hydrogen may be supplied. The hydrogen gas is activated by contact with the thermal catalyst 5 and a part thereof becomes activated hydrogen ions H ^* , thereby cleaning the surface of the substrate 10. The gas pressure due to the supply of the hydrogen-based carrier gas and the source gas is about 0.1 to 1.0 Pa, in this example 0.5 P
a. Therefore, the mixture ratio of the hydrogen-based carrier gas and the source gas may be fixed or changed so that the gas pressure is lowered to form a dense film and vice versa for higher-speed film formation.
However, it goes without saying that this gas pressure range is restricted by the quality of the formed film and the performance of the apparatus.

Next, in a second step, a silicon nitride film 11 for a protective film is formed. In the film forming apparatus 1 to which hydrogen gas 50 to 100 SCCM is supplied, monosilane 1 to 20 SC
A source gas obtained by mixing 5 to 50 SCCM of ammonia with CM is introduced. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. In the film forming apparatus 1,
The introduced gas forms a silicon nitride film 11 for a protective film on one main surface of the substrate 10 via the thermal catalyst 5. In this example, the silicon nitride film 11 is formed to have a thickness of 50 to 200 (nm). At this time, in order to increase the ratio of the source gas in the film forming apparatus 1, the mass flow controller M is controlled to reduce the supply of the hydrogen gas during the film formation, and the silicon nitride film 11 is formed at a high speed. May be. After that, the supply of ammonia and silane into the film forming apparatus 1 is stopped.

The silicon nitride film 11 for the protective film is formed to stop Na ions from the substrate 10 when borosilicate glass, aluminosilicate glass or the like is used as the substrate 10. This is unnecessary when synthetic quartz glass is used as the substrate 10.

Next, in a third step, a silicon oxide film 12 for a protective film is formed. When the amount of hydrogen gas is reduced in the second step, 50 to 100 SCCM of hydrogen gas as a carrier gas is introduced into the film forming apparatus 1. Further, monosilane gases 1 to 2 continuously supplied into the film forming apparatus 1.
0 SCCM, helium diluted oxygen gas 1-2 SCCM
Are introduced in an appropriate mixing ratio. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a.
In the film forming apparatus 1, the introduced gas forms a silicon oxide film 12 for a protective film on the substrate 10 via the thermal catalyst 5. In this example, the silicon oxide film 12 has a thickness of 50 to 100.
(Nm) thick. At this time, in order to increase the ratio of the source gas in the film forming apparatus 1, the mass flow controller M is controlled to reduce the supply of hydrogen gas during the film formation, and the silicon oxide film 12 is formed at a high speed. May be. The supply of silane and helium diluted oxygen into the film forming apparatus 1 is stopped.

In the fourth step, a polysilicon film 13 containing at least one of tin, germanium and lead is formed. Before the formation of the polysilicon film 13 containing at least one of tin, germanium, and lead, a hydrogen gas is supplied as a carrier gas into the film forming apparatus 1. If the surface cleaning is performed by hydride ions H ^* , a high-quality polysilicon film can be reliably obtained, which is preferable.

When the polysilicon film 13 is formed,
When the hydrogen gas is reduced in the third step, the film forming apparatus 1
Inside, 50-100 SC of hydrogen gas as carrier gas
Introduce CM. At this time, monosilane gas 1 to 20 SCCM is supplied into the film forming apparatus 1. A gas containing at least one of tin, germanium and lead, for example, SnH _{4 1 to} 20S in the case of tin
Introduce CCM. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. The introduced gas forms a tin-containing polysilicon film 13 on the substrate 10 via the thermal catalyst 5. The tin-containing polysilicon film 13 of this example is formed to a thickness of 40 to 60 (nm).

At this time, if necessary, the raw material gas
Gas (monosilane (SiH₄) Or disilane (Si
₂H₆) Or trisilane (Si₃H₈) Etc.)
Phosphorus or arsenic or antimony, etc.
By mixing an appropriate amount of P-type boron, any N-type or P-type
Forming a Tin-Containing Polysilicon Film with a Type Impurity Carrier Concentration
Can be In the case of N-type, for example,
(PH₃), Arsine (AsH₃), Stibine (Sb
H₃) Is adopted, and in the case of P-type, for example, diborane
(B₂H ₆) Is adopted. At this time, in the film forming apparatus 1,
Mass flow control to increase the proportion of raw material gas
Controller M to reduce the supply of hydrogen gas during film formation.
To reduce or stop the tin-containing polysilicon film 13 at high speed.
A film may be formed.

After forming the tin-containing polysilicon film 13, the polysilicon may be made amorphous by doping or implanting silicon ions.
By doing so, a seed for crystal growth can be obtained, and a polysilicon film having a large grain size can be obtained. As described above, by amorphizing the once crystallized polysilicon film, the thermal energy absorption of laser light increases, the amorphous silicon film is easily melted during laser annealing, and crystallization by laser annealing is facilitated. Become.

When the tin-containing polysilicon film 13 is formed, the source gas is cut, the thermal catalyst 5 and the substrate are cooled to a temperature at which there is no problem, and the introduction of the carrier gas is stopped. Thereafter, after sufficiently exhausting, the pressure is returned to the atmospheric pressure by introducing nitrogen gas, the substrate 10 is taken out of the bias catalytic CVD film forming apparatus, and the formed tin-containing polysilicon film 13 is subjected to an excimer laser annealing treatment. The excimer laser annealing is performed in a laser annealing apparatus (not shown) different from the bias catalytic CVD film forming apparatus. The inside of the laser annealing apparatus is evacuated, or nitrogen gas or a so-called forming gas, that is, a mixed gas of nitrogen gas and hydrogen gas is introduced, and short-wavelength pulsed laser light is irradiated from the film forming surface side of the substrate 10. Do.

As a short-wavelength pulse laser beam used in this example,
Means that the laser wavelength is 100-400nm, practical range
Is 150 to 350 nm, and the pulse width is 10 to 50 nsec.
Among them, the one with 20 nsec is used. Also, the pulse peak
Strength is 10⁶W / cm²Above-10⁸W / cm²Less than
And the fluence (energy of one pulse)
200-300mJ / cm ²And

As such a short-wavelength pulse laser beam, X
eCl (308 nm wavelength) is used. Irradiation is performed with 95% or more overlap scanning, and the polysilicon film is preferably heated and melted. The laser beam shape is a line beam (for example, 275 × 0.3 to 0.4 m).
m ² ). During the excimer laser annealing, the substrate 10 may be heated to 300 to 400 ° C.

In this example, after the excimer laser treatment, a silicon oxide film and a silicon nitride film or a silicon oxynitride film for a top gate insulating film are successively formed. After forming a silicon oxide film and a silicon nitride film or a silicon oxynitride film, excimer laser treatment can be performed. Also in this case, the excimer laser annealing is performed by irradiating a short-wavelength pulsed laser beam from the surface side.

As described above, the silicon film is melted by excimer laser processing via the silicon oxide film and the silicon nitride film for the top gate insulating film. When the silicon oxide film and the silicon nitride film are thick, high energy irradiation is required. Therefore, it is desired to form these films as thinner films. The silicon oxide film and the silicon nitride film formed by the bias catalytic CVD method are:
It has a feature that the withstand voltage is large and sufficient insulation performance can be obtained even when formed as a thin film. Therefore, as in this example, when the silicon film is melted by excimer laser processing via the silicon oxide film and the silicon nitride film, the formation of the silicon oxide film and the silicon nitride film includes:
It can be said that a bias catalytic CVD method capable of forming a thin film is suitable.

After that, the substrate 1 was removed from the laser annealing apparatus.
0 is taken out, and the substrate 10 is placed again in the bias catalytic CVD apparatus. As a fifth step, a silicon oxide film 14 for a gate insulating film is formed. Hydrogen gas 50 to 100 SCCM as a carrier gas is introduced into the film forming apparatus 1. Also, monosilane gas 1 to 20S
CCM and helium diluted oxygen 0.1 to 2 SCCM,
Mix and introduce at an appropriate ratio. A DC voltage (for example, 1 kV or less, several tens V or more) equal to or lower than the glow discharge starting voltage is applied between the susceptor 2 and the gas shower head 3a. In the film forming apparatus 1, the introduced gas forms a silicon oxide film 14 for a gate insulating film on the substrate 10 to a predetermined thickness by thermal decomposition and catalytic action of the thermal catalyst 5. If necessary, helium-diluted oxygen may be cut and ammonia may be mixed at an appropriate ratio to form a silicon nitride film 15 having a predetermined thickness continuously. At this time, in order to increase the ratio of the source gas in the film forming apparatus 1, the mass flow controller M is controlled to reduce the supply of the hydrogen gas during the film formation, and the silicon oxide film 14 and the silicon nitride film 15 are formed. The film may be formed at a high speed.

After the film formation, the raw material gas is cut, the thermal catalyst is cooled to a temperature at which there is no problem, and the introduction of the carrier gas is stopped. After the film formation, the interface between the formed polysilicon film and the silicon oxide film and the silicon oxide film are annealed by activating hydrogen ions H ^* by cutting the source gas and introducing only the hydrogen-based carrier gas. In addition, the interface state can be reduced and the insulating film can be modified. At the time of forming the insulating thin film, the gradient gas may be formed by decreasing or increasing the inclination of each source gas.

In this embodiment, the thin film is formed using a single-chamber bias catalytic CVD apparatus. However, a thin film may be formed using a multi-chamber bias catalytic CVD apparatus. In that case, the following A ~
Using a multi-chamber vacuum vessel provided with a C chamber, the above first to fifth steps are performed in the following procedure. In the first step, a hydrogen-based carrier gas is supplied into each chamber so that the thermal catalyst 5
Is heated to a predetermined temperature. After that, the substrate 10 is transferred to the A chamber, and a monosilane gas and an ammonia gas are mixed and introduced in an appropriate ratio, and an electric field is applied to the silicon nitride film 50 to apply the electric field.
A thickness of ~ 200 (nm) is formed.

When the silicon nitride film is formed, the substrate 10
Is transferred to the B chamber, a silane-diluted oxygen gas is mixed into a monosilane gas at an appropriate ratio and introduced, and an electric field is applied to form a silicon oxide film having a thickness of 50 to 100 (nm). Thereafter, the substrate 10 is transferred to a C chamber, and a monosilane gas and SnH ₄ are mixed and introduced in an appropriate ratio, and an electric field is applied to form a tin-containing polysilicon film 40 to 60 (nm) thick.

When the polysilicon film 13 is formed, the source gas is cut, the thermal catalyst 5 is cooled to a temperature at which there is no problem, and the introduction of the carrier gas is stopped. After this, the substrate 10
Is taken out of the film forming apparatus 1 and the formed polysilicon film is subjected to excimer laser annealing.

Thereafter, the substrate 10 is placed in the chamber B again, mixed with a monosilane gas and an oxygen gas diluted with helium at an appropriate ratio, and introduced.
A thickness of about 100 (nm) is formed. Substrate 10 if necessary
Is transferred to the A chamber, a monosilane gas and an ammonia gas are mixed in an appropriate ratio and introduced, and electrolysis is applied to form a silicon nitride film 50 to 100 (nm) thick. After the film formation, the raw material gas is cut, and the thermal catalyst 5 is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut.

In the top gate type polysilicon CMOS TFT manufacturing method of this example, as described above, the supply of hydrogen gas is reduced or stopped during the film formation, and each thin film can be formed at a high speed. Even if the hydrogen-based carrier gas is stopped in the middle of the film, a large amount of activated hydrogen ions H ^* are generated due to the thermal decomposition and catalytic reaction of the silane-based gas. Even when a film is formed, the thermal catalyst 5 maintains a sufficient catalytic function. Thus, 40-
A large grain size tin-containing polysilicon layer having a thickness of 60 (nm) is formed.

Next, a MOS having the above-mentioned tin-containing polysilicon layer as at least a channel, source and drain region
A TFT is manufactured. As a sixth step, as shown in FIG. 23, in order to control the impurity concentration in the channel region for the N-channel MOS TFT,
T is masked with a photoresist r1, and P-type impurity ions (for example, boron difluoride ion BF ₂ ⁺ ) are, for example, 20 to 30 keV and 2 to 3 × 10 ¹² atoms / s.
Ions are implanted at a dose of cm ² to form a silicon layer 11 in which the conductivity type of the polysilicon layer is made P-type.

Next, as a seventh step, as shown in FIG. 24, in order to control the impurity concentration of the channel region for the P-channel MOSTFT, an N-channel M
The OSTFT is masked with a photoresist r2, and N-type impurity ions (for example, phosphorus ions P ⁺ ) are
Ion implantation is performed at ５０50 keV at a dose of ² to 3 × 10 ¹² atoms / cm ² to form a polysilicon layer 12 having an N-type polysilicon layer.

Next, in an eighth step, as shown in FIG. 25, molybdenum / metal having high heat resistance as a gate electrode material is used.
The tantalum alloy film 16 is formed by, for example,
(Nm) deposited thick.

Next, in a ninth step, as shown in FIG. 26, a photoresist r3 is formed in a predetermined pattern, and using this as a mask, the molybdenum / tantalum alloy film 16 is patterned into the shape of the gate electrode 17, and Then, the photoresist r3 is removed.

Next, in a tenth step, as shown in FIG.
Thus, the P-channel MOS TFT and the gate electrode 17 are
Example masked with photoresist r4 and is an N-type impurity
For example, As⁺The ions are, for example, 1 at 60-70 keV.
× 10^Fifteenatoms / cm ²Ion implantation at a dose of
After removing the photoresist, N₂Medium at about 1000 ° C for 20
RTA (Rapid Thermal) for 30 seconds to 30 seconds
Anneal) and N-channel MOSTFT
N⁺Source region S1 and drain region D1
Formed. Note that this RTA processing is performed for the P channel M
The activation may be performed together with the activation of the OSTFT.

Next, in an eleventh step, as shown in FIG. 28, the N-channel MOSTFT and the gate electrode 17 are masked with a photoresist r5, and a P-type impurity, for example, B ⁺ ion, for example, at 20 to 30 keV At 1 ×
Ion implantation is performed at a dose of 10 ¹⁵ atoms / cm ² , and after stripping the photoresist, 20 seconds at about 1000 ° C. in N _2.
RTA (Rapid Thermal) for 30 seconds to 30 seconds
Anneal) and P-channel MOSTFT
Are formed, respectively, of the P ⁺ type source region S2 and the drain region D2.

Next, in a twelfth step, as shown in FIG. 29, a silicon oxide film 19, for example, a phosphor silicate glass (PSG) film 20 having a thickness of 50 to 100 (nm) is formed on the entire surface by a bias catalytic CVD method or the like. For example, 200-
A silicon nitride film 21 having a thickness of 300 (nm)
A film is formed to a thickness of 0 (nm).

Next, in a thirteenth step, as shown in FIG. 30, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is applied to the entire surface including each hole at 150 ° C. by a sputtering method or the like. Deposit to a thickness of 1 μm. Then, this is patterned to form a P-channel M
A source or drain electrode S or D of each of the OSTFT and the N-channel MOSTFT and a gate contact or a wiring G are formed. Then, forming gas (N
₂ + H ₂ ), sintering is performed at 400 ° C. for 1 hour to improve ohmic contact and surface state, thereby completing each MOSTFT.

After forming the source electrode S or the drain electrode D and the gate extraction electrode or the wiring G in the thirteenth step, the following fourteenth step water vapor annealing step and the fifteenth step plasma cleaning step (or sputtering step) Cleaning step).

In this example, the laser annealing step after the fifth step, and the steam annealing step and the plasma cleaning step (or the sputter cleaning step) are provided, but the laser annealing step is provided. May not include a steam annealing step and a plasma cleaning step (or a sputter cleaning step). Further, the laser annealing process may not be provided, and a steam annealing process and a plasma cleaning process (or a sputter cleaning process) may be provided. Also, when performing the laser annealing step and the steam annealing step before forming the electrodes,
Since the electrodes are not corroded by water vapor, there is no need to perform a plasma cleaning or sputter cleaning step on the electrodes. If the laser annealing step is not performed between the fourth step (polysilicon film forming step) and the fifth step (gate insulating film (silicon oxide film) forming step), the polysilicon film 13 and the gate insulating film It is better to form the silicon oxide film 14 continuously.

The fourteenth step is a steam annealing step as described above, and is performed on the substrate 10 on which the thin film layer and the electrodes are formed.
Is subjected to steam annealing by the above-described method using vacuum suction. The substrate 10 is placed on the susceptor 32 in the steam annealing chamber 31. In the steam annealing chamber 31, the substrate 10 is heated in high-pressure steam of 2 × 10 ⁵ Pa to ³ × 10 ⁵ Pa at 180 ° C. to 200 ° C. for 30 minutes to 60 minutes to form an interface between the insulating film and the semiconductor film or The insulating film is modified.

Next, in a fifteenth step, at least the surface of the electrode pad portion of the formed film is subjected to sputter cleaning or plasma cleaning according to the procedure described in the first embodiment. After that, as in the case where the steam annealing step is not performed, 4% of the forming gas (N ₂ + H ₂ )
Sintering is performed at 00 ° C. for 1 hour to improve the ohmic contact and the surface state, thereby completing each MOSTFT.

(Embodiment 2) Further, as Embodiment 2, a bottom gate type polysilicon CMOSTF
An example of the T manufacturing method will be described. In this example, a polysilicon film is subjected to excimer laser annealing and / or steam annealing. In this embodiment, the thin film is formed by the bias catalyst CVD. However, the present invention is not limited to this, and a high-density bias catalyst CVD, a bias reduced pressure CVD, and a bias normal pressure CVD can also be applied to the embodiment. is there. The material and size of the substrate 10 are selected based on the same criteria as in the specific example 1.

The above bottom gate type polysilicon CMOS
A manufacturing process of a TFT will be described. First, a sputtered film of a molybdenum / tantalum alloy having a thickness of 300 to 400 (nm) is formed at least in the TFT region of the substrate 10. And by general-purpose photolithography and etching technology,
20-45 degree taper etching is performed to form a bottom gate electrode.

Next, a silicon nitride film and a silicon oxide film for a protective film and a bottom gate insulating film are formed on the substrate 10 by a procedure similar to the first to fourth steps of the specific embodiment 1. A polysilicon film containing tin as at least one of tin, germanium and lead, and a silicon oxide film for a protective film and for reducing laser reflection are formed. At this time, at least the silicon oxide film and the tin-containing polysilicon film of the gate insulating film are preferably formed continuously. After the film formation, the raw material gas is cut, the thermal catalyst 5 is cooled to a temperature at which there is no problem, and the introduction of the carrier gas is stopped. Thereafter, the substrate 10 is taken out of the film forming apparatus 1 and introduced into a laser annealing apparatus, and the tin-containing polysilicon film is subjected to laser annealing according to the same procedure as that of the specific example 1. However, in this example, excimer laser annealing is performed by irradiating a short-wavelength pulsed laser beam from the surface side of the formed thin film.

[0303] Thus, 40 to 60
A (nm) thick large grain size tin-containing polysilicon layer is formed. Next, a MOSTFT having a tin-containing polysilicon layer as at least a channel region is manufactured. In this example,
Since the bottom gate electrode is formed first, after forming the tin-containing polysilicon and the silicon oxide film of the protective film,
Source and drain electrodes are formed as electrodes.

Next, the P-channel MOSTFT is masked with a photoresist and a P-type impurity ion (for example, boron difluoride ion BF ₂ ⁺ ) is ion-implanted in the same procedure as in the sixth step of the specific embodiment. Then, the conductivity type of the polysilicon layer is changed to a P-type silicon layer. Next, the N-channel MOSTFT is masked with a photoresist, and N-type impurity ions (for example, phosphorus ions P ⁺ ) are implanted by the same procedure as in the seventh step of the above specific example.
The polysilicon layer is an N-type silicon layer.

Thereafter, ion implantation and R ion implantation are performed in the same procedure as in the tenth and eleventh steps of the specific embodiment 1.
Activation by TA is performed, and the N ⁺ -type source region and the drain region of the N-channel MOS TFT and the P-channel MO TFT are activated.
A P ⁺ type source region and a drain region of the STFT are formed, respectively. Next, a silicon oxide film for protection, a phosphosilicate glass (PSG) film, and a silicon nitride film are formed on the entire surface by bias catalyst CVD or the like.

Next, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole at a temperature of 150 ° C. to a thickness of 1 μm by a sputtering method or the like. Then, this is patterned and P
Channel MOSTFT and N-channel MOSTFT
To form respective source or drain electrodes. Then, at 400 ° C. for 1 hour in a forming gas (N ₂ + H ₂ ).
Time sintering is performed to improve the ohmic contact and the surface state, thereby completing each MOSTFT.

Thereafter, in the same manner as in the specific example 1, the steam annealing treatment and the plasma cleaning (or sputter cleaning) are performed. In this example, the laser annealing step, the water vapor annealing step, and the plasma cleaning step (or the sputter cleaning step) are provided. However, the apparatus may be provided with either of these steps.

In this example, since the steam annealing step is performed after the formation of the source electrode and the drain electrode,
It is configured to perform plasma cleaning (or sputter cleaning) after performing the steam annealing step. However, the steam annealing step may be performed immediately after forming the silicon oxide film for the protective film and for reducing the laser reflection. In particular, as shown in FIG. 18B, when performing film formation and water vapor annealing using a multi-chamber vacuum container having a water vapor annealing chamber 45 in addition to the film formation chamber 43 and the like, The annealing step can be performed continuously in the same apparatus. As described above, when the steam annealing step is performed before the formation of the source electrode and the drain electrode, these electrodes are not corroded by the steam, and therefore, it is not necessary to perform the plasma cleaning or the sputter cleaning step on these electrodes.

(Third Embodiment) As a third embodiment, an embodiment of a method of manufacturing a dual gate type polysilicon CMOSTFT will be described. In this example, a polysilicon film is subjected to excimer laser annealing and / or steam annealing. In this embodiment, the thin film is formed by bias catalyst CVD. However, the present invention is not limited to this, and high-density bias catalyst CVD, bias decompression CVD, and bias normal pressure CVD are also applicable to this embodiment. It is possible. The material and size of the substrate 10 are selected based on the same criteria as in the specific example 1.

Next, a dual gate type polysilicon CM
A manufacturing process of the OSTFT will be described. First, substrate 1
At least, a sputtered film of a molybdenum / tantalum alloy having a thickness of 300 to 400 (nm) is formed in at least the TFT region.
Then, taper etching of 20 to 45 degrees is performed by general-purpose photolithography and etching technology to form a bottom gate electrode.

Next, a silicon nitride film for a protective film, a bottom gate insulating film, a silicon oxide film, and at least a tin oxide film are formed on the substrate 10 by the same procedure as the first to fourth steps in the first embodiment. A polysilicon film containing tin as one or more of germanium and lead, a silicon oxide film for a top gate insulating film, and a silicon nitride film as needed. At least, the tin-containing polysilicon film and the silicon oxide film for the top gate insulating film are formed continuously. Thereafter, the substrate 10 is taken out of the film forming apparatus 1 and introduced into the laser annealing apparatus, and the tin-containing polysilicon film is subjected to laser annealing according to the same procedure as that of the specific example 1. In this manner, for example, a tin-containing polysilicon film having a large grain diameter of 40 to 60 (nm) is formed. Next, a MOSTFT having a tin-containing polysilicon layer as at least a channel region is manufactured.

According to the same procedure as that of the sixth step of the above specific example, the P-channel MOSTFT is masked with a photoresist, and P-type impurity ions (for example, boron difluoride ion BF ₂ ⁺ ) are implanted. Is a P-type silicon layer. Then, by the same procedure as the seventh step of the above specific example, the N-channel MO
The STFT is masked with a photoresist, and N-type impurity ions (for example, phosphorus ions P ⁺ ) are implanted, so that the conductivity type of the polysilicon layer is changed to an N-type silicon layer.

Next, the molybdenum / tantalum alloy film deposited by the sputtering method is patterned into the shape of the gate electrode by the same procedure as the eighth step and the ninth step of the specific example 1, and the top gate electrode is formed. Form.

Thereafter, ion implantation and R were performed by the same procedure as in the tenth and eleventh steps of the above specific example 1.
Activation by TA is performed, and the N ⁺ -type source region and the drain region of the N-channel MOS TFT and the P-channel MO TFT are activated.
A P ⁺ type source region and a drain region of the STFT are formed, respectively. Next, a protective silicon oxide film and a silicon nitride film are formed on the entire surface by bias catalyst CVD or the like.

Next, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole at a temperature of 150 ° C. to a thickness of 1 μm by a sputtering method or the like. Then, this is patterned and P
Channel MOSTFT and N-channel MOSTFT
, A source or drain electrode and a gate contact or wiring are formed. Thereafter, sintering was performed at 400 ° C. for 1 hour in a forming gas (N ₂ + H ₂ ) to improve ohmic contacts and surface states.
The STFT is completed.

Thereafter, in the same manner as in the specific example 1, steam annealing and plasma cleaning (or sputter cleaning) are performed. In this example, the laser annealing step, the water vapor annealing step, and the plasma cleaning step (or the sputter cleaning step) are provided. However, the apparatus may be provided with either of these steps.

In this example, since the steam annealing step is performed after the formation of the source electrode, the drain electrode, and the top gate electrode, plasma cleaning (or sputter cleaning) is performed after the steam annealing step. I have. However, the steam annealing step may be performed immediately after forming the silicon oxide film or the like as the top gate insulating film. In particular, as shown in FIG. 18, when performing film formation and steam annealing using a multi-chamber vacuum vessel including a steam annealing chamber 45 in addition to the film formation chamber 43 and the like, the film formation and the steam annealing step are performed. Can be performed continuously in the same apparatus. in this way,
If the steam annealing step is performed before the electrodes are formed, it is not necessary to perform the plasma cleaning or sputter cleaning step on these electrodes because these electrodes are not corroded by water vapor.

In this example, in addition to the silicon thin film, a polycrystalline semiconductor such as germanium or silicon germanium, a microcrystalline semiconductor, or an amorphous semiconductor thin film is used, and at least one of tin, germanium, and lead is used. What it contains can be formed.

(Embodiment 4) As Embodiment 4, an embodiment of a method of manufacturing a top gate type single crystal silicon CMOS TFT will be described. First, a step having an appropriate shape and dimensions is formed in at least a TFT forming region of the substrate 10, and a semiconductor film containing at least one of tin, germanium, and / or tin and a gate insulating film are formed by a bias catalytic CVD method. Is continuously formed, and the step is used as a seed for grapho-epitaxial growth. As described above, when forming at least the tin-containing polysilicon film and the silicon oxide film for the gate insulating film, a hydrogen gas is supplied as a carrier gas, and the thermal catalyst 5 is heated to be thermally decomposed. In addition, it is assumed that a catalytic action is possible, and a continuous film is formed. The material and size of the substrate 10 are selected based on the same criteria as in the first embodiment.

Next, a description will be given of a manufacturing process of a top-gate single-crystal silicon CMOSTFT including the first to twelfth processes. First, in a first step, as shown in FIG. 31, a photoresist r1 is formed in a predetermined pattern on one main surface of the substrate 10, and using this as a mask, for example, F ₄ plasma of carbon tetrafluoride (CF ₄ ) is used. ^The substrate 1 is irradiated with ⁺ ions and reactive ion etching (RIE) is performed.
A plurality of steps 10a are formed at zero.

In this case, the step 10a serves as a seed during the later-described single-crystal silicon grapho-epitaxial growth, and has a depth D of 0.05 to 0.2 μm, for example.
m, length L 5.0 to 10.0 μm, width W 2.0 to 10.
It is formed to a thickness of 0 μm.

Next, in a second step, a photoresist r1
After removal of, by the same procedure as in the specific example 1 above,
Silicon nitride film for protective film 50 to 100 (nm) thickness and protection
Deposit a silicon oxide film 50 to 100 (nm) thick for protective film
I do. Note that a silicon nitride film for a protective film is formed on the substrate 10,
A silicon oxide film is laminated, and a plurality of steps 10a are formed on this film.
It may be formed individually. However, Na from the substrate ⁺
Steps should be made so that contamination such as ions can be prevented.
It is desirable that a silicon nitride film exists at the bottom of the difference.

Next, in a third step, as shown in FIG. 32, a single crystal silicon film containing tin is formed on the substrate 10 by bias catalytic CVD. At this time, hydrogen gas 50 to 100 SCC as a carrier gas is set in the film forming apparatus 1.
M is introduced. In addition, monosilane 1 to 1 as raw material gas
20 SCCM and SnH ₄ 1-20 SCCM are introduced, and a tin-containing single crystal silicon film is formed on the substrate 10 by a bias catalytic CVD method. At this time, step 1
The single crystal silicon film 22 is epitaxially grown to a thickness of several μm to 0.005 μm (for example, 50 to 100 (nm)) by performing grapho-epitaxial growth using 0a as a seed.

[0324] If necessary, a silane-based gas (monosilane, disilane, trisilane, or the like) as a raw material gas may be used.
By mixing an appropriate amount of N-type phosphorus, arsenic, or antimony, or by mixing an appropriate amount of P-type boron,
Alternatively, a tin-containing single crystal silicon film having a P-type impurity carrier concentration can be formed. In the case of N-type, for example, phosphine, arsine, and stibine are employed, and in the case of P-type, for example, diborane is employed.

The tin-containing single-crystal silicon film 22 deposited on the substrate 10 has been epitaxially grown. This is due to a known phenomenon called graphoepitaxy. The film quality and deposition rate of the single crystal silicon film are determined by the temperature of the thermal catalyst, the temperature of the substrate, and the cleaning of the step surface of the activated hydrogen ions H ^* by the catalytic action of the thermal catalyst. The crystal orientation of the growth layer can be controlled by variously changing the shape of the step 10a. At this time, in order to increase the ratio of the source gas in the film forming apparatus 1, the mass flow controller M is controlled to reduce the supply of the hydrogen gas during the film formation, thereby forming the tin-containing single crystal silicon film at a high speed. It may be configured to be a film.

After the tin-containing single-crystal silicon film 22 is formed, as shown in FIG. 33, as a fifth step, a silicon oxide film for a gate insulating film is formed by the same procedure as in the fifth step of the above-described specific embodiment 1. 23, or, if necessary, a silicon oxide film 23 and a silicon nitride film.

Thus, the tin-containing single crystal silicon film 22 is deposited on the substrate 10 by the bias catalytic CVD method and graphoepitaxy. Next, a MOSTFT having a tin-containing single crystal silicon film as at least a channel region
Is made.

In the sixth step, as shown in FIG.
Impurity concentration in channel region for channel MOSTFT
In order to control the degree of
Mask with photoresist r2, and use P-type impurity ions (eg,
For example, boron difluoride ion BF ₂ ⁺), For example, 20
5 × 10 at ~ 30 keV¹²atoms / cm²Do
Ion-implanted in the appropriate amount, and the conductivity type of the tin-containing single crystal silicon film
Is a P-type silicon layer 11.

Next, as a seventh step, as shown in FIG. 35, in order to control the impurity concentration of the channel region for the P-channel MOSTFT, an N-channel M
The OSTFT is masked with a photoresist r3, and N-type impurity ions (for example, phosphorus ions P ⁺ ) are
Ion implantation is performed at ５０50 keV at a dose of 5 × 10 ¹² atoms / cm ² to form an N-type silicon layer ^{12 of} a tin-containing single crystal silicon film.

Next, in an eighth step, as shown in FIG. 36, a molybdenum / tantalum alloy film 24 as a gate electrode material is formed by, for example, sputtering (400 nm).
Deposit thick.

Next, in a ninth step, as shown in FIG. 37, a photoresist r4 is formed in a predetermined pattern, and using this as a mask, the molybdenum / tantalum alloy film 24 is patterned into the shape of the gate electrode 25, and The resist r4 is removed.

Next, in a tenth step, as shown in FIG.
Thus, the P-channel MOS TFT and the gate electrode 25
Example masked with photoresist r5 and is an N-type impurity
For example, As⁺The ions are, for example, 1 at 60-70 keV.
× 10^Fifteenatoms / cm ²Ion implantation at a dose of
After removing the photoresist,₂Medium at about 1000 ° C for 20
RTA (Rapid Thermal) for 30 seconds to 30 seconds
Anneal) and N-channel MOSTFT
N⁺Source region S1 and drain region D1
Formed.

Next, in an eleventh step, as shown in FIG. 39, the N-channel MOSTFT and the gate electrode 25 are masked with a photoresist r6, and a P-type impurity, for example, B ⁺ ion is applied at 30 keV, for example, at 1 keV. × 10
After ion implantation at a dose of ¹⁵ atoms / cm ² and removal of the photoresist, the film is exposed to N ₂ at about 1000 ° C. for 20 seconds to 3 seconds.
RTA (Rapid Thermal Ann) for 0 seconds
eal), and the P ^{+ of the} P-channel MOSTFT is activated.
Form source region S2 and drain region D2 are formed. Note that this RTA process is an N-channel MOSTF
Activation of T may be combined.

Next, in a twelfth step, as shown in FIG. 40, a silicon oxide film 27, for example, a 50 to 100 (nm) -thick phosphor silicate glass (PSG) film 28 is formed on the entire surface by bias catalytic CVD or the like. For example, 200-3
The silicon nitride film 29 having a thickness of 00 (nm) is
A film is formed to a thickness of 0 to 200 (nm).

Next, in a thirteenth step, as shown in FIG. 41, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is sputtered at 150 ° C. for 1 μm on the entire surface including each hole. Deposited to the thickness of
This is patterned to form a source or drain electrode S or D and a gate extraction electrode or wiring G of the P-channel MOSTFT and the N-channel MOSTFT, respectively.

Next, a steam annealing step and a plasma cleaning step (or a sputter cleaning step) are performed in the same manner as in the fourteenth step and the fifteenth step of the specific example 1. Then, forming gas (N
₂ + H ₂ ) to improve ohmic contact and surface state by sintering at 400 ° C. for 1 hour to complete each MOSTFT.

In this example, a step is formed at least in the semiconductor device formation region of the substrate, and the tin-containing single crystal silicon film is grown by grapho-epitaxial growth using the step as a seed, so that it has high electron / hole mobility. Thus, a tin-containing single crystal silicon film having excellent operability can be obtained. Further, the insulating film is modified by the steam annealing treatment, and the interface state between the gate insulating film and the tin-containing single-crystal silicon film is improved, so that a semiconductor device with more excellent operation characteristics can be obtained. Needless to say, when a tin-containing single crystal silicon film is formed, laser annealing is not performed. This is because, when the laser annealing is performed, the single crystal silicon is turned into a polysilicon film, and the characteristics are deteriorated.

(Embodiment 5) As Embodiment 5, an embodiment of a method of manufacturing a bottom gate type single crystal silicon CMOS TFT will be described. The material and size of the substrate 10 are selected based on the same criteria as in the specific example 1.

The above bottom gate type single crystal silicon CMO
The manufacturing process of the STFT will be described. First, the substrate 10
A sputtered film of molybdenum / tantalum alloy having a thickness of 300 to 400 (nm) is formed at least in the TFT region. Then, taper etching of 20 to 45 degrees is performed by general-purpose photolithography and an etching technique to form a bottom gate electrode.

Then, the thickness of the silicon nitride film 50 to 100 (nm) and the thickness of the silicon oxide film 50 for the protective film and the bottom gate insulating film are determined by the same procedure as the first to third steps of the specific embodiment 1. A thickness of about 100 (nm) is formed. At this time, a silicon oxynitride film may be formed instead of the silicon nitride film and the silicon oxide film.

Next, a photoresist is formed on one main surface of the substrate 10 in a predetermined pattern, and using this as a mask, for example, F ⁺ ions of CF ₄ plasma are irradiated, and the substrate is subjected to reactive ion etching (RIE). A plurality of steps are formed in the ten TFT formation regions. In this case, the step serves as a seed during the later-described monocrystalline silicon grapho-epitaxial growth, and has a depth D.
0.05 to 0.2 μm, length L2 to 10 μm, width W2
It may be 10 μm.

After the removal of the photoresist, single-crystal silicon containing tin as at least one of tin, germanium, and lead using the step on the substrate 10 as a seed by the same procedure as in the specific example 4 described above. Several μm film
A film having a thickness of 0.005 μm (for example, 50 to 100 (nm)) is formed.

When a tin-containing single crystal silicon film is formed,
A silicon oxide film for a protective film is formed by the same procedure as the fifth step of the specific example 1. In this manner, the substrate 1 is formed by the bias catalytic CVD method and the graphoepitaxy.
A tin-containing single crystal silicon film is deposited using the step above zero as a seed. Then, in the same manner as in the specific example 2, a MOSTFT having a tin-containing single crystal silicon film as at least a channel region is manufactured.

The fourteenth step and the first step
A steam annealing step and a plasma cleaning step (or a sputter cleaning step) are performed in the same procedure as the five steps. Then, forming gas (N ₂ +
Sintering is performed at 400 ° C. for 1 hour in H ₂ ) to improve ohmic contacts and surface states, thereby completing each MOSTFT.

(Embodiment 6) As Embodiment 6, an embodiment of a method of manufacturing a dual gate type single crystal silicon CMOS TFT will be described. The material and size of the substrate 10 are selected based on the same criteria as in the specific example 1.

The above-mentioned dual gate type single crystal silicon CM
A manufacturing process of the OSTFT will be described. A sputtered film of a molybdenum / tantalum alloy is formed in a thickness of 300 to 400 (nm) at least in the TFT region of the substrate 10. Then, taper etching of 20 to 45 degrees is performed by general-purpose photolithography and an etching technique to form a bottom gate electrode.

Then, the thickness of the silicon nitride film 50 to 100 (nm) and the thickness of the silicon oxide film 50 for the protective film and the bottom gate insulating film are determined by the same procedure as the first to third steps of the specific embodiment 1. A thickness of about 100 (nm) is formed. At this time, a silicon oxynitride film may be formed instead of the silicon nitride film and the silicon oxide film.

Next, a photoresist is formed on one principal surface of the substrate 10 in a predetermined pattern, and using this as a mask, for example, F ⁺ ions of CF ₄ plasma are irradiated, and the substrate is subjected to reactive ion etching (RIE). A plurality of steps are formed in the ten TFT formation regions. In this case, the step serves as a seed during the later-described monocrystalline silicon grapho-epitaxial growth, and has a depth D.
0.05 to 0.2 μm, length L2 to 10 μm, width W2
It may be 10 μm.

Next, a single crystal silicon film containing at least tin, germanium, and / or tin as one or more of tin is used as a seed by using a step on the substrate 10 as a seed by a procedure similar to that of the specific example 4 described above. ~ 0.005μm
(E.g., 50 to 100 (nm)) is grown by grapho-epitaxial growth. In this manner, a single-crystal silicon film is deposited using the steps on the substrate 10 as seeds by the bias catalytic CVD method and graphoepitaxy.

Next, a MOSTFT having a tin-containing single crystal silicon film as at least a channel region is manufactured in the same manner as in the specific example 3. After the tin-containing single crystal silicon film is formed, the silicon oxide film for the top gate insulating film, or the silicon oxide film and the silicon nitride film as necessary, are formed by the same procedure as the fifth step of the specific example 1. Form a film. At this time, a silicon oxynitride film may be formed instead of the silicon nitride film and the silicon oxide film.

Next, the source and drain regions of the silicon oxide film or silicon nitride film for the top gate insulating film are opened, and a molybdenum / tantalum alloy sputter film is formed on the entire surface. To form source, drain and top gate electrodes.

In this embodiment, after the formation of the top gate, the source electrode, and the drain electrode, a steam annealing step and a plasma cleaning step (or a sputter cleaning step) are performed in the same manner as in the specific example 1. Thereafter, 400 in forming gas (N ₂ + H ₂ )
Sintering is performed at 1 ° C. for 1 hour to improve the ohmic contact and the surface state, thereby completing each MOSTFT.

(Specific Example 7) As a specific example 7, a top gate type single crystal silicon CMO obtained by forming a single crystal silicon film by heteroepitaxial growth.
An example of the STFT manufacturing method will be described. First, a hydrogen gas as a carrier gas is supplied to at least the TFT formation region of the substrate 10 by a bias catalytic CVD method or the like, and the thermal catalyst is heated so that thermal decomposition and catalytic action are possible. A material layer (crystalline sapphire film or the like) having good lattice matching with the semiconductor (single crystal silicon) is formed, and the material having good lattice matching is heteroepitaxially grown as a seed. The material and size of the substrate 10 are selected based on the same criteria as in the first embodiment.

The above-described steps of manufacturing the top gate type single crystal silicon CMOSTFT including the first to thirteenth steps will be described in more detail. First, the first step, the second
In the process, the silicon nitride films 50 to 200 for the protective film are formed in the same procedure as the first and second processes of the above specific embodiment.
(Nm) Thickness is formed.

Next, in a third step, a material layer (such as a crystalline sapphire film) having a good lattice match with the single crystal semiconductor (single crystal silicon) is formed. That is, as shown in FIG.
On one main surface of the substrate 10, a bias catalytic CVD method or the like is used.
A crystalline sapphire thin film 50 is formed to a thickness of 5 to 200 (nm). The crystalline sapphire thin film 50 is produced by oxidizing a trimethylaluminum gas with an oxidizing gas (oxygen / water) and crystallizing the same.

Next, in a fourth step, a single crystal silicon film 22 containing at least tin as one or more of tin, germanium, and lead is formed. When the amount of hydrogen gas is reduced or stopped in the second step, 50 to 100 SCCM of hydrogen gas as a carrier gas is introduced into the film forming apparatus 1. In addition, monosilane 1 to 20S as source gas
CCM and tin hydride (SnH ₄ ) 1 to 20 SCCM are introduced, and a tin-containing single crystal silicon film is formed on the substrate 10 by a bias catalytic CVD method. At this time, as shown in FIG. 43, a single-crystal silicon film 22 is epitaxially grown to a thickness of 0.005 μm to several μm (for example, 50 to 100 (nm)) on the entire surface of the crystalline sapphire thin film 50.

As described above, silicon is heteroepitaxially grown using the crystalline sapphire thin film 50 as a seed, and is deposited as, for example, a tin-containing single crystal silicon film 22 having a thickness of about 50 to 100 (nm). in this case,
Since sapphire has almost the same lattice constant as single crystal silicon, silicon grows heteroepitaxially on the crystalline sapphire thin film 50.

If necessary, a silane-based gas (monosilane, disilane, trisilane, etc.) as a source gas may be used.
By mixing an appropriate amount of N-type phosphorus, arsenic, or antimony, or by mixing an appropriate amount of P-type boron,
Alternatively, a single crystal silicon film having a P-type impurity carrier concentration can be formed. In the case of N-type, for example, phosphine, arsine, and stibine are employed, and in the case of P-type, for example, diborane is employed.

At this time, in order to increase the ratio of the source gas in the film forming apparatus 1, the mass flow controller M is controlled to reduce the supply of the hydrogen gas during the film formation, and the tin-containing single crystal silicon film is formed. You may comprise so that a film may be formed at high speed.

Thereafter, as shown in FIG. 44, as a fifth step, a silicon oxide film 23 for a gate insulating film is formed by the same procedure as in the fifth step of the specific example 1.
At this time, the tin-containing single crystal silicon film and the silicon oxide film for the gate insulating film are formed continuously. After these films are formed, a silicon nitride film may be formed as necessary. Further, instead of forming the silicon oxide film and the silicon nitride film, a silicon oxynitride film may be formed. After the formation of the thin film, the raw material gas is cut, the thermal catalyst is cooled to a temperature at which no problem occurs, and the introduction of the carrier gas is stopped.

Thus, the single-crystal silicon film 22 is deposited on the substrate 10 by the bias catalytic CVD method and heteroepitaxy. Next, a MOSTFT using a single crystal silicon film as a channel region is manufactured.

As a sixth step, as shown in FIG.
Impurity concentration in channel region for channel MOSTFT
In order to control the degree of
Mask with a resist r1 and use P-type impurity ions (eg,
For example, boron difluoride ion BF ₂ ⁺), For example, 20
5 × 10 at ~ 30 keV¹²atoms / cm²Do
Ion-implanted in the appropriate amount, and the conductivity type of the tin-containing single crystal silicon film
Is a P-type silicon layer 11.

Next, as a seventh step, as shown in FIG. 46, in order to control the impurity concentration of the channel region for the P-channel MOSTFT, an N-channel M
The OSTFT is masked with a photoresist r2, and N-type impurity ions (for example, phosphorus ions P ⁺ ) are
Ion implantation is performed at ５０50 keV at a dose of 5 × 10 ¹² atoms / cm ² to form an N-type silicon layer ^{12 of} a tin-containing single crystal silicon film.

Next, in an eighth step, as shown in FIG. 47, a molybdenum / tantalum alloy film 24 as a gate electrode material is formed to a thickness of 400 (n) by sputtering, for example.
m) Deposit thick.

Next, in a ninth step, as shown in FIG. 48, a photoresist r3 is formed in a predetermined pattern, and using this as a mask, the molybdenum / tantalum alloy film 24 is patterned into the shape of the gate electrode 25. The resist r3 is removed.

Next, in a tenth step, as shown in FIG.
Thus, the P-channel MOS TFT and the gate electrode 25
Example masked with photoresist r4 and is an N-type impurity
For example, As⁺The ions are, for example, 1 at 60-70 keV.
× 10^Fifteenatoms / cm ²Ion implantation at a dose of
After removing the photoresist,₂Medium at about 1000 ° C for 20
RTA (Rapid Thermal) for 30 seconds to 30 seconds
Anneal) and N-channel MOSTFT
N⁺Source region S1 and drain region D1
Formed.

Next, in an eleventh step, as shown in FIG. 50, the N-channel MOSTFT and the gate electrode 25 are masked with a photoresist r5, and a P-type impurity, for example, B ⁺ ions, for example, 20 to 30 keV At 1 ×
After ion implantation at a dose of 10 ¹⁵ atoms / cm ² and removal of the photoresist, RTA (Rapid Thermal A) at about 1000 ° C. for 20 to 30 seconds in N _2.
nneal) to form a P ⁺ -type source region S2 and a drain region D2 of the P-channel MOSTFT. Note that this RTA process is an N-channel MOS
The activation of the TFTs may be performed together.

Next, in a twelfth step, as shown in FIG. 51, a silicon oxide film 27, for example, a 50 to 100 (nm) -thick phosphor silicate glass (PSG) film 28 is formed on the entire surface by bias catalytic CVD or the like. For example, 200-3
The silicon nitride film 29 having a thickness of 00 (nm) is
A film is formed to a thickness of 0 to 200 (nm).

Next, in a thirteenth step, as shown in FIG. 51, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is sputtered at 150 ° C. for 1 μm over the entire surface including each hole. Deposited to the thickness of
By patterning this, as shown in FIG. 52, the P-channel MOSTFT and the N-channel MOSTFT are
A source or drain electrode S or D and a gate extraction electrode or wiring G are formed.

Next, in a fourteenth step, a procedure similar to the fourteenth step and the fifteenth step of the specific example 1 is used.
A steam annealing step and a plasma cleaning step (or a sputter cleaning step) are performed. Thereafter, sintering is performed at 400 ° C. for 1 hour in a forming gas (N ₂ + H ₂ ) to improve ohmic contacts and surface states, thereby completing each MOSTFT.

In this example, a material layer having good lattice matching with a single crystal semiconductor, for example, single crystal silicon, is formed at least in the semiconductor device formation region of the substrate, and a single crystal silicon film is heterogeneously formed using the material having good lattice matching as a seed. Since the epitaxial growth is performed, a tin-containing single crystal silicon film having high electron / hole mobility and excellent operability can be obtained.

(Embodiment 8) As Embodiment 8, a bottom-gate type single-crystal silicon CMOS obtained by forming a single-crystal semiconductor film by heteroepitaxial growth.
An example of a TFT manufacturing method will be described. The material and size of the substrate 10 are selected based on the same criteria as in the first embodiment. First, a molybdenum / tantalum alloy sputtered film 300 to 400
(Nm) Thickness is formed, and a bottom gate electrode is formed. The bottom gate electrode is tapered by 20 to 45 degrees by general-purpose photolithography and etching technology. Next, a silicon nitride film 50 to 100 (nm) thick for a protective film and a bottom gate insulating film, and a silicon oxide film 50 to 100 are formed in the same procedure as the first to third steps of the above specific example 1. (Nm) Thickness is formed. Instead of the silicon nitride film and the silicon oxide film, the silicon oxynitride film may be 50 to 200 (nm) thick.

Next, a crystalline sapphire thin film having a thickness of 5 to 200 (nm) is formed in the same procedure as in the specific example 7. Next, a single-crystal silicon film containing at least one of tin, germanium, and lead containing at least one of 0.005
Heteroepitaxial growth is performed to a thickness of μm to several μm (for example, 50 to 100 (nm)).

As described above, silicon is heteroepitaxially grown using the crystalline sapphire thin film as a seed, and is deposited as a tin-containing single crystal silicon film having a thickness of, for example, about 50 to 100 (nm). Note that this crystalline sapphire film is a seed for heteroepitaxial growth of silicon and also plays a role as a bottom gate insulating film.

Thereafter, a silicon oxide film for a protective film is formed by the same procedure as in the fifth step of the specific example 1. After the film formation, the raw material gas is cut, the thermal catalyst is cooled to a temperature that does not cause a problem, and the introduction of the carrier gas is stopped.

Thus, a tin-containing single crystal silicon film is deposited on the substrate 10 by the bias catalytic CVD method and heteroepitaxy. Next, in the same manner as in the specific example 7, a MOSTFT having a tin-containing single crystal silicon film as at least a channel region is manufactured. In this embodiment, after the formation of the source electrode and the drain electrode, the steam annealing is performed in the same manner as in the first embodiment.

(Embodiment 9) As a specific embodiment 9, a dual-gate single-crystal silicon CM obtained by forming a single-crystal silicon film by heteroepitaxial growth.
An example of the OSTFT manufacturing method will be described. The material and size of the substrate 10 are selected based on the same criteria as in the first embodiment. Dual gate type single crystal silicon C
The MOSTFT is manufactured by the following steps. First, a sputtered film of molybdenum / tantalum alloy is formed in a thickness of 300 to 400 (nm) at least in the TFT region of the substrate 10. Then, the taper etching of 20 to 45 degrees is performed by general-purpose photolithography and etching technology,
A bottom gate electrode is formed.

Next, the first step of the specific example 1 to
By the same procedure as the third step, a silicon nitride film 50 to 100 (nm) thick and a silicon oxide film 50 to 100 (nm) thick for the protective film and the bottom gate insulating film are formed. Note that a silicon oxynitride film having a thickness of 50 to 200 (nm) may be formed instead of forming the silicon nitride film and the silicon oxide film.

Next, a crystalline sapphire thin film having a thickness of 5 to 200 (nm) is formed in the same procedure as in the specific example 7 described above. Next, a single-crystal silicon film containing at least one of tin, germanium, and lead containing at least one of 0.005
Heteroepitaxial growth is performed to a thickness of μm to several μm (for example, 50 to 100 (nm)).

As described above, silicon is heteroepitaxially grown using the crystalline sapphire thin film as a seed, and is deposited as a tin-containing single crystal silicon film having a thickness of, for example, about 50 to 100 (nm). Thus, a tin-containing single-crystal silicon film is deposited on the substrate 10 by the bias catalytic CVD method and heteroepitaxy. After that, a MOSTFT having a tin-containing single crystal silicon film as at least a channel region is manufactured.

Then, a silicon oxide film for a top gate insulating film having a thickness of 50 to 100 (nm) is formed by the same procedure as in the fifth step of the specific example 1. Further, if necessary, a silicon nitride film having a thickness of 50 to 100 (nm) is formed. Note that a silicon oxynitride film having a thickness of 50 to 200 (nm) may be formed instead of the silicon oxide film and the silicon nitride film. After the film formation, the raw material gas is cut, the thermal catalyst 5 is cooled to a temperature at which there is no problem, and the introduction of the carrier gas is stopped. Note that this crystalline sapphire thin film is a seed for heteroepitaxial growth of silicon and also plays a role as a bottom gate insulating film.

Next, the source and drain regions of the silicon oxide film for the top gate insulating film are opened, and a sputtered film of molybdenum / tantalum alloy is formed on the entire surface. Form drain and top gate electrodes.

In this embodiment, after the formation of the top gate electrode, the source electrode, and the drain electrode, a steam annealing process and plasma cleaning or sputter cleaning of the electrodes are performed in the same manner as in the first embodiment.

[0384]

According to the present invention, at least tin, germanium is applied on the substrate by applying an electric field equal to or lower than the glow discharge starting voltage between the substrate and the electrode by utilizing bias catalytic CVD or high-density bias catalytic CVD. By performing a semiconductor film forming step including forming a semiconductor film containing at least one of lead and lead, the following effects can be obtained. That is, in the present invention, since a semiconductor film containing at least one of tin, germanium, and lead is formed, tin, germanium, and lead are mixed in the obtained single crystal silicon layer or polysilicon layer. Even if
Since these are elements of the fourth group of the periodic table, they do not become carriers in the silicon layer, so that the silicon layer has a high resistance. Therefore, _Vth adjustment and resistance value adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin, germanium, and lead contained in the silicon layer in an appropriate amount render crystal defects electrically inactive, so that the resulting silicon layer has reduced junction leakage and increased electron / hole mobility. It will be. In addition, since the crystal irregularity existing at the crystal grain boundary is reduced and the stress of the film is reduced, the electron / hole mobility is increased and the transistor characteristics are improved.

Also, by applying an electric field equal to or lower than the glow discharge starting voltage between the substrate and the electrode by using the bias catalyst CVD or the high-density bias catalyst CVD, a semiconductor film is formed on the substrate. The reaction gas is brought into contact with the heated catalyst body, and the generated reaction species (radical deposition species having high energy or their precursors and radical ions) are DC or AC / DC below the glow discharge starting voltage, or Since a directional kinetic energy is given by applying an electric field such as RF / DC to vapor-deposit a predetermined film on the substrate, the following remarkable effects can be obtained.

(1) The reactive species (radical deposited species having high energy or its precursor and radical ions) generated by the thermal catalyst receives directional kinetic energy by the action of an electric field, and is efficiently deposited on the substrate. As well as being guided, diffusion in the film during migration and generation on the substrate is sufficient. Therefore, as compared with the conventional catalytic CVD method, the kinetic energy of the reactive species can be independently controlled by the electric field, so that the adhesion of the generated film to the substrate, the density of the generated film, the uniformity of the generated film or the smoothness of the generated film can be improved. It is possible to improve the positiveness, the embedding property in a via hole and the like, and the step coverage. Further, it is possible to lower the substrate temperature, control the stress of the formed film, and so on, and realize a high quality film. (2) Since the reactive species (ions, radicals, etc.) generated by the catalyst can be independently controlled by an electric field and can be efficiently deposited on the substrate, the utilization efficiency of the reaction gas is high, the generation rate is increased, and the productivity is increased. The cost can be reduced by improving and reducing the reaction gas. (3) A much simpler and less expensive device is realized as compared with the plasma CVD method. (4) Since the above-mentioned electric field is applied even in the normal pressure type, the density,
A high quality film with good uniformity and adhesion can be obtained. (5) Since the kinetic energy of the reactive species is large and a desired high-quality film can be obtained even with a low-temperature substrate, the substrate temperature can be lowered, so that a large and inexpensive insulating substrate (borosilicate glass, aluminosilicate) Glass substrates such as acid glass,
A heat-resistant resin substrate such as polyimide) can be used, and the cost can be reduced in this respect as well.

In the case where the present invention is carried out by bias catalytic CVD, no plasma is generated, and therefore, a film with low stress and no damage by plasma is obtained.
When the present invention is performed by the high-density bias catalytic CVD, the influence of the plasma hardly reaches the substrate, the damage by the plasma is reduced, and a film with low stress can be obtained.

In the present invention, since the semiconductor film containing at least one of tin, germanium and lead is annealed by laser, only the extreme surface of the semiconductor film is instantaneously heated. In addition, the influence of heat on the substrate is reduced, and the amorphous silicon or microcrystalline silicon thin film can be crystallized and the impurities can be activated without causing the deformation of the substrate. Can be. In addition, the crystallization and activation can be performed at a low temperature without increasing the temperature of the entire substrate. Further, the present invention improves the performance of the thin film semiconductor device and facilitates manufacturing. In addition, since the polysilicon film contains at least one of tin, germanium, and lead, crystal irregularities existing at the crystal grain boundaries are reduced, and the stress of the film is reduced. A membrane can be obtained.

Further, according to the present invention, since annealing is performed in a low-pressure high-temperature or high-pressure high-temperature atmosphere containing water vapor, even at a low-temperature heat treatment of 400 ° C. or less, at least tin, germanium, and lead can be effectively treated. The interface state between a semiconductor containing any one or more of them and the insulating film can be improved and the insulating film can be modified.

[0390] In addition, by modifying the insulating film, that is, reducing water and OH groups in the insulating film, hot insulating of the gate insulating film or the semiconductor film containing at least one of tin, germanium, and lead can be achieved. The effect of suppressing electron degradation can be obtained.

Further, since the electrostatic charge caused by defects and impurities in the gate insulating film can be neutralized and the negative flat band voltage can be made closer to 0 V, the n-channel MIS transistor can be depleted. , Avoiding the transition and making it an enhancement type, p-channel M
In the IS transistor, the threshold voltage _Vth can be prevented from increasing and a reliable operation can be performed.
CMOS using MIS transistors of both conductivity type channels
And the like can be easily integrated.

Further, variation in element characteristics in the same semiconductor substrate can be reduced, and circuit integration can be facilitated. In addition, at least tin, germanium, improvement in interface characteristics between the semiconductor film and the insulating film containing at least one of lead, that is, a threshold value is reduced, an on-current is increased, an off-current is reduced, and a threshold is reduced. Value voltage V _th
Therefore, the integrated circuit can be operated at high speed.

Also, after the steam annealing treatment after the electrode formation, at least the electrode surface is sputter-cleaned or plasma-cleaned to remove its oxide film and hydroxide film, so that it is taken out (gold wire bonding, electroless N
The electrical / mechanical contact of (i / Au plating + solder bump) is improved, and the characteristics, quality and reliability are improved.

Further, according to the present invention, the type and strength of the electric field as the control factor, the type and temperature of the catalyst, the substrate heating temperature, the vapor deposition conditions, the type of source gas,
By changing the N or P type impurity concentration to be added, a semiconductor film containing at least one of tin, germanium, and lead having a wide range of N or P type impurity concentration can be efficiently and easily obtained. _Vth adjustment is easy with high mobility, and high-speed operation with low resistance is possible. Further, since the substrate temperature can be further reduced, low-strain-point glass or a heat-resistant resin substrate, which is inexpensive and easy to increase in size, can be adopted, and the cost can be reduced.

In the present invention, when a thin film is formed on a substrate by using bias catalytic CVD or high-density bias catalytic CVD, activated hydrogen ions H ^* are constantly generated and electrolysis is applied, so that the surface of the substrate is reduced. Since it is configured to be always efficiently cleaned, an amorphous silicon transition layer is formed at the interface between the silicon oxide film of the gate insulating film and the polysilicon film containing at least one of tin, germanium, and lead. Instead, a high-quality thin film layer can be formed. Further, after film formation, after laser annealing, and after steam annealing, at least the respective concentrations of oxygen, carbon, and nitrogen in the polysilicon film near the interface with the gate insulating film, for example, 1 × 10 4 ¹⁹ atoms / c
m ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³
And the concentration of hydrogen can be reduced to 0.01 atomic% / cm ³
As described above, it is possible to form a high mobility, high quality polysilicon film.

Before forming a film, activated hydrogen ions H ^*
The surface of the substrate is constantly cleaned and the surface modification treatment is performed, so that the adhesion of molecules such as water and oxygen on the substrate surface is removed, the interface state is reduced, the stress between the respective films is low, and high quality components are formed. A film (a silicon nitride film, a silicon oxide film, a polysilicon film containing at least one of tin, germanium, and lead, or the like) can be formed. In particular, in the case where a gate insulating film and a silicon film are successively formed, a treatment for exposing to activated hydrogen ions H ^* has a high quality of a semiconductor-insulator junction structure having a low interface state density due to a hydrogen annealing effect. A semiconductor device can be manufactured.

For this reason, not only the top gate type but also
Even with a bottom gate type and a dual gate type TFT, a polysilicon film and a single crystal silicon film containing at least one of tin, germanium, and lead having high electron / hole mobility can be obtained. Therefore, a semiconductor device using this high-performance polysilicon film or single-crystal silicon film,
It becomes possible to manufacture electro-optical devices and the like.

When a continuous film is formed by the bias catalyst CVD method or the like, the film can be formed into an inclined junction by gradually decreasing or increasing each film forming material gas in the same chamber. Therefore, stress between the respective films is reduced, and a high-quality insulator-semiconductor junction semiconductor device can be manufactured.

In the case where a semiconductor film containing at least one of tin, germanium and lead and an insulating film are formed in different chambers in a vacuum chamber, contamination is prevented and stress between the films is reduced. Can be planned,
High-quality semiconductor devices can be manufactured.

Furthermore, in the present invention, the formation of a semiconductor film and an insulating film containing at least one of tin, germanium, and lead, and the laser annealing and the steam annealing are performed in different chambers of a vacuum vessel. Thereby, it is possible to continuously perform the formation of the semiconductor film and the insulating film, the laser annealing, and the steam annealing. Furthermore, this can prevent contamination and improve workability, thereby enabling high-performance, high-quality, inexpensive semiconductor devices to be manufactured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of an apparatus used for a thin film forming method of the present invention.

FIG. 2 is an explanatory diagram in a case where bias catalytic CVD is performed using the apparatus of FIG. 1;

FIG. 3 is an explanatory diagram in a case where bias catalytic CVD is performed using the apparatus of FIG. 1;

FIG. 4 is a schematic explanatory view of a main part of a DC bias catalytic CVD apparatus used in the present invention.

FIG. 5 is an RF / DC bias catalyst CV used in the present invention.
It is a schematic explanatory view of the principal part of D device.

FIG. 6 shows the AC / DC bias catalyst CV used in the present invention.
It is a schematic explanatory view of the principal part of D device.

FIG. 7 is a schematic view showing various methods for applying a bias catalyst CVD voltage of the present invention.

FIG. 8 is a schematic view of an acceleration electrode used in bias catalytic CVD according to the present invention.

FIG. 9 is a schematic view of an apparatus used for irradiating a reactive species with charged particles by bias catalytic CVD according to the present invention.

FIG. 10 is a graph showing a gas introduction mode to a chamber.

FIG. 11 is a graph showing a gas introduction mode to a chamber.

FIG. 12 is a graph showing a mode of gas introduction into a chamber.

FIG. 13 is a graph showing a mode of gas introduction into a chamber.

FIG. 14 is a graph showing a mode of gas introduction into a chamber.

FIG. 15 is a graph showing a gas introduction mode into a chamber.

FIG. 16 is an explanatory diagram showing an example of a gas supply method.

FIG. 17 is an explanatory diagram showing an example of a method for supplying water vapor into the chamber.

FIG. 18 is an explanatory view showing another example of an apparatus used for the thin film forming method of the present invention.

FIG. 19 is an explanatory view showing another example of an apparatus used for the thin film forming method of the present invention.

FIG. 20 is an explanatory view showing another example of an apparatus used for the thin film forming method of the present invention.

FIG. 21 is an explanatory view showing another example of an apparatus used for the thin film forming method of the present invention.

FIG. 22 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 23 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 24 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 25 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 26 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 27 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 28 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 29 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 30 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 31 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 32 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 33 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 34 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 35 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 36 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 37 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 38 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 39 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 40 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 41 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 42 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 43 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 44 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 45 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 46 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 47 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 48 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 49 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 50 is an explanatory view showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

FIG. 51 is an explanatory view showing one example of a sputtering apparatus used for the thin film forming method of the present invention.

FIG. 52 is an explanatory diagram showing a process of a method of forming a thin film and a method of manufacturing a thin film semiconductor in an example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Film-forming apparatus A, B, C chamber 1a Exhaust system 2 Susceptor 2a Upper surface 2b Heater 2c Heater power supply 3 Gas introduction system 3a Gas shower head 3b Shower head holder 3c Manual valve 3d Automatic valve 3e Three-way valve 5 Thermal catalyst 5a Heating means 5b Thermal catalyst holder 6 Rail 8a Reaction gas supply box 8b Belt 10 Substrate 10a Step 11, 15, 21, 29 Silicon nitride film 12, 14, 19, 23, 27 Silicon oxide film 13, 13n, 13p Polysilicon film 16, Reference Signs List 24 Molybdenum / tantalum alloy film 17, 25 Gate electrode 20, 28 Phosphosilicate glass (PSG) film 22 Single crystal silicon film 30 DC power supply 31 Steam annealing chamber 32 Susceptor 33 Gas supply system 34 Pressure gauge 35 Water container 36 Constant temperature bath 37 Connecting pipe Reference Signs List 8 Carrier gas supply port 41 Load / lock chamber 42 Separation chamber 43 Film formation chamber 44 Laser annealing chamber 45 Steam annealing chamber 46 Semiconductor film deposition chamber 47 Insulating film deposition chamber 50 Sapphire thin film 60 Reaction gas 61 Supply conduit 67 Shutter 68 Touch Medium power supply 69 DC power supply 70 Reactive species 71 Heater wire 72 Magnetic seal 73 Front chamber 74 Turbo molecular pump chamber 75 Valve 76 Deposited species, generated film 101 Mesh electrode 113 Low pass filter 114 Matching circuit 116 Switch 125 Low frequency power supply

Continued on the front page F-term (reference) EE13 EF05 EH19 HA15 HA16 HA18 HA23 5F052 AA02 BA07 BB07 CA04 CA09 DA01 DB01 FA05 FA13 JA04 5F110 AA01 AA16 AA17 AA19 AA26 AA28 BB02 BB04 CC02 CC08 DD01 DD02 DD03 DD04 DD05 DD13 DD14 FF27 FF02 FF23 FF03 FF23 FF02 GG02 GG04 GG12 GG13 GG22 GG25 GG32 GG33 GG34 GG44 GG47 GG52 GG55 GG57 HJ01 HJ04 HJ13 HJ23 HL03 HL23 HL27 NN02 NN03 NN04 NN23 NN24 NN25 NN35 PP03 PP04 PP05 PP04 Q13 Q33 Q33 Q

Claims (44)

[Claims] 1. A semiconductor film forming method for forming a semiconductor film on a substrate by utilizing a bias catalyst CVD or a high density bias catalyst CVD, wherein at least a raw material gas is supplied to a vacuum vessel and disposed in the vacuum vessel. A semiconductor including at least one of tin, germanium, and lead on the substrate by applying an electric field equal to or lower than a glow discharge initiation voltage between the substrate and the electrode. A method for forming a semiconductor film, comprising: a film forming step; and a laser annealing step of irradiating the formed semiconductor film with a laser and annealing the formed semiconductor film with a laser. 2. Before the semiconductor film forming step, a carrier gas containing hydrogen is constantly supplied to the vacuum vessel, and the substrate is cleaned with activated hydrogen ions H ^* generated by the supplied carrier gas. 2. The method according to claim 1, further comprising a cleaning step, wherein the cleaning step and the semiconductor film forming step are performed. 3. A cleaning method in which a carrier gas containing hydrogen is supplied to the vacuum vessel before the semiconductor film forming step, and the substrate is cleaned with activated hydrogen ions H ^* generated by the supplied carrier gas. The method according to claim 1, wherein: a step of increasing or decreasing the supply of the carrier gas at least one before, during, or after the semiconductor film forming step; and the semiconductor film forming step. A method for forming a semiconductor film. 4. The semiconductor film forming step is performed in a film forming chamber in the vacuum vessel. The laser annealing step is performed in a laser annealing chamber in the vacuum vessel, and the semiconductor film forming step and the laser annealing step are performed. 2. The method according to claim 1, wherein the method is performed continuously in the vacuum vessel. 5. An insulating film is formed on the semiconductor film annealed by the laser in the film forming chamber, and the step of forming the semiconductor film, the step of laser annealing, and the step of forming the insulating film are performed in the vacuum vessel. 2. The method according to claim 1, wherein the step is performed continuously. 6. A semiconductor film forming method for forming a semiconductor film on a substrate by using bias catalytic CVD or high-density bias catalytic CVD, wherein at least a raw material gas is supplied to a vacuum vessel and disposed in the vacuum vessel. Applying an electric field of a glow discharge starting voltage or less between the substrate and the electrode, on the substrate, at least tin, germanium, a semiconductor film containing one or more of lead, an insulating film, Forming a semiconductor film and an insulating film, and irradiating a laser to the formed semiconductor film and the insulating film, and annealing the formed semiconductor film and the insulating film with a laser. A method for forming a semiconductor film, comprising: 7. The semiconductor film forming method according to claim 1, wherein the laser annealing step is performed in a laser annealing apparatus different from the vacuum vessel. 8. A process for forming a semiconductor film and an insulating film in a film forming chamber in the vacuum container, the laser annealing process in a laser annealing chamber in the vacuum container, 7. The method according to claim 6, wherein the laser annealing step is performed continuously in the vacuum vessel. 9. A semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the laser is formed in a laser annealing chamber in the vacuum vessel. The method according to claim 6, wherein an annealing step is performed, and the formation of the semiconductor film, the formation of the insulating film, and the laser annealing step are performed continuously in the vacuum vessel. 10. In the semiconductor film forming step or the semiconductor film and insulating film forming step,
Each concentration of oxygen, carbon, and nitrogen in at least the carrier channel region in the semiconductor film is 1 × 10 ¹⁹
atoms / cm ³ or less, hydrogen concentration of 0.01 atomic% /
forming a semiconductor film is cm ³ or more, in the laser annealing process, the semiconductor film by laser annealing, oxygen in at least the carrier channel region of the semiconductor film, carbon, each concentration of 1 × 10 ¹⁹ atoms of nitrogen / cm ³ or less, the semiconductor film forming method according to claim 1 or 6, wherein the hydrogen concentration is characterized in that 0.01 atomic% / cm ³ or more semiconductor film. 11. The semiconductor film in the step of forming a semiconductor film or the step of forming a semiconductor film and an insulating film when the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced-pressure CVD or a bias-normal-pressure CVD. Forming a semiconductor film in which at least the concentration of oxygen, carbon, and nitrogen in at least the carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less and the hydrogen concentration is 0.01 atom% / cm ³ or more; In the laser annealing step, the semiconductor film is laser-annealed so that at least the concentration of oxygen, carbon, and nitrogen in the carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less and the hydrogen concentration is 0.1 × 10 ¹⁹ atoms / cm ³ or less. claim 1, characterized in that a 01 atomic% / cm ³ or more semiconductor film The semiconductor film forming method other 6 wherein. 12. A semiconductor film forming method for forming a semiconductor film on a substrate by using bias catalytic CVD or high-density bias catalytic CVD, wherein at least a raw material gas is supplied to a vacuum vessel and disposed in the vacuum vessel. Applying an electric field of a glow discharge starting voltage or less between the substrate and the electrode, on the substrate, at least tin, germanium, a semiconductor film containing one or more of lead, an insulating film, Forming a semiconductor film and an insulating film, and a water vapor annealing step of annealing the formed semiconductor film and the insulating film with water vapor. 13. The method according to claim 12, wherein the steam annealing step is performed in a steam annealing apparatus different from the vacuum vessel. 14. Performing a semiconductor film and an insulating film forming step in a film forming chamber in the vacuum vessel, performing the steam annealing step in a steam annealing chamber in the vacuum vessel, 13. The method according to claim 12, wherein the steam annealing step is continuously performed in the vacuum vessel. 15. A semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the steam is formed in a steam annealing chamber in the vacuum vessel. 13. The method according to claim 12, wherein an annealing step is performed, and the formation of the semiconductor film, the formation of the insulating film, and the steam annealing step are sequentially performed in the vacuum vessel. 16. In the step of forming a semiconductor film and an insulating film, each concentration of oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less. Forming a semiconductor film having a hydrogen concentration of 0.01 atomic% / cm ³ or more; in the steam annealing step, the semiconductor film is steam-annealed to form oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film; Has a concentration of 1 × 10 ¹⁹ atoms / cm ³ or less and a hydrogen concentration of 0.1 × 10 ¹⁹ atoms / cm ³ or less.
13. The semiconductor film forming method according to claim 12, wherein the semiconductor film is at least 01 atomic% / cm < ³ >. 17. The bias catalytic CVD or high density
Bias catalytic CVD, bias reduced pressure CVD or
The semiconductor film in the case of as normal pressure CVD and
As the semiconductor film in the insulating film forming step,
Oxygen, charcoal at least in the carrier channel region of
Each concentration of element and nitrogen is 1 × 10 ¹⁹atoms /
cm³Hereinafter, the hydrogen concentration is 0.01 atomic% / cm.³Above
A semiconductor film is formed, and in the steam annealing step, the semiconductor film is steam annealed.
At least a carrier channel in the semiconductor film.
Each concentration of oxygen, carbon and nitrogen in the
× 10¹⁹atoms / cm³Hereinafter, when the hydrogen concentration is 0.0
1 atomic% / cm ³Characterized by the above semiconductor film
13. The method for forming a semiconductor film according to claim 12, wherein 18. When the semiconductor film is single crystal silicon, a step is formed at least in a silicon film formation region,
13. The method according to claim 12, wherein a single-crystal silicon film is formed by grapho-epitaxial growth in the silicon film formation region including the step. 19. When the semiconductor film is single crystal silicon, a material layer having good lattice matching with single crystal silicon is formed at least in a silicon film formation region, and the single crystal silicon film is formed in the silicon film formation region including the material layer. 13. The method according to claim 12, wherein is heteroepitaxially grown. 20. The material layer having good lattice matching with the single crystal silicon is made of at least one kind of material selected from a group containing sapphire or spinel structure or calcium fluoride. The method for forming a semiconductor film according to the above. 21. A semiconductor film forming method for forming a semiconductor film on a substrate by using bias catalytic CVD or high-density bias catalytic CVD, comprising supplying at least a raw material gas to a vacuum vessel and disposing the raw material gas in the vacuum vessel. Applying an electric field of a glow discharge starting voltage or less between the substrate and the electrode, on the substrate, at least tin, germanium, a semiconductor film containing one or more of lead, an insulating film, Forming a semiconductor film and an insulating film, comprising: irradiating a laser to the formed semiconductor film and the insulating film, and annealing the formed semiconductor film and the insulating film with a laser; A method for forming a semiconductor film, comprising: a steam annealing step of performing annealing with steam after the laser annealing step. 22. A carrier gas containing hydrogen is constantly supplied to the vacuum vessel before the semiconductor film and insulating film forming step, and activated hydrogen ions H ^* generated by the supplied carrier gas are applied to the substrate. 22. A cleaning process for cleaning the semiconductor device, wherein the cleaning process and the semiconductor film and insulating film forming process are performed.
The method for forming a semiconductor film according to any one of the above. 23. Before the step of forming the semiconductor film and the insulating film, a carrier gas containing hydrogen is supplied to the vacuum vessel, and activated hydrogen ions H ^* generated by the supplied carrier gas cause the activated hydrogen ions H ^* to flow on the substrate. Performing a cleaning step of cleaning, a step of increasing or decreasing the supply of the carrier gas at least one of before, during, and after the step of forming the semiconductor film and the insulating film; and a step of forming the semiconductor film and the insulating film. 22. The method of forming a semiconductor film according to claim 6, wherein: 24. The method according to claim 21, wherein the laser annealing step is performed in a laser annealing apparatus different from the vacuum vessel, and the steam annealing step is performed in a steam annealing apparatus different from the vacuum vessel. A method for forming a semiconductor film. 25. A semiconductor film and insulating film forming step in a film forming chamber in the vacuum vessel, the laser annealing step in a laser annealing chamber in the vacuum vessel, and a laser annealing step in a steam annealing chamber in the vacuum vessel. 22. The method for forming a semiconductor film according to claim 21, wherein a steam annealing step is performed, and the semiconductor film and insulating film forming step, the laser annealing step, and the steam annealing step are sequentially performed in the vacuum vessel. 26. A semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, an insulating film is formed in an insulating film forming chamber in the vacuum vessel, and the laser is formed in a laser annealing chamber in the vacuum vessel. Performing an annealing step, performing the steam annealing step in a steam annealing chamber in the vacuum vessel, forming the semiconductor film, forming the insulating film, laser annealing step, and the steam annealing step in the vacuum vessel. 22. The method according to claim 21, wherein the method is performed. 27. In the semiconductor film and insulating film forming step, the concentration of oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film is 1 × 10 ¹⁹ atoms / cm ³ or less. Forming a semiconductor film having a hydrogen concentration of 0.01 atomic% / cm ³ or more; in the steam annealing step, the semiconductor film is steam-annealed to form oxygen, carbon, and nitrogen in at least a carrier channel region in the semiconductor film; Has a concentration of 1 × 10 ¹⁹ atoms / cm ³ or less and a hydrogen concentration of 0.1 × 10 ¹⁹ atoms / cm ³ or less.
And 01 atomic% / cm ³ or more semiconductor film, in the laser annealing process, the semiconductor film by laser annealing, oxygen in at least the carrier channel region in the semiconductor film, carbon, the respective concentration of 1 × 10 nitrogen 22. The semiconductor film forming method according to claim 21, wherein the semiconductor film has a thickness of ¹⁹ atoms / cm ³ or less and a hydrogen concentration of 0.01 atomic% / cm ³ or more. 28. The bias catalytic CVD or high density
Bias catalytic CVD, bias reduced pressure CVD or
The semiconductor film in the case of as normal pressure CVD and
As the semiconductor film in the insulating film forming step,
Oxygen, charcoal at least in the carrier channel region of
Each concentration of element and nitrogen is 1 × 10 ¹⁹atoms /
cm³Hereinafter, the hydrogen concentration is 0.01 atomic% / cm.³Above
A semiconductor film is formed, and in the steam annealing step, the semiconductor film is steam annealed.
At least a carrier channel of the semiconductor film.
Each concentration of oxygen, carbon and nitrogen in the region is 1 ×
10¹⁹atoms / cm³Hereinafter, the hydrogen concentration is 0.01
Atomic% / cm³The above semiconductor film, and in the laser annealing step, the semiconductor film is
Anneal to at least carrier carriers in the semiconductor film.
Oxygen, carbon and nitrogen concentrations in the tunnel region
Is 1 × 10¹⁹atoms / cm³Below, the hydrogen concentration
0.01 atomic% / cm³Specially, the above semiconductor film is used.
22. The method of forming a semiconductor film according to claim 21, wherein: 29. The method according to claim 1, wherein the bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD.
22. The method of forming a semiconductor film according to any one of items 12 and 21. 30. A manufacturing method for manufacturing a top gate type TFT using a bias catalyst CVD or a high-density bias catalyst CVD, wherein at least a raw material gas is supplied to a vacuum container, and the device is disposed in the vacuum container. An electric field equal to or lower than the glow discharge starting voltage is applied between the substrate and the electrode, and a protective film and a semiconductor film containing at least one of tin, germanium, and lead are formed on the substrate in the vacuum container. And a gate insulating film;
Is continuously formed into a polycrystalline semiconductor film, and thereafter, the semiconductor film is subjected to laser annealing, and then a source / top gate / drain electrode is formed. 31. A method for manufacturing a bottom gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, comprising forming a bottom gate electrode on a substrate and supplying at least a source gas to a vacuum vessel. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium, and lead and a protective film are continuously formed, and thereafter, the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. A method for manufacturing a thin-film semiconductor device, comprising forming a drain electrode. 32. A manufacturing method for manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate electrode is formed on a substrate, and at least a source gas is supplied to a vacuum container. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium and lead and a top gate insulating film are successively formed, and then the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. A method for manufacturing a thin film semiconductor device, comprising forming a / top gate / drain electrode. 33. The method of manufacturing a thin film semiconductor device according to claim 30, wherein the laser annealing is performed in a laser annealing apparatus different from the vacuum vessel. 34. The semiconductor film and the insulating film are formed in a film forming chamber in the vacuum vessel, and the laser annealing is performed in a laser annealing chamber in the vacuum vessel. 33. The method of manufacturing a thin film semiconductor device according to claim 30, wherein the film and the laser annealing are continuously performed in the vacuum vessel. 35. A laser annealing chamber in the vacuum vessel, wherein the semiconductor film is formed in a semiconductor film forming chamber in the vacuum vessel, the insulating film is formed in an insulating film forming chamber in the vacuum vessel. 33. The method according to claim 30, wherein the laser annealing is performed in the vacuum vessel, and the formation of the semiconductor film, the formation of the insulating film, and the laser annealing are continuously performed in the vacuum vessel. Of manufacturing a thin film semiconductor device. 36. A manufacturing method for manufacturing a top gate type TFT using a bias catalytic CVD or a high density bias catalytic CVD, wherein at least a raw material gas is supplied to a vacuum container, and the raw material is disposed in the vacuum container. A semiconductor containing at least one of tin, germanium and lead on the substrate in the vacuum vessel by applying an electric field equal to or lower than a glow discharge starting voltage between the substrate and the electrode. A film and a gate insulating film are continuously formed, then a source / top gate / drain electrode is formed, and then a steam annealing process is performed at a low pressure and a high temperature or a high pressure and a high temperature. A method for manufacturing a thin film semiconductor device, comprising performing plasma cleaning or sputter cleaning of a drain electrode. 37. A method of manufacturing a bottom gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, comprising forming a bottom gate electrode on a substrate and supplying at least a source gas to a vacuum container. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium, and lead and a protective film are continuously formed, and then a source / drain electrode is formed. After that, plasma cleaning or sputter cleaning of the bottom gate electrode and the source / drain electrode is performed. Method of manufacturing a thin film semiconductor device. 38. A method for manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, wherein a bottom gate electrode is formed on a substrate, and at least a source gas is supplied to a vacuum container. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium and lead, and a top gate insulating film are continuously formed, and then a source / top gate / drain electrode is formed. Then, a water vapor annealing treatment is performed, and thereafter, the bottom gate electrode and the source / top gate / drain electrode are subjected to plasma cleaning or Method of manufacturing a thin film semiconductor device which is characterized in that the sputter cleaning. 39. A manufacturing method for manufacturing a top gate type TFT using bias catalyst CVD or high-density bias catalyst CVD, wherein at least a raw material gas is supplied to a vacuum container, and the material is disposed in the vacuum container. An electric field equal to or lower than the glow discharge starting voltage is applied between the substrate and the electrode, and a protective film and a semiconductor film containing at least one of tin, germanium, and lead are formed on the substrate in the vacuum container. And a gate insulating film;
Then, the semiconductor film is laser-annealed into a polycrystalline semiconductor film, then a source / top gate / drain electrode is formed, and then a steam annealing process is performed at a low pressure and a high temperature or a high pressure and a high temperature. Performing a plasma cleaning or a sputter cleaning of the source / top gate / drain electrodes. 40. A method of manufacturing a bottom gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, comprising forming a bottom gate electrode on a substrate and supplying at least a source gas to a vacuum container. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium, and lead and a protective film are continuously formed, and thereafter, the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. Forming an electrode, and then performing a steam annealing process at a low pressure and a high temperature or a high pressure and a high temperature. Thereafter, the bottom gate electrode and the source / drain electrode A method for manufacturing a thin film semiconductor device, comprising performing plasma cleaning or sputter cleaning. 41. A method for manufacturing a dual gate type TFT using a bias catalyst CVD or a high density bias catalyst CVD, comprising forming a bottom gate electrode on a substrate and supplying at least a source gas to a vacuum container. Applying an electric field equal to or less than a glow discharge start voltage between the substrate and the electrode disposed in the vacuum vessel, and in the vacuum vessel, a protective film on a bottom gate electrode, a bottom gate insulating film, A semiconductor film containing at least one of tin, germanium and lead and a top gate insulating film are successively formed, and then the semiconductor film is subjected to laser annealing to form a polycrystalline semiconductor film. / Top gate / drain electrodes are formed, and then steam annealing is performed at a low pressure and a high temperature or a high pressure and a high temperature. And performing a plasma cleaning or a sputter cleaning of the source / top gate / drain electrodes. 42. The bias catalyst CVD or the high-density bias catalyst CVD is a bias reduced pressure CVD or a bias normal pressure CVD.
41. The method for manufacturing a thin-film semiconductor device according to any one of 1, 32, 36, 37, 38, 39, 40, and 41. 43. A cleaning step of constantly supplying a carrier gas containing hydrogen to the vacuum vessel, and cleaning the substrate with activated hydrogen ions H ^* generated by the supplied carrier gas. The film and the cleaning step are repeated, or the film formation of the film is repeated after the cleaning step.
42. The method for manufacturing a thin-film semiconductor device according to any one of 7, 38, 39, 40, and 41. 44. A cleaning step of supplying a carrier gas containing hydrogen to the vacuum vessel, and cleaning the substrate with activated hydrogen ions H ^* generated by the supplied carrier gas; and supplying the carrier gas. 31. The method according to claim 30, further comprising: performing a step of increasing / decreasing at least one of before, during, and after forming the film; and forming the film.
31. The method for manufacturing a thin-film semiconductor device according to any one of 31, 32, 36, 37, 38, 39, 40, and 41.