JP2001168690A - Data transferring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transferring circuit which realizes fast data processing with a minimum delay circuit scale by the distribution method of a clock distribution circuit by allowing the skew of a clock signal in some degree. SOLUTION: This data transferring circuit consists of plural flip/flops and uses a signal, which is obtained by deviating one period of a clock signal by a fixed interval regularly, to the clock signal to be distributed to the respective flip-flop. The signal deviated by the fixed interval is a signal obtained by deviating 1/4 period of the clock signal, e.g. regularly. In a method for distributing the signal to the respective flip-flop, the clock signal to be inputted to the flip-flop on a transmission side is delayed compared with the clock signal to be inputted to the flip-flop on a reception side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline composed of a plurality of flip-flops, and more particularly, to a data transfer circuit having a minimum delay circuit scale by a clock distribution method and achieving high-speed data processing.

[0002]

2. Description of the Related Art In a conventional data transfer circuit, a delay accuracy in a clock signal distribution in particular greatly contributes. In order to accurately distribute a delay of a clock signal, a plurality of clock drivers on a clock wiring path are provided. The clock wiring is configured such that the clock wiring is of equal length on the upper stage side and the shortest wiring is on the lower stage side.

A data transfer circuit having such a clock signal distribution circuit normally distributes a clock signal to each flip-flop with the same phase and the same delay to constitute a data transfer circuit. However, the data transfer circuit cannot set the delay difference of the clock signal distributed to each flip-flop to “0”, so that no error occurs in data transfer between flip-flops (pipeline). To ensure that the flip-flops connected to the same clock do not inadvertently capture the same data on the same clock), in general, always provide a delay circuit to guarantee a minimum delay between flip-flops. Has been inserted. However, in recent years, this delay circuit has tended to increase as the size of the semiconductor integrated circuit has increased, and this delay circuit has caused a problem that the accommodating property / wiring property of the integrated circuit has deteriorated.

To solve this problem, for example, as disclosed in Japanese Patent Laid-Open No. 11-191610, the clock skew is reduced by reducing the total length of the clock wiring itself and the wiring delay. Has been proposed.

Further, there is a "clock signal distribution circuit" disclosed in Japanese Patent Application Laid-Open No. 6-204828. The claim is directed to a "continuously-connected delay circuit comprising a plurality of clock buffers provided on a semiconductor chip receiving an external clock signal and an inverter group having a hierarchical structure receiving an output signal from the clock buffer. Consisting of
A clock, wherein output signals of each of the inverter groups are distributed by the clock buffer such that a clock signal of a flip-flop outputting data in the sequential circuit group is delayed from a clock signal of the flip-flop receiving data. Distribution circuit "
The present invention and its configuration are almost the same.

[0006]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. H11-1916
In the technique disclosed in FIG. 10, as shown in FIG. 3, the clock signal 101 is distributed to the flip-flops so that the delay variation does not occur. As is clear from the comparison of FIG. 1 as one embodiment of the present invention, since the clock skew is devised from the viewpoint of clock distribution, as the size of the semiconductor integrated circuit becomes larger,
Since it is increasingly difficult to reduce clock skew, and furthermore, CMOS circuits, which are the mainstream technology in recent years, tend to have large variations in delay even within the same integrated circuit. It is becoming difficult to reduce the minimum delay circuit size between them. The "clock signal distribution circuit" disclosed in Japanese Patent Application Laid-Open No. 6-204828, as shown in FIG.
Delay circuits M11 to M18 having a hierarchical structure having output signals from clock buffers M15 and M16 are arranged, and data is input to clock signal b of flip-flop 11 which outputs data in sequential circuit groups (flip-flops 11 to 14). The clock signal a of the flip-flop 12 is set to be slower. Therefore, this clock signal distribution circuit is connected to flip-flop 1 to which data is input.
Flip-flop 11 for outputting data after operation 2
Operates, but since the delay amounts of the clock buffers M15 and M16 are not specified, hardware with a clock buffer more than a necessary minimum may be inserted.
There is a possibility that the accommodating property of the SI and the wiring property are deteriorated.

The main object of the present invention is not to reduce the scale of the minimum delay circuit from the viewpoint of reducing clock skew, which is inconsistent with the progress of a semiconductor integrated circuit which is becoming huge, but to allow clock skew to some extent and to reduce An object of the present invention is to provide a data transfer circuit which has a minimum delay circuit scale and which is the best in terms of high-speed data processing, by devising a distribution method of the distribution circuit.

[0008]

According to a data transfer circuit of the present invention, in a data transfer circuit including a plurality of flip-flops and having a pipeline, a clock signal distributed to the pipeline is transmitted for one cycle of the clock signal. Between the flip-flops due to the skew occurring in the clock signal and the delay time of the clock signal, and the delay time of the signal shifted at regular intervals is distributed to each flip-flop. Is larger than the minimum delay time.

Further, the data transfer circuit of the present invention is a data transfer circuit called a pipeline composed of a plurality of flip-flops. In order to distribute the clock signal to the pipeline, one cycle of the clock signal is used. And a pipeline in which the outputs of the signals shifted at regular intervals of the delay circuit array are connected in reverse order of the output of the data signals of the pipeline.

A signal in which one cycle of the clock signal is regularly shifted by a predetermined interval is a signal generated by the skew generated in the clock signal and the delay time of each flip-flop.
The signal is characterized by being longer than the minimum delay time between flops.

Further, the means for distributing to each flip-flop is characterized in that the clock signal input to the transmitting flip-flop is input later than the clock signal input to the receiving flip-flop.

The present invention relates to a data transfer (pipeline) circuit composed of a plurality of flip-flops,
By distributing the clock signal distributed to the flip-flops constituting the pipeline at regular intervals, a minimum signal between the flip-flops due to the skew (phase difference) generated in the clock signal is obtained. It is characterized in that a data transfer circuit can be configured without considering delay.

Therefore, in the data transfer circuit of the present invention, by distributing a signal in which the input clock signal between flip-flops for performing data transfer is regularly shifted by a constant interval, the amount of hardware to be inserted is minimized. The hardware that distributes the clock signal does not require precise distribution. Further, by eliminating the need for the minimum delay circuit, the accommodating property / wiring property of the semiconductor integrated circuit is improved.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of FIG.

Referring to FIG. 1, a data transfer circuit according to the present invention receives a clock signal (CLK signal) 101 as an input,
Similarly to the delay circuit 21 that outputs the clock signal 102 that generates a fixed delay with respect to the clock signal 101,
A delay circuit 22 that receives a clock signal 102 and outputs a clock signal 103, a delay circuit 23 that receives a clock signal 103 and outputs a clock signal 104, and a data signal 201 that receives a data signal 201 as a data input.
, And similarly, the output of the flip-flop 11/12/13/14 is used as a data input, and the clock signal 103/102/10
Flip flop 1 with 1/104 clock input
2/13/14/15.

In this embodiment, the clock signal 102 is a signal obtained by delaying the clock signal 101 by １ ／ of the clock cycle.
Reference numeral 104 denotes a signal obtained by delaying each of the clock signals 102/103 by 1/4 of the clock cycle. Further, it is assumed that the delay variation (hereinafter, skew) of each clock signal is １ ／ or less of the clock cycle.

The data transfer circuit according to the present invention is characterized in that a flip-flop constituting the data transfer circuit is positively input with a clock signal which causes a delay difference. That is, the present data transfer circuit is characterized in that data transfer can be performed without being aware of the skew of the clock signal input to each flip-flop in the data transfer between the flip-flops of the components. In addition, the clock signal in which the delay difference is positively generated has regularity, and between the flip-flops for performing data transfer (for example, flip-flops 11/12), the transmitting-side flip-flop 11 is used. Is characterized in that the clock signal 104 is a signal that is delayed by 1/4 clock cycle from the clock signal 103 that is the clock input of the receiving flip-flop 12. That is, the input clock signal of the transmission-side flip-flop is always a signal delayed from the input clock signal of the reception-side flip-flop.

In this embodiment, the clock signal 102
With respect to the clock signal 101,
4 and a clock signal 1
03/104 is a signal obtained by delaying each of the clock signals 102/103 by １ ／ of the clock cycle. However, the clock signal 102 may be a signal obtained by delaying the clock signal 101 by １ ／ of the clock cycle,
The signal may be a signal delayed by / 5. The signal delayed by the clock cycle can be determined according to the sum of the skew of the delay circuit and the delay time of the flip-flop.

Next, the operation of this data transfer circuit will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

As a precondition, the clock signal 102 is
The clock signal 101 is a signal obtained by delaying the clock signal 101 by 遅 延 of the clock cycle by the delay circuit 21.
3/104 are assumed to be signals obtained by delaying the clock signal 102/103 by 遅 延 of the clock cycle by the delay circuits 22/23, respectively. That is, clock signal 1
02, 103, and 104 correspond to the clock signal 101, respectively.
The signal is delayed by 3/4 clock cycle.

The data transfer from the flip-flop 11 to the flip-flop 12 will be described as an example. Since the input clock signal 104 of the flip-flop 11 is a clock signal delayed by １ ／ of the clock period with respect to the clock signal 103 of the flip-flop 12, the maximum data transfer from the flip-flop 11 to the flip-flop 12 is performed. The delay is required to be ／ of the clock cycle. However, even if delay variation (clock skew) occurs in the clock signal 103 in the earlier delay,
If the period is equal to or less than ４ of the clock cycle, the flip-flop 11 erroneously causes the flip-flop 12 to use the clock obtained by taking in the data signal 201.
There is no need to worry about taking in one data output (strictly speaking, the sum of the clock skew and the hold time of the flip-flop is １ ／ or less of the clock cycle). This eliminates the need for the data transfer circuit designer to design such that the minimum delay of the transfer between flip-flops can be satisfied while being aware of the clock skew, as in the related art. It is possible to reduce the hardware required for satisfying. In addition, the hardware for distributing the clock signal does not require precise distribution, and it is expected that the accommodating property / wiring property in the semiconductor integrated circuit is improved.

In the present embodiment, the data transfer circuit in which the clock signal returns to the original state at the five stages of the flip-flops 11 to 15 is taken as an example.
There is a demerit that the maximum value of the maximum delay of the data transfer between 5 is 3/4, but the delay difference of the input clock signal of each flip-flop is less than the clock skew caused by the performance of the semiconductor integrated circuit. It should be noted that the clock skew is generally about 1/10 or less of the clock cycle, so that the disadvantage of the maximum delay and the effect can be extremely small.

[0023]

As described above, a plurality of flips
In a data transfer (pipeline) circuit composed of flops, by distributing a signal shifted by a predetermined interval (clock skew or more) to clock signals distributed to flip-flops constituting the pipeline, The data transfer circuit can be configured without being aware of the minimum delay between flip-flops due to skew (phase difference) generated in the signal, reducing the hardware required to satisfy the minimum delay It is possible to do.

Further, according to the present invention, the hardware for distributing the clock signal does not require precise distribution, and the accommodating / wiring property in the semiconductor integrated circuit is improved.

Furthermore, according to the present invention, the clock skew is allowed to some extent and the distribution method of the clock distribution circuit is devised. As a result, the minimum delay circuit scale and the high-speed data processing can be obtained. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of FIG.

FIG. 3 is a diagram illustrating a conventional distribution logic of a clock signal.

FIG. 4 is a block diagram showing another conventional clock signal distribution circuit.

[Explanation of symbols]

11, 12, 13 Flip flops constituting the pipeline 14, 15 Flip flops constituting the pipeline 21, 22, 23 Delay circuit 101 Clock signal 102 Clock signal delayed by 1/4 cycle of clock signal 103 Clock signal Clock signal delayed by 2/4 cycle 104 Clock signal delayed by 3/4 cycle of clock signal 104

Claims (6)

[Claims] 2. A data transfer circuit comprising a plurality of flip-flops and having a pipeline, wherein a clock signal distributed to the pipeline is obtained by shifting a signal obtained by periodically shifting one cycle of the clock signal by a predetermined interval. Means for distributing the signals to flops, wherein a delay time of the signal shifted at a predetermined interval is longer than a minimum delay time between flip-flops due to a skew generated in the clock signal and a delay time of each flip-flop. Data transfer circuit. 2. A signal in which one cycle of the clock signal is regularly shifted by a constant interval is a signal longer than a minimum delay time between flip-flops due to a skew generated in the clock signal and a delay time of each flip-flop. 2. The data transfer circuit according to claim 1, wherein: 3. The means for distributing to each of the flip-flops comprises: a clock signal input to a transmitting-side flip-flop;
2. The data transfer circuit according to claim 1, wherein the data is input later than a clock signal input to the receiving flip-flop. 4. A data transfer circuit having a pipeline composed of a plurality of flip-flops, wherein one cycle of the clock signal is regularly shifted by a constant interval in order to distribute a clock signal to the pipeline. A data transfer circuit, comprising: a delay circuit array for outputting a delayed signal; and a pipeline formed by connecting the outputs of the signals shifted by a predetermined interval in the delay circuit array in the reverse order of the output of the data signal of the pipeline. 5. A signal obtained by periodically shifting one cycle of the clock signal by a predetermined interval is a signal larger than the minimum delay time between flip-flops due to the skew generated in the clock signal and the delay time of each flip-flop. 5. The method according to claim 4, wherein
Data transfer circuit as described. 6. A clock signal input to a transmission side flip-flop by the pipeline,
5. The data transfer circuit according to claim 4, wherein the clock signal is input later than the clock signal input to the receiving flip-flop.