KR20030054335A - Synchronous semiconductor device - Google Patents

Abstract

PURPOSE: A synchronous semiconductor device is provided to reduce the clock skew and the signal delay by equalizing loads of end-terminal clock buffers of a clock tree. CONSTITUTION: Clock buffers(310-340) of a second clock buffer unit(300) drive a plurality of flip-flops or dummy cells(400a,400L,400p). The clock buffers(310,330) drive four flip-flops(400a-400d), while the clock buffers(320,340) drive three flip-flops(400e-400g, 400m-400o). There is a difference between load capacities of the clock buffers(310,330) driving the four flip-flops(400a-400d) and the clock buffers(320,340) driving the three flip-flops(400e-400g, 400m-400o). In order to make the clock buffers(320,340) have a load identical to that of the clock buffer(310,330), the output terminal of the clock buffers(320,340) is loaded.

Description

Synchronous Semiconductor Device

The present invention relates to a synchronous semiconductor device having a clock tree, and more particularly, to a synchronous semiconductor device having reduced clock delay time and skew without adjusting a metal line of the semiconductor device.

In general, a logic circuit or a system operating in synchronization with a clock is often operated in synchronization with a precise clock, and a clock source and a clock source are used to stably supply the clock to the logic circuit or the system with a constant timing. In many cases, a clock buffer is provided between the logic circuits.

The clock buffer pulls up or pulls down the clock applied from the clock source to prevent the waveform of the clock source from being distorted and to sufficiently drive the multiple logic gates to which it is connected.

Here, it may be considered to supply a clock source to all logic circuits requiring a clock in parallel to the clock. However, as is well known, the number of logic circuits that the digital logic circuit can simultaneously drive is the digital logic circuit. There is a limit depending on the current capacity output.

This is commonly referred to as fan-out, and the current capacity of the clock source is also limited, so that many logic circuits or systems synchronized to the same clock need a clock buffer to stably receive the clock source. do.

1 is a block diagram of a clock tree inside a synchronous semiconductor according to the related art.

A plurality of flip-flops are driven by the first clock buffer unit 20 and the first clock buffer unit 20 for driving the second clock buffer unit 30 by receiving the output of the clock source 10. And a second clock buffer section 30 for driving 40a to 40n.

Hereinafter, a clock tree forming method having the above-described configuration will be described with reference to FIG. 1.

As shown in FIG. 1, the clock buffers 31 to 34 of the second clock buffer unit 30 drive a plurality of flip-flops 40a to 40n, and the clock buffers 31 and 33 are four flip-flops. The clock buffers 32 and 34 are driving three flip-flops.

Accordingly, a difference occurs between the load capacities of the clock buffers 31 and 33 driving four flip flops and the load capacities of the clock buffers 32 and 34 driving three flip flops each.

Here, the flip-flops 40a to 40n have capacitive loads and resistive loads with respect to the clock buffers 31 to 34, and the capacitive loads and the resistive loads allow the clock output from the clock buffer to be delayed. It will play a role.

In addition, when the loads applied to the respective clock buffers 31 to 34 are different, a problem arises in that the timing of the clock applied to each of the flip-flops 40a to 40n varies.

This is commonly referred to as skew, and it is difficult for an integrated circuit that requires accurate timing to operate at high speed due to a different timing of the clock reaching each flip-flop.

Accordingly, in order to solve the problem of the clock tree as described above, the clock buffer is increased or decreased by increasing or decreasing the length of the metal line between the clock buffers 32 and 34 and the flip-flops 40e to 40g and 40l to 40n. We tried to solve this problem by balancing the loads of (31, 33) and clock buffers (32, 34).

Meanwhile, with the development of integrated circuit technology, the width of metal lines in integrated circuits is decreasing to increase the degree of integration of integrated circuits.

That is, as the width of the metal line decreases, the resistance value of the metal line per unit length increases, and the capacitive load between the metal lines also increases as the degree of integration increases.

Therefore, in the conventional method of adjusting the load by increasing or decreasing the length of the metal line, since the signal delay caused by the metal line becomes larger than the delay caused by the flip-flop, the entire clock is delayed by the delay times of the clock buffers 32 and 34. There is a problem that the delay time of the tree is determined.

That is, the operation speed of all the clock buffers is determined at the delay time of the clock buffers 32 and 34 having the slowest operation speed by using the metal line to match the entire synchronization of the clock tree.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a synchronous semiconductor device which reduces clock delay and skew generated when a clock source is supplied by a clock tree composed of a plurality of buffers. There is this.

1 is a block diagram of a conventional synchronous semiconductor internal clock tree;

2 is a block diagram of a synchronous semiconductor internal clock tree according to the present invention;

* Explanation of symbols for the main parts of the drawings

100: clock source 200: first clock buffer unit

300: second clock buffer unit 400a to 400p: flip-flop and dummy cell

In order to solve the above problems, the present invention provides a synchronous semiconductor device having a plurality of loads driven in synchronization with a clock supplied by a clock tree, wherein at least one of the last clock buffers of the clock tree has the same load. It characterized in that it comprises a dummy load.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a synchronous semiconductor internal clock tree according to the present invention.

As shown in FIG. 2, the clock buffers 310 to 340 of the second clock buffer unit 300 drive a plurality of flip-flops or dummy cells 400a to 400p, and the clock buffers 310 and 330 are four. Four flip-flops 400a to 400d, but the clock buffers 320 and 340 drive three flip-flops 400e to 400g and 400m to 400o.

Therefore, a difference occurs between the load capacities of the clock buffers 310 and 330 driving four flip flops and the load capacities of the clock buffers 320 and 340 driving three flip flops.

As described above, when the clock tree is formed in the integrated circuit, if the loads on the respective clock buffers are different from each other, a problem arises in that the clocks arrive at different logic gates connected to the respective clock buffers.

Accordingly, as described above, a flip-flop or other logic circuit similar to the load of the flip-flop (for example 400a) is connected to the clock buffers 310 to 340 having different loads.

This is called a dummy cell, and loads are applied to the output terminals of the clock buffers 320 and 340 so that the clock buffers 320 and 340 have the same load as the clock buffers 310 and 330.

Also, since the dummy cell only needs to operate as a load on the connected clock buffer, there is no need to generate any output signal.

If the clock buffers 320 and 340 each have only two flip-flops as loads, the dummy cells 400h and 400p are configured to have twice the load than the flip-flops (eg 400a). Just add

Therefore, the loads applied to the respective clock buffers 310 to 340 are the same, and the clock supplied from the clock source 100 reaches almost the same timing on the respective flip-flops and the dummy cells 400a to 400p. It can alleviate skew.

In addition, although the degree of integration of an integrated circuit increases and accordingly the width of a metal line constituting the integrated circuit decreases, the present invention forms a clock tree for supplying a clock supplied from the clock source 100 to a plurality of logic gates. Since dummy cells are used, they are hardly affected by signal delay due to metal lines.

In the present invention, a flip-flop is used as the load of the clock buffers 310 to 340 as an example. However, any logic circuit connected to the clock buffers 310 to 340 and operated by receiving a clock may be connected. It is not limited to.

As described above, the synchronous semiconductor device, which is provided in the synchronous semiconductor device and has the same load of the clock buffer as the last stage of the clock tree for supplying the clock source to the synchronous semiconductor device, thereby reducing clock skew and signal delay. The device can be implemented.

Claims (1)

A synchronous semiconductor device having a plurality of loads driven in synchronization with a clock supplied by a clock tree, And at least one dummy load such that the last clock buffers of the clock tree all have the same load.