JP2001168204A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a construction by which a transistor comprising a protective circuit can perform its functions even if the semiconductor device is highly integrated and is operated at high-speed. SOLUTION: The semiconductor device is provided with a well region 5a of first conductive type in which a protective circuit is formed, and a well region 4 of second conductive type containing a high concentration of impurities whose upper part is separated by an element isolation region 2 and whose part lower than the bottom of the element isolation region is bonded. The well region of first conductive type intrudes the well area of second conductive type across the element isolation region or intrudes the region of second conductive type by a half of the width of the element isolation region. An overcurrent does not flow between source/drain region of the transistor as protective circuit, but comes into contact with the part of the well region of first conductive type intruding the well region of second conductive region with a depletion layer being extending from the drain region, and flows between the drain region and the part intruding the well region of second conductive type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a protection circuit for protecting a main circuit from electrostatic breakdown and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high integration and high speed of semiconductor devices such as ICs and LSIs have been promoted. for that reason,
The concentration of the source / drain region of the transistor is increased. Therefore, the LDD transistor whose electric field has been relaxed and Conv. The withstand voltage difference between the transistors is eliminated, and the main body is destroyed before the protection transistor used as a protection circuit to prevent electrostatic breakdown when a surge is applied. FIG. 8 is a circuit diagram showing a protection circuit for protecting a main body circuit formed in a conventional semiconductor device from electrostatic breakdown. FIG. 9 is a cross-sectional view of a MOS transistor having an LDD (Lightly Doped Drain) structure used for its main circuit, and FIG. 10 is a cross-sectional view of a conventional MOS transistor used for a protection circuit. The present invention is characterized by the well region in which the transistor is formed, and therefore, the protection circuit and the transistor shown in FIGS. 8 and 9 are also used for the present invention. FIG.
In FIG. 9, a main circuit formed on a semiconductor substrate is composed of, for example, a memory, a logic, and the like, and mainly uses an LDD transistor shown in FIG. A protection circuit is connected between the main body circuit and its external terminals. The protection circuit includes a MOS transistor PTr.

For example, a P-type or N-type silicon semiconductor substrate 11 is used as the transistor of the main circuit of FIG. The semiconductor substrate 11 has, for example, an STI (Shallow Treble
An element isolation region 12 having an (nchIsolation) structure is formed. The element region surrounded by the element isolation region 12 is constituted by a P-well region 13. A P-well or N-well region 14 is formed in an adjacent element region adjacent to the P-well region 13 and separated by the element isolation region 12. For the element isolation region, a LOCOS structure or the like can be used. The impurity concentration of these well regions is, for example, about 10 ¹⁷ / cm ³ . For example, an N-type source region 15 and an N-type drain region 15a having an impurity concentration of about 10 ²⁰ / cm ³ are formed in the P-well region 13,
Further, an LDD structure 16 having a lower concentration than the source region 15 and the drain region 15a is formed at the tips thereof to increase the breakdown voltage of the transistor. A gate electrode 18 made of polysilicon or the like is formed between the source region 15 and the drain region 15a via a gate oxide film 17, and a side wall insulating film 19 made of a silicon nitride film or the like is formed on the side wall of the gate electrode 18. Are formed.

On the other hand, the transistor used in the conventional protection circuit shown in FIG. 10 uses, for example, a P-type or N-type silicon semiconductor substrate 21 as in FIG. Semiconductor substrate 2
1, an element isolation region 22 having, for example, an STI structure is formed. The element region surrounded by the element isolation region 22 is
The P well region 23 is formed. A P-well or N-well region 24 is formed in an adjacent element region adjacent to the P-well region 23 and separated by the element isolation region 22. The impurity concentration of these well regions is, for example, about 10 ¹⁷ / cm ³ . In the P-well region 23, for example, an N-type source region 25 and an N-type drain region 25a having an impurity concentration of about 10 ²⁰ / cm ³ are formed. A gate electrode 28 made of polysilicon or the like is formed between the source region 25 and the drain region 25a with a gate oxide film 27 interposed therebetween, and a side wall insulating material such as a silicon nitride film is formed on the side wall of the gate electrode 28. Membrane 2
9 are formed.

[0005]

Conventionally, a semiconductor device has
As shown in FIG. 8, a protection circuit is used to protect the main circuit of the semiconductor device from electrostatic breakdown. As the protection circuit, while the main body circuit uses an MOS transistor having an LDD structure, for example, an NMOS transistor (Conv) having a conventional structure shown in FIG. 10 is used. As shown in FIG. 11, a transistor having a conventional LDD structure (conventional LDD) has a high withstand voltage.
Conventional MOS transistor (Con
v), the overcurrent applied to the main circuit is released to the semiconductor substrate by utilizing the difference in withstand voltage. However, current transistors with LDD structure (LD
In D), the gate length is small, and the impurity concentration in the LDD region is increased in order to suppress the short channel effect and increase the driving force. Therefore, the current transistor of LDD structure (LD
The withstand voltage of D) is reduced, and the difference in withstand voltage is significantly reduced.

As described above, as a result of high integration and high speed of a semiconductor device, even if an LDD structure is used for a transistor used in a main circuit, a transistor (LDD) with high integration and high speed of a main circuit is used. And protection circuit transistor (C
onv) is very small as compared with the case where a transistor having a conventional LDD structure is used. In FIG. 11, the vertical axis represents the current I (A) and the horizontal axis represents the breakdown voltage V (V). The transistor withstand voltage of the current LDD structure is lower than that of the conventional LDD structure transistor. As a result, the withstand voltage difference between the transistor of the protection circuit and the transistor of the protection circuit is small, the function as the protection circuit is not sufficient, and an overcurrent flows to the main body circuit. At present, there is a problem of fear. The present invention has been made in view of the above circumstances, and a semiconductor device in which a transistor included in a protection circuit can sufficiently perform its function even when the integration and speed of the semiconductor device have been increased, and a manufacturing method thereof. Provide a way.

[0007]

According to the present invention, there is provided a first conductivity type well region in which a protection circuit is formed, and an upper portion of the first conductivity type well region is separated from an element isolation region. Below, the high impurity concentration second
A first conductivity type well region, wherein the first conductivity type well region extends into the second conductivity type well region beyond the element isolation region, or a half of the width of the element isolation region. It is further characterized in that it enters the second conductivity type region side. When an overcurrent is applied to the external terminal of the main circuit, the overcurrent does not flow between the source / drain regions of the transistor of the protection circuit, but the depletion layer extends from the drain region and the second current of the first conductivity type well region.
The flow comes into contact between the drain region and the portion that has entered the second conductivity type well region by contacting the portion that has entered the conductivity type well region. That is, the distance between the second conductive type well region and the portion that has entered the well region is formed to be shorter than the distance (gate length) between the source / drain regions. By forming a passage (drain region-portion of the first conductivity type well region that has entered the second conductivity type well region) more easily than the source / drain region flows, the transistor constituting the protection circuit is formed. Can improve the protection function.

That is, in the semiconductor device of the present invention, a semiconductor substrate in which a plurality of element regions are partitioned by an element isolation region; a first conductivity type well region formed in the semiconductor substrate; Formed in the first
A second conductivity type well region separated from the first conductivity type well region by the element isolation region; and the first conductivity type well region enters the second conductivity type well region beyond the element isolation region. It is characterized by doing so. A protection circuit may be formed in a predetermined region of the second conductivity type well region. The protection circuit may include a first conductivity type MOS transistor. The first conductivity type well region may have a higher impurity concentration than the second conductivity type well region. The impurity concentration of the first conductivity type well region adjacent to the second conductivity type well region where the protection circuit is formed is not adjacent to the second conductivity type well region where the protection circuit is formed. The impurity concentration may be higher than that of the first conductivity type well region. In addition, the semiconductor device of the present invention includes a semiconductor substrate formed by dividing a plurality of element regions by element isolation regions, a first conductivity type well region formed in the semiconductor substrate, and a semiconductor substrate formed in the semiconductor substrate. A first conductivity type well region and a second conductivity type well region separated by the device isolation region, wherein the first conductivity type well region has a second width larger than half the width of the device isolation region. It is characterized in that it enters the conductive type well region side.

Further, the semiconductor device according to the present invention includes a semiconductor substrate formed by dividing a plurality of element regions by element isolation regions, an N-well region formed in the semiconductor substrate, and a semiconductor substrate formed in the semiconductor substrate. A P-well region separated from the previous N-well region by the device isolation region, and the N-well region enters the P-well region side from a half of the width of the device isolation region, and The distance between the drain region of the P well region and the portion of the N well region that enters the P well region is formed to be shorter than the channel length between the source / drain regions. With this configuration, a passage (a portion between the drain region and the N-well region that enters the P-well region) in which an overcurrent flows more easily than between the source / drain regions is formed, and a protection circuit is formed. The protection function of the transistor can be improved. Since the breakdown voltage of the N-well region is smaller than before,
The withstand voltage difference from the transistor having the DD structure can be increased. A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a plurality of element regions defined by element isolation regions on a semiconductor substrate; and ion-implanting a first conductivity type impurity into a predetermined element region of the semiconductor substrate. Forming a second conductivity type well region by ion-implanting a second conductivity type impurity into another element region of the semiconductor substrate, wherein the first conductivity type well region is formed. The ion implantation amount of the first conductivity type well region is larger than the ion implantation amount of the second conductivity type well region so that the first conductivity type well region enters the second conductivity type well region beyond the element isolation region. Features. The method may further include a step of forming a protection circuit in a predetermined region of the second conductivity type well region.

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
Forming a plurality of device regions defined by device isolation regions on the semiconductor substrate; forming a first conductivity type well region by diffusing first conductivity type impurities into predetermined device regions of the semiconductor substrate; Forming a second conductivity type well region by diffusing a second conductivity type impurity into another element region of the semiconductor substrate; and implanting a first conductivity type ion into the first conductivity type well region and performing heat diffusion. Wherein the ion implantation and the heat diffusion process allow the first conductivity type well region to enter the second conductivity type well region beyond the element isolation region. Also,
A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a plurality of element regions defined by element isolation regions on a semiconductor substrate; and ion-implanting a first conductivity type impurity into a predetermined element region of the semiconductor substrate. Forming a second conductivity type well region by ion-implanting a second conductivity type impurity into another element region of the semiconductor substrate, wherein the first conductivity type well region is formed. Is larger than the ion implantation amount of the second conductivity type well region, and the first conductivity type well region enters the second conductivity type well region side from half the width of the element isolation region. It is characterized by doing so.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a plurality of device regions defined by device isolation regions on the semiconductor substrate; forming a first conductivity type well region by diffusing first conductivity type impurities into predetermined device regions of the semiconductor substrate; Forming a second conductivity type well region by diffusing a second conductivity type impurity into another element region of the semiconductor substrate; and implanting a first conductivity type ion into the first conductivity type well region and performing heat diffusion. Wherein the first conductivity type well region enters the second conductivity type well region side from a half of the width of the element isolation region by the ion implantation and heat diffusion steps. Method.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. FIG. 1 is a schematic cross-sectional view showing a protection circuit portion of a semiconductor device, and FIGS. 2 to 4 are cross-sectional views of manufacturing steps of the semiconductor device. This semiconductor device uses, for example, a P-type or N-type silicon semiconductor substrate 1 for forming a transistor. In the semiconductor substrate 1, for example, an element isolation region 2 having an STI structure in which silicon oxide is embedded is formed. The element region surrounded by the element isolation region 2 is constituted by a P-well region 4. An N-well region 5a is formed in an adjacent device region adjacent to the P-well region 4 and separated by the device isolation region 2. The impurity concentration of the P well region 4 is, for example, about 10 ¹⁷ / cm ³ , and the impurity concentration of the N well region 5 a adjacent to the P well region 4 is about three times that of the P well region 4. The P well region 4 has, for example, an impurity concentration of 10 ²⁰ / cm ^3.
Impurity diffusion regions such as the N-type source region 8a and the N-type drain region 8 are formed. A gate oxide film (SiO ₂ ) 6 is formed between the source region 8 a and the drain region 8.
A gate electrode 6 made of polysilicon or the like is formed via a, and a side wall insulating film 7 made of a silicon nitride film or the like is formed on the side wall of the gate electrode 6.

The source region 8a and the N well region 5a are
It is grounded (GND). Also, the drain region 8
Connected to power supply 9. A P-well or N-well region 5c is formed in the other element region adjacent to the P-well region 4 and separated from the element isolation region 2. The impurity concentration of the P well or N well region 5c is, for example, 1
It is about 0 ¹⁷ / cm ³ . The N well region 5a enters the P well region beyond the bottom of the element isolation region 2. As a result of this configuration, when an overcurrent is applied to the external terminal 9, the overcurrent does not flow between the source region 8a and the drain region 8 of the transistor forming the protection circuit, but flows from the drain region 8 to the depletion layer. Extends into contact with the portion 5b of the N-well region that has entered the P-well region, and flows between the drain region 8 and the portion 5b that has entered the P-well region. That is, the distance between the drain region 8 and the portion 5b of the N-well region 5a that enters the P-well region is formed to be shorter than the distance (channel length) between the source / drain regions 8a and 8. And
By forming a passage (over a portion of the drain region 8-N well region 5a that enters the P well region) where an overcurrent flows more easily than between the source / drain regions, the protection function of the transistor constituting the protection circuit is improved. be able to. Since the breakdown voltage of the N-well region is smaller than before, LDD
The withstand voltage difference from the transistor having the structure can be increased (see FIG. 12).

Next, the manufacturing process of the semiconductor device of FIG. 1 will be described with reference to FIGS. First, the surface region of the P-type or N-type silicon semiconductor substrate 1 is RIE (Reactive Ion).
Etching is performed by, for example, etching to form a groove having a predetermined pattern in order to form an element isolation region. next,
CVD (Chemical Vapor Deposition)
position) silicon oxide film (TEOS film)
Is deposited. This silicon oxide film is applied from the surface to CMP (C
The silicon oxide film other than the groove is removed by polishing using a chemical mechanical polishing method, thereby forming an element isolation region 2 having an STI structure in which the silicon oxide film is embedded in the groove.
The element isolation region 2 partitions a plurality of element regions (FIG. 2A). Next, a photoresist 3 is formed on the semiconductor substrate 1 by lithography, and the photoresist 3 is patterned to open the surface of the element region where the P-well region is formed. Then, impurity ions such as B + are implanted into the opened element region to form a P well region 4 (FIG. 2).
(B)). Then, after removing the photoresist 3,
A photoresist 3a is again formed on the semiconductor substrate 1 by lithography, and the photoresist 3a is patterned to open the surface of an element region where an N-well region is to be formed.

Then, an impurity ion such as P + is implanted into the opened element region to form an N well region 5 adjacent to the P well region 4 previously formed. The dose at this time is about three times that when the P well region 4 is formed (FIG. 3A). Next, when the semiconductor substrate 1 is subjected to a heat treatment after removing the photoresist 3a, the N-well region 5 receives a dose amount of about three times that of the P-well region 4, so that the region is enlarged and the P-well region 4 is enlarged. Go in and go to P
An N-well region 5a having a portion 5b penetrating into the well region is formed (FIG. 3B). Next, a MOS transistor having a conventional structure used as a protection circuit is formed in the P-well region 4 in which the adjacent N-well region 5a enters. A gate oxide film (SiO ₂ ) 6a is formed on the surface of the P well region 4 by heat treatment. Then, the polysilicon film formed on the semiconductor substrate 1 is patterned by lithography to form a gate electrode 6 made of polysilicon on the gate oxide film 6a. A silicon nitride film (SiN) is deposited on the semiconductor substrate 1 including the gate electrode 6 and anisotropically etched by RIE or the like to form a sidewall insulating film 7 made of a silicon nitride film on the gate sidewall. Then, the silicon nitride film existing in other portions is removed (FIG. 4A).

Next, N-type impurity ions such as As + and P + are implanted into the P-well region 4 of the semiconductor substrate 1 by lithography to form an N-type impurity diffusion region, which is formed into a source region 8a and a drain region. 8 (FIG. 4
(B)). Thereafter, the N well region 5a and the source region 8
a is grounded (GND) (see FIG. 1). The distance between the drain region and the portion of the N-well region that enters the P-well region is formed to be shorter than the distance (channel length) between the source / drain regions. The protection function of the transistor constituting the protection circuit is improved by forming a passage (the portion between the drain region and the N-well region that enters the P-well region) more easily than the source / drain region. be able to. Since the breakdown voltage of the N-well region is smaller than in the conventional case, the difference in breakdown voltage from the transistor having the LDD structure can be increased.

Next, a second embodiment will be described with reference to FIGS. 5 to 7 are cross-sectional views illustrating a manufacturing process of the semiconductor device. This embodiment is characterized by a manufacturing process.
This semiconductor device is different from the semiconductor device of the first embodiment in the impurity concentration distribution of the N-well region adjacent to the P-well region where the protection circuit is formed and separated by the element isolation region. Is the same. That is, the impurity concentrations of the P-well region 34 and the N-well region 35a are, for example, about 10 ¹⁷ / cm ³ , and the N-well region 35a adjacent to the P-well region 34 enters the P-well region 34 and the portion 35b. The portion 35d including the vicinity has an impurity concentration higher than that of the P-well region 34 (see FIG. 7).

First, using a P-type or N-type silicon semiconductor substrate 31, a photoresist is formed on the semiconductor substrate 31 by lithography, and the photoresist is patterned to form a photoresist.
The surface of the element region where the well region is to be formed is opened, and impurity ions such as B + are implanted into the opened element region to form the P well region. Until this step, the first
2 (a) and 2 (b) are not shown. Thereafter, after removing the photoresist, a photoresist 33a is formed again on the semiconductor substrate 1 by lithography, and the photoresist 33a is patterned to
The surface of the element region forming the well region is opened. Then, an impurity ion such as P + is implanted into the opened element region to form an N well region 35 adjacent to the P well region 34 previously formed. The dose at this time is
This is the same as when the P well region 34 is formed (FIG. 5).
(A)). Next, after removing the photoresist 33a, a photoresist 33b is formed on the semiconductor substrate 31 by lithography, and the photoresist 33b is patterned to open again the surface of the element region where the N-well region is formed.

Then, an impurity ion such as P + is implanted into the opened element region to form a high concentration region 35d at the bottom of the N well region 35 (FIG. 5B). Next, when the semiconductor substrate 31 is subjected to a heat treatment after removing the photoresist 33b, the high-concentration region 35d expands into the P-well region 34 and enters the P-well region, and an N-well having a portion 35b entering the P-well region. The region 35a is formed (FIG. 6A). Next, the adjacent N well region 35a
A MOS transistor having a conventional structure used as a protection circuit is formed in the P-well region 34 in which is embedded. A gate oxide film (SiO ₂ ) 36 a is formed on the surface of the P well region 34 by thermal oxidation. Then, the polysilicon film formed on the semiconductor substrate 31 is patterned by lithography to form a gate electrode 36 made of polysilicon on the gate oxide film 36a. A silicon nitride film (SiN) is deposited on the semiconductor substrate 31 including the gate electrode 36, and anisotropically etched by RIE or the like to form a sidewall insulating film 37 made of a silicon nitride film on the gate sidewall. Then, the silicon nitride film existing in other portions is removed (FIG. 6B). Next, N-type impurity ions such as As + and P + are implanted into the P-well region 34 of the semiconductor substrate 31 by lithography to form N-type impurity diffusion regions, which are used as a source region 38a and a drain region 38. . Thereafter, the N well region 35a and the source region 38a are grounded (GND) (FIG. 7).

The distance between the drain region and the portion of the N-well region that enters the P-well region is formed to be shorter than the distance (channel length) between the source / drain regions. By forming a passage (over the portion of the drain region-the N-well region that has entered the P-well region), the overcurrent is easier to flow than between the source / drain regions,
The protection function of the transistor included in the protection circuit can be improved. Since the breakdown voltage of the N-well region is smaller than in the conventional case, the difference in breakdown voltage from the transistor having the LDD structure can be increased. FIG. 13 is a sectional view of a semiconductor substrate in which the protection circuit shown in FIG. 1 is connected to a peripheral circuit of a semiconductor device such as a memory. MOS transistors Tr1 and Tr2 are formed in the P-well region and the N-well region in the peripheral circuit. In the protection circuit, a MOS transistor Tr in which a gate electrode and a source region 8a are short-circuited is formed in a P-well region 4, and an N-well region 5a adjacent via an element isolation region (STI) 2 is a high-concentration region. (For example, about three times the P-well region). This N-well region 5
a is grounded (GND), and normally no transistor is formed. Overcurrent flowing into the semiconductor device from the outside is prevented from flowing from the drain region 8 of the protection circuit to the N well region 5.
b to protect peripheral circuits.

[0021]

According to the present invention, when overcurrent is applied to the external terminal of the main circuit, the overcurrent does not flow between the source / drain regions of the transistor of the protection circuit.
A depletion layer extends from the drain region and contacts a portion of the first conductivity type well region that has entered the second conductivity type well region,
Since the current flows between the drain region and the portion that has entered the second conductivity type well region, the protection function of the transistor forming the protection circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of an apparatus according to a first embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment;

FIG. 5 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment;

FIG. 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 8 is a circuit diagram showing the present invention and a conventional protection circuit.

FIG. 9 shows an LDD used in the present invention and a conventional semiconductor device.
Sectional drawing of the MOS transistor of a structure.

FIG. 10 is a cross-sectional view of a conventional MOS transistor having a conventional structure used in a protection circuit.

FIG. 11 shows a conventional transistor having a conventional LDD structure and a conventional MOS transistor (Co).
FIG. 6 is a characteristic diagram showing a withstand voltage difference from FIG.

FIG. 12 is a characteristic diagram showing a breakdown voltage of an N-well region according to the present invention.

FIG. 13 is a cross-sectional view of a semiconductor device to which a protection circuit of the present invention is connected.

[Explanation of symbols]

1, 11, 21, 31 ... semiconductor substrate, 2, 1
2, 22, 32 ... element isolation region, 3, 3a, 33
a, 33b photoresist, 4, 13, 23, 3
4 ... P-well region, 5, 5a, 5c, 14, 2
4, 35, 35a, 35c... N-well region, 5
b: Entrance of N-well region, 6, 18, 2
8 ... gate electrode, 6a, 17, 27, 36a
..Gate oxide films, 7, 19, 29, 37 ... sidewall insulating films, 8, 15a, 25a, 38 ... drain regions, 8a, 15, 25, 38a ... source regions, 9 ... Power supply, 35d... High concentration region in N-well region.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) CC19 DA27

Claims (12)

[Claims] A first conductivity type well region formed on the semiconductor substrate; a first conductivity type well region formed on the semiconductor substrate; a first conductivity type well region formed on the semiconductor substrate; A conductive type well region having a second conductive type well region separated by the element isolation region; and the first conductive type well region entering the second conductive type well region beyond the element separation region. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, wherein a protection circuit is formed in a predetermined region of the second conductivity type well region. 3. The protection circuit according to claim 2, wherein the protection circuit comprises a first conductivity type MOS transistor.
3. The semiconductor device according to claim 1. 4. The first conductivity type well region includes:
4. The semiconductor device according to claim 1, wherein the impurity concentration is higher than the conductivity type well region. 5. The second circuit in which the protection circuit is formed.
The impurity concentration of the first conductivity type well region adjacent to the conductivity type well region is lower than that of the first conductivity type well region not adjacent to the second conductivity type well region where the protection circuit is formed. 2. The method according to claim 1, wherein
The semiconductor device according to claim 3. 6. A semiconductor substrate in which a plurality of element regions are divided by element isolation regions, a first conductivity type well region formed in the semiconductor substrate, and a first conductive type well region formed in the semiconductor substrate. A conductivity type well region, a second conductivity type well region separated by the device isolation region, wherein the first conductivity type well region has a second conductivity type well region larger than half the width of the device isolation region. A semiconductor device which is inserted into a side. 7. A semiconductor substrate in which a plurality of element regions are partitioned by element isolation regions, an N-well region formed in the semiconductor substrate, and a front N-well region formed in the semiconductor substrate. A P-well region separated by the element isolation region, wherein the N-well region enters the P-well region side from a half of the width of the element isolation region, and is connected to a drain region of the P-well region. A semiconductor device, wherein a distance between the N-well region and a portion of the N-well region that enters the P-well region is shorter than a channel length between the source / drain regions. 8. A step of forming a plurality of device regions defined by device isolation regions in a semiconductor substrate, and ion-implanting a first conductivity type impurity into a predetermined device region of the semiconductor substrate to form a first conductivity type well region. Forming a second conductivity type well region by ion-implanting a second conductivity type impurity into another element region of the semiconductor substrate. The ion implantation amount of the first conductivity type well region is: , The second
The amount of ion implantation in the well of the conductivity type is increased,
The conductivity type well region extends beyond the element isolation region and the second region is formed.
A method for manufacturing a semiconductor device, wherein the semiconductor device is inserted into a conductive well region. 9. The method according to claim 8, further comprising a step of forming a protection circuit in a predetermined region of the second conductivity type well region. 10. A step of forming a plurality of device regions defined by device isolation regions on a semiconductor substrate, and forming a first conductivity type well region by diffusing a first conductivity type impurity into a predetermined device region of the semiconductor substrate. Forming a second conductivity type well region by diffusing a second conductivity type impurity into another element region of the semiconductor substrate; and implanting a first conductivity type ion into the first conductivity type well region. A semiconductor diffusion step, wherein the first conductivity type well region enters the second conductivity type well region beyond the element isolation region by the ion implantation and the heat diffusion process. Device manufacturing method. 11. A step of forming a plurality of device regions defined by device isolation regions in a semiconductor substrate, and ion-implanting a first conductivity type impurity into a predetermined device region of the semiconductor substrate to form a first conductivity type well region. Forming a second conductivity type well region by ion-implanting a second conductivity type impurity into another element region of the semiconductor substrate. The ion implantation amount of the first conductivity type well region is: , The second
The amount of ion implantation in the well of the conductivity type is increased,
A method for manufacturing a semiconductor device, characterized in that a well of a conductivity type enters a side of a second conductivity type well from a half of a width of the element isolation region. 12. A step of forming a plurality of element regions defined by an element isolation region on a semiconductor substrate, and forming a first conductivity type well region by diffusing a first conductivity type impurity into a predetermined element region of the semiconductor substrate. Forming a second conductivity type well region by diffusing a second conductivity type impurity into another element region of the semiconductor substrate; and implanting a first conductivity type ion into the first conductivity type well region. A step of performing heat diffusion, wherein the first conductivity type well region enters the second conductivity type well region side from a half of the width of the element isolation region by the ion implantation and heat diffusion steps. Semiconductor device manufacturing method.