JP2001167570A - Line memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store even the serial data of the final cycle that are smaller than the number of bits of parallel data with no loss and then read the serial data into and out of a line memory which stores the inputted serial data after converting them into the parallel data. SOLUTION: The line memory device 100 includes a line memory macro 101 which uses serial/parallel conversion, a shift register 111 which has its capacity equal to the bit width of the data to be converted into the parallel data, a selector 109 and a control block 110 which controls the register 111 and selector 109. In such a constitution, it is possible to store all digital signals S102 in the memory 100 and then to read them out with no loss by storing the data (which cannot be stored in the macro 101) of the final cycle whose signals S102 are smaller than the number of bits of serial/parallel conversion into the register 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line memory for holding one horizontal line of video signal data using a line memory macro.

[0002]

2. Description of the Related Art Conventionally, correlation of signals stored in a line memory is performed. Since the line memory is often used, it is formed into a macro as a line macro memory.

In the case of a line memory macro using serial-to-parallel conversion in units of 8 bits, an operation is performed at a writing / reading speed that is 1/8 that of a case where serial data is written / read to / from a FIFO. Therefore, the clock frequency can be reduced to one-eighth, high-speed operation can be achieved, and power consumption can be reduced.

[0004]

Here, in order to minimize the area and power consumption, the line memory macro stores data in the memory in units of multiples of eight, and restricts data stored in units of multiples less than eight. May be imposed.

On the other hand, in recent years, due to the diversification of media and the like, the use of non-standard signals whose length in one horizontal direction is slightly different from that of standard signals is increasing. In this case, the number of sampled data is slightly different, so the number of data in one horizontal direction is not always constant and may or may not be a multiple of eight. If the number of data in one horizontal direction is not a multiple of 8, the fractional data becomes the head of the next one-line signal, and the luminance signal obtained therefrom is incorrect. There is.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. A line memory device capable of correctly storing data for each horizontal direction using a line memory macro even when the number of data in one horizontal direction is different. The purpose is to provide.

[0007]

According to a first aspect of the present invention, there is provided a line memory device comprising:
Serial-parallel conversion means for converting the serial data into first parallel data, memory means for storing the first parallel data when the first serial data is parallel-converted by a predetermined data amount, Parallel-to-serial conversion means for converting data read from the memory into second serial data, FIFO means for sequentially storing the first serial data, and outputting the serial data as third serial data; And selecting means for selecting one of the serial data. According to a second aspect of the present invention, there is provided a line memory device according to the first aspect of the present invention, wherein the selecting means determines that the first serial data is determined for a predetermined period or more. When the input data amount is not input, the data of the FOFO means is selected.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of a serial / parallel conversion circuit according to Embodiment 1 of the present invention. Hereinafter, description will be made in the order of block numbers.

Reference numeral 100 denotes a line memory device main body.
It receives a digital input signal S102 of one bit and a valid signal S103 indicating that the digital input signal S102 is valid, and outputs a digital output signal S109 of one bit.

The digital input signal S102 is a line signal in one frame of the video signal, and is a valid signal S
When 103 is asserted (high level), it is a valid signal. When the valid signal S104 is at a high level, the digital output signal S108 is valid.

Reference numeral 101 denotes a line memory macro, which includes a 1-bit digital input signal S102, a valid signal S103 indicating that the digital input signal S102 is valid,
S104 for enabling the output of the 1-bit digital output signal S108 is input, and the 1-bit digital output signal S108 is input.
108 is output.

Reference numerals 102, 103, and 104 denote a signal S102 input terminal, a signal S103 valid signal input terminal, a signal S104 valid signal input terminal, and a signal S109 output terminal, respectively.

Reference numeral 106 denotes a serial / parallel converter.
The 1-bit digital input signal S102 is converted from serial to parallel into an 8-bit parallel signal S106. When the valid signal S103 becomes valid, the digital input signal S10
No. 2 sequentially designates a bit position from the MSB to the LSB every 8 bits, stops the operation when the last data is transmitted, and repeats the same operation again from the MSB when the next data is input. That is, for each line, the first bit of the digital input signal S102 is the MS of the parallel data S106.
B is output.

Reference numeral 107 denotes a memory which stores parallel data S
106, and has a capacity equal to or larger than the number of pixels for one line. The data width for writing and reading is 8 bits. However, it is output only when 8 bits of the digital input signal S102 are converted into the parallel signal S106. That is,
Data of less than the last 8 bits is not written.

Since the memory 107 writes and reads data in 8-bit units, the serial data S10
2 compared to the case of writing / reading to FIFO etc.
In order to operate at a 1/8 write / read speed, the clock frequency can be reduced to 1/8, and power consumption can be reduced.

Reference numeral 108 denotes a parallel-to-serial conversion unit which converts the parallel data S107 output from the memory 107 into serial data S108 and outputs the data. Of the digital input signal S102, the one converted into parallel every eight bits and stored in the memory 107 has a valid signal S1
When 04 becomes valid, the parallel data S107 is read.

Reference numeral 109 denotes a selector, which is the serial data S108 converted by the parallel-serial converter 108 and the serial data S111 output from the shift register 111.
Is selected by the control signal S110b and output. Memory 10
7 to output the data stored in the control signal S11.
0b is set to low level, and data of less than the last 8 bits of the digital input signal S102 which is not written to the memory 107 is stored in the shift register 111 and the control signal S11
When 0b is at the high level, it outputs to S109.

Reference numeral 110 denotes a control unit, and a valid signal S10
3. The selector 109 and the shift register 111 are controlled based on the valid signal S104. The control signal S110a is a control signal for the shift register 111, and the valid signal S10
When 3 is at the high level, the control signal S110a is set to the high level to shift the data. When the number of data in the last cycle is less than a multiple of 8, the switching is performed until the end of the last cycle, that is, every multiple of 8. Also, when the data of the shift register 111 is output,
To a high level to shift data. Conversely, when it goes low, data is held. Control signal S110b
Is an output signal selection signal of the selector 111. When the signal goes high, the output signal S111 of the shift register 111 is selected.
09 is output.

Reference numeral 111 denotes a 1-bit, 7-word shift register for storing data of the digital input signal S102 in the last cycle of less than 8 bits. When the control signal 110a is at a high level, the data is shifted, and when it is at a low level, the data is held.

The operation of the line memory device configured as described above will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. Less than,
The description will be given in chronological order.

In the cycle from time T0 to time T1, conversion of serial data S102 into parallel data S106 is started. The valid signal S103 is asserted to a high level.

In a plurality of cycles from time T1 to time T3, the data of the cycle leaving the last two cycles is parallel-converted, and as a result is output as serial data S108. The description of the operation of this cycle is omitted.

In a plurality of cycles from time T2 to time T3, the serial data S108 of the parallel data S107
Is started, and the data of the cycle leaving the last four cycles is serially converted. The valid signal S104 is asserted to a high level.

In the cycle from time T3 to time T4, 8-bit serial data A102, which is the second last cycle, is input.

In the cycle from time T4 to time T5, the last 3-bit data B102 is input. At time T5, the last bit of the digital input signal S102 ends, and the valid signal S103 goes low. Also, data A1
02 is parallel-converted and stored in the memory 107 as data A106.

In the cycle from time T4 to time T6, data B102 is output from serial / parallel conversion section 106 as corresponding parallel data B106. LS
The 5 bits of B are indeterminate data. Also, the control signal S
110a goes low at the end of the cycle in which the valid signal S103 goes low. (Multiple units of 8) In the cycle from time T6 to time T8, the second cycle from the end, the 8-bit parallel data A10
7 is output from the memory 107.

In the cycle from time T7 to time T9, the parallel data A107 is converted to the serial data A108.
Is converted to Further, the selector 109 selects the serial data A108 and outputs it as the serial data A109.

In the cycle from time T8 to time T10, the control signal S110a switches to the high level, sends a data shift signal to the shift register, and outputs the serial data B111.

In the cycle from time T9 to time T11, the selectivity of the selector 109 is switched, and the selector 1
09 selects the serial data B111 and outputs it as serial data B109.

That is, as described above, even when the number of data of the digital input signal S102 is not a multiple of the number of bits of the data to be parallel-converted, there is an effect that the data of the last cycle is not lost.

[0032]

As described above, even when the number of data of the digital input signal S101 is not a multiple of the number of bits of the data to be parallel-converted, the data of the last cycle is not lost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a line memory device according to a first embodiment of the present invention;

FIG. 2 illustrates an operation of the circuit illustrated in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 line memory device main body 101 line memory macro 102 data signal input terminal 103 write enable signal input terminal 104 read enable signal input terminal 105 data signal output terminal 106 serial / parallel converter 107 memory 108 parallel / serial converter 109 data output selector 110 Shift register control unit 111 Shift register

Claims (2)

[Claims] 1. A serial / parallel conversion means for converting first serial data into first parallel data, and converting the first parallel data when the first serial data is parallel-converted by a predetermined data amount. Memory means for storing, parallel-serial conversion means for converting data read from the memory into second serial data, FIFO means for sequentially storing the first serial data, and outputting the same as third serial data; The first
Or a selection means for selecting one of the third serial data. 2. The line memory device according to claim 1, wherein the selection means is configured to output the first serial data when a predetermined data amount is not input for a predetermined period or more.
A line memory device for selecting data of an OFO means.