JP2001157021A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor, where work for designating a different area part which is completely overlapped and included in one area, is facilitated. SOLUTION: An area designating means 917 can designate a reset position for resetting processing for reading the area signal from a bit map memory 907 at an arbitrary position in the main scanning direction in an image display area. An area signal generating means 917 has a reset position register 902 for storing the reset position and a reset means 903 for resetting the reading processing of the area signal during execution. When a system reaches the position stored in the reset position register 902 while the read processing is being executed, the position is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a digital copying machine for designating an arbitrary area in a read document image and performing image processing on the area.

[0002]

2. Description of the Related Art In recent years, digital image processing apparatuses such as digital copiers display an image read from an original on a display or the like, select a part of the displayed image using a touch panel or the like, and select a specific area. There is an image processing apparatus in which designation is performed, and various image processing is applied to only the designated area portion so that the image can be printed out. Hereinafter, a method of designating an area from a display image in the digital image processing apparatus will be described with reference to the drawings. FIG. 11 is a block diagram illustrating the overall configuration of the image processing apparatus. As shown in FIG. 11, the image processing apparatus converts a document image into R, G,
B. Scanner 101 for reading as digital data of
(Image reading unit), an image processing unit 102 that performs image processing (processing) such as painting on read image data and outputs the processed image data, and specifies a specific area where the user performs processing on the image data. Operation unit 103
(Area specifying means), a display / coordinate specifying unit 104 (image display means) for displaying read image data and a processing result, and displaying a specific area for performing the processing, and processing in the image processing unit 102. Storage unit 105 (bitmap memory) for storing image data and area data for performing processing such as processing, and a CPU 106 for controlling the entire apparatus.
A ROM 107 for storing parameters and control procedure data for controlling the entire apparatus, and an image processing unit 1
The printer 108 outputs the result processed in step S02.

Next, the operation of the image processing apparatus will be described. The document image read by the scanner 101 is displayed on the display / coordinate designation unit 104. The operator of the image processing apparatus uses the operation unit 103 to specify an area from the document image displayed on the display / coordinate specifying unit 104, and the area specifying data is stored in the storage unit 105. Document image data and area designation data stored in the storage unit 105,
Further, using the parameters and control procedure data stored in the ROM 107, the image processing unit 102 forms output image data that has been processed by the user in a specified area in the document image and is output from the printer 108. You. The CPU 106 controls the entire apparatus so that all the above processes are performed in order. FIG. 12 is a block diagram showing the internal configuration of the image processing unit 102 in FIG. 11 in more detail. Note that in FIG. 12, the inside surrounded by a broken line corresponds to the image processing unit 102 in FIG. 11, and connection parts to the scanner 101, the printer 108, and the like are shown in a simplified manner. 11 shows only a part of the memory 210 related to the image processing unit 102 in the storage unit 105 of FIG. 11, and FIG.
2 shows only a part related to the image processing unit 102 in the CPU 106.

FIG. 12 shows three inputs of R (red), G (green), and B (blue) from the scanner 101, and Y (yellow), M (magenta), C (cyan),
This shows an example of the configuration of an image processing unit when four outputs of K (black) are recorded and output on transfer paper by the printer 108. 12, the image processing unit 102 includes R,
A magnification unit 201 that performs main scanning magnification independently for each of the colors G and B, an RGB γ correction unit 202 that performs γ correction such as gray balance for each of the colors R, G, and B, and correction for blurring of the lens system, etc. , R, G, B independently, an RGB filter unit 203 for performing MTF correction (sharpening), a create unit 204 for performing image processing such as mirror, italic, shadowing, hollowing, painting, moving, and the like. , G, B, Y, M, C, and K, a color correction unit 205 that converts a data system, a CMYK filter unit 206 that performs film processing according to the MTF of the printer, and performs γ correction according to the γ characteristics of the printer CMYKγ correction unit 20
7. Perform halftone processing by dither processing or density pattern method, and change C, M, Y, K to C ', M', Y ', K' (however, the number of bits is C> C ', M>M' , Y>Y'K>
K ′), and a region signal generation unit 209 (region signal generation means) for generating a signal for switching processing for each region. The memory 210 is a memory that stores information for generating an area signal and a memory that stores binary image data for performing a closed-loop filling process. The CPU 211 is a CPU that controls each processing unit inside the image processing unit 102. Although FIG. 12 shows only the connection relationship between the CPU 211 and the area signal generator 209 for convenience, the actual CPU 211
Is also connected to other processing units in the image processing unit 102 and controls them.

The connection of each processing unit in the image processing unit 102 includes a scaling unit 201, an RGB γ correction unit 202, an RGB filter unit 203, a create unit 204, and a color correction unit 20.
5, CMYK filter unit 206, CMYKγ correction unit 20
7 and the gradation processing unit 208. The area signal generation unit 209 includes a scaling unit 201, a memory 210, a CPU
211. An area signal input from the area signal generation unit 209 to the scaling unit 201 is generated in synchronization with image data read from the scanner 101.
The CPU 211 controls the area signal generator 209 to display /
The data of the area designated by the coordinate designating unit 104 is written into the memory 210 and the area data to be sent to the scaling unit 201 is held. Image processing that is switched in each area for each area signal generated from the area signal generation unit 209 includes, for example, normal processing for the area signal “0”, mirror processing for the area signal “1”, and “2” for the area signal. Can be arbitrarily defined, such as inversion processing. The memory 210
This is a bitmap memory capable of storing area information for performing image processing in an image area of a document. Area information is
One dot of the document image has n bits of information. n
The information amount of bits is a bit numerical value that can distinguish each area when there are a plurality of designated areas in the image area of the original and the processing specified for each designated area is individually performed. The distinguishable value is 2 n (where n is the number of bits)
Is the value of The information amount of n bits is, for example, n = 3 when discriminating eight types of processing regions, and is 2 to the third power (3 bits). The eight types of processing can be represented by 0 to 7 indicated by these three bits. Further, as the number of processing areas to be distinguished increases, a larger memory capacity is required. For example, to distinguish nine types of processing areas, n
= 4 bits are required. Regarding memory capacity,
For example, if the size of the original image is A3 (297 mm × 420
mm), the density is 16 pixels / mm, and the memory capacity is about 32 Mbit × 3b in order to perform eight kinds of processing in the designated area.
It = 96 Mbit is required (297 mm × 16 pixels × 420 mm × 16 pixels × 3 bits). When adding information other than the above-described eight types of processing to the information for one dot, a larger memory capacity is required. When other information is also added, for example, when the size of the original image is A3, a memory capacity of 32 × 3 M bits or more is required. Further, in order to perform the closed loop processing of the designated area in the above configuration, the scanner 10
The image data from 1 is binarized and stored, and a closed loop contour is detected (tracked) from the binarized binary data. The memory capacity of the binary data is only required to be able to store one bit of information for one dot of the document image. Therefore, when the size of the document image is A3, 32 Mbits is a necessary memory capacity.

FIG. 13A shows an area (area 1) in which the area signal is "1", and FIG. 13B shows a description position of data designating area 1 in the bit map memory. FIG. FIG. 14A is a diagram showing a detailed description position of data designating the area 1 in FIG. 13 on the bitmap memory, and FIG. 14B is a diagram showing an area signal, and FIG. FIG. 4 is a diagram showing an area output signal. With reference to FIGS. 13 and 14, a method of generating a region signal in region signal generating section 209 will be described. The process of generating the area signal in the area signal generation unit 209 is performed by converting only the data of the edge of the area 1, for example, the data of FIG. 13B and FIG.
14 (b) and FIG. 14 (c). The image data of the document read by the scanner 101 is stored in the display / coordinate designation unit 1.
04 is displayed as a document image. When processing is performed on a specific range in the displayed document image, first, the area of the range in which the processing is performed by the display / coordinate instruction unit 104 is shown as a region 302 in FIG. As follows. Next, in order to distinguish the outside 301 and the area (inside) 302 of the designated area 302, the area signal generation unit 20
9 generates a region signal. An area signal of the area 302 different from the area signal of the area 301 is stored in the bitmap memory. As a storage method, as shown in FIG. 13B, the edge 30 in the main scanning direction in the area 302 is used.
Only 3 is written into the memory, and each area signal is generated such that the outside 301 and the inside 302 are alternately switched every time the number of edges in the main scanning direction appears. For example, when data having an area signal of “1” is stored in the bitmap memory, an edge portion (area starts in the main scanning direction) of the area like a part of the bitmap memory shown in FIG. The data of the area signal “1” is written only in the edge part and the edge part where the area ends. This FIG.
(A) is a storage dot in which each of the grids corresponds to one dot of the image area, and each grid has a data capacity capable of distinguishing each area. Although not shown in FIG. 14 (a), a blank column is data in which the area signal is "0". The data of the area stored in the bitmap memory is
At the time of processing by the image processing unit 102, the image data is sequentially read in the main scanning direction. When one line has been read, the data is shifted by one line in the sub-scanning direction and sequentially read in the main scanning direction. For example,
When the line indicated by the arrow shown in FIG. 14A is read, when the data of the area signal “1” for starting the area is read as shown in FIG. Then, when the area signal is generated from the area signal generator 209 and the data of the area signal “1” for terminating the next area is read, the generation of the area signal is ended. As a result, the area signal “0” output from the image processing unit 102,
The area output signal of "1" is as shown in FIG.

FIG. 15A shows a designated area when a plurality of areas (area 1) having an area signal of "1" are designated. FIG. 15B shows an area in the bit map memory. FIG. 8 is a diagram showing a position where data designating the. When an area to which the data of the area signal "1" is to be written is designated as shown in FIG. 15A, the data is written at the edge position of the area data as shown in FIG. 15B. In this case, the region 501 in which two regions of the same region signal “1” overlap each other is designated as outside the region in this case. FIG. 16A is a diagram showing a detailed description position of data designating region 1 in FIG. 15 on the bitmap memory, and FIG. 16B is a diagram showing a region signal, and FIG. FIG. 4 is a diagram showing an area output signal. In the bit map memory shown in FIG. 16A, the data of the area signal “1” is double-written at the position where the area starts and the position where the area ends. Codes from “0” to “7” are used as each area signal. For example, in the line indicated by the arrow in FIG. 16A, the area signal of data read from the bitmap memory is only “1”. , Signals 601 and 602 whose area signals are “1”
Are generated from the area signal generator 209 as shown in FIG. By this area signal “1”, the image processing unit 1
FIG. 16 (c) shows the area output signal output from 02.

Next, the case where a plurality of different area signals are specified with an overlap, instead of the case where a plurality of the same area signals are specified with an overlap as shown in FIG. 15, will be described.
In that case, the processing is performed according to the priority of the area signal specified in advance. FIG. 17A is a diagram showing a specified area when areas (area 1 and area 2) of different area signals “1” and “2” are specified.
FIG. 4B is a diagram showing a position where data designating an area in the bitmap memory is described. As for the priority of the area signal, the value with the larger numerical value of the area signal assigned to each area is preferentially processed. As shown in FIG. 17A, it is assumed that two different area signals, that is, area 1 and area 2 are designated to overlap each other to form an area 701.
As shown in FIG. 17B, data is written into the memory 210 at the position of the edge of each area. FIG.
FIG. 18A is a diagram showing a detailed description position of data designating the area 1 and the area 2 in FIG. 17 on the bitmap memory, and FIGS. 18B and 18C are views showing an area signal; FIG. 18D is a diagram showing the area output signal. FIG.
The area designated as in FIG. 7B is stored in the bitmap memory as shown in FIG. FIG.
As shown in FIGS. 18 (b) and 18 (c), the data of the area 1 and the area 2 in the line indicated by the arrow in (a) are signals 801 (area signal "1") and 802 (area signal "2" )). In the example of FIG. 17 and FIG. 18, since the area signal assigned to each area gives priority to a large value,
An area output signal as shown in FIG. That is, the signal 801 in FIG. 18B and the signal 8 in FIG.
The area output signal in the signal 803 of the overlapping portion of 02, that is, the area output signal when the area 1 and the area 2 are simultaneously output, is obtained by priority processing in which the area 2 having a larger numerical value of the area signal than the area 1 has priority. , The output signal of the area 2 is output. By specifying an area using the touch panel or the like as described above, the digital image processing apparatus can perform necessary processing only on a portion of the display that requires image processing. Therefore, as in the case where the partial processing is performed by an analog image processing apparatus, it is possible to eliminate the trouble of printing and outputting the image once read from the document as it is, cutting and pasting the output result, and copying again.

[0009]

However, for example, in the case where the second area is designated so that any of the first areas completely overlap and enter the inside,
In the case where only the first area is designated and output and the image processing is performed inside, in the conventional digital image processing apparatus in which the area signal takes priority, the output of the second area is the first area. Since it takes precedence over the output of the area, it is not possible to specify and output only the first area, and therefore, it is not possible to perform image processing inside only the first area. It was necessary to specify the first area. Further, for example, when it is desired to specify only the first area and output repeatedly, or when only the first area is specified and output it to an arbitrary position, all of the first area is manually set. It was necessary to repeatedly specify the area or to specify the first area at an arbitrary position. Also, as described above, it is difficult for a normal operator to manually specify only the first area included in the second area because it is an elaborate operation. If the specified area overlaps with the donut part and it is necessary to perform another process on the inner area, it is necessary to match all directions (up, down, left, and right) at once, and it is difficult to specify the area. . SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and facilitates the operation of designating another area part completely overlapping one area, and making the overlapping part easier. It is an object of the present invention to provide an image processing apparatus capable of easily performing a process to be performed.

[0010]

According to a first aspect of the present invention, there is provided an image processing apparatus, comprising: an image reading unit for outputting image data obtained by reading an image on a document; Image display means for displaying an image based on image data; area designation means for designating a designated area for performing image processing from the image display area of the image display means; and an image other than the designated area and the designated area Area signal generating means for generating an area signal corresponding to each of the display areas; and an area signal corresponding to the designated area in a storage area having a storage area corresponding to the image display area and corresponding to the designated area. And a bitmap memory for storing the bitmap memory, wherein the area designating means stores the bitmap memory at an arbitrary position in the main scanning direction within an image display area. It is possible to specify a reset position for resetting the read processing region signal in Li,
The area signal generating means includes a reset position register for storing the reset position, and reset means for resetting the read processing of the area signal, and the read processing is performed at the position stored in the reset position register during the read processing. The reading process is reset when it has reached. According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, when the area signal generating means reads an area signal from the bitmap memory, the area signal generating means can repeatedly execute the processing of resetting the read processing. Features. According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, the area signal generating means only performs an area signal of an area at a position designated by the reset position register during the read processing. Reset processing can be performed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. A first embodiment of the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.
FIG. 1 shows that the area signals are “1”, “2”, “3”, and
Regions that are "4" (region 1, region 2, region 3, region 4)
FIG. 2 is a block diagram showing a circuit for performing arithmetic processing according to the first embodiment. FIG. 3 is a block diagram showing a circuit for performing arithmetic processing according to the first embodiment. FIG. 4 is a diagram showing each signal subjected to the arithmetic processing, and FIG. 4 is a diagram showing an area where the area designated in FIG. 1 is arithmetically processed by the circuit in FIG. 2 and output. In the present embodiment, as shown in FIG. 1, different regions 1, 2, and 3 are designated so as not to have an overlapping portion, and region 4 is designated so as to include all regions 1, 2, and 3. Is done. Line 100 at the arrow
The data of region 1, region 2, region 3, and region 4 on 5 are output as shown in regions 1, 2, 3, and 4, respectively, of FIG. In FIG. 1, the area 1 is defined as an area 1001, and the area 2 is defined as an area 1010.
02, a portion of the region 3 is referred to as a region portion 1003, and a portion of the region 4 including all of the regions 1 to 3 is referred to as a region portion 1004. According to the conventional method in which the numerical value of the region signal is output in accordance with the priority order in which the larger value is given, when the region portions 1001 to 1003 and the region portion 1004 shown in FIG. Since the priority is output, for the area portions 1001 to 1003,
Could not output. Therefore, when image processing is to be performed on the region portion 1001, the region portion 1002, or the region portion 1003, the region portion is newly designated separately in the conventional method. Therefore, in this embodiment,
The arithmetic circuit 9 shown in FIG.
An arbitrary area in the areas 1 to 3 can be designated by the circuit to which 17 is added.

The arithmetic circuit shown in FIG. 2 counts up by a clock input in order to obtain a reset generation timing, and a counter 901 whose count value is cleared by input of a line synchronization signal lsync, and a value of a timing for resetting an area signal. Is set in the reset register 90
2 is compared with the count value of the counter 901 and the value set in the reset register 902, and the reset signal 911
And a reset signal 911 that counts up upon generation of the reset signal.
Counter 904, which counts the number of occurrences of, and the count value is cleared by input of a line synchronization signal lsync, a read start address register 905 in which a read start address 915 for reading area data is set, and a reset counter 904 A selector 906 for selecting an input from the plurality of read start address registers 905 based on the count value of the register 905, a bit map memory 907 for storing area data and outputting data 913,
Read control circuit 908 for reading data 913 from bitmap memory 907 and outputting it as 3-bit data
And a decoding circuit 909 for converting the data stored in the bitmap memory 907 as a region signal into a signal for each number of each region shown in regions 1 to 7 in FIG. And a priority circuit 910 for selecting an area signal in accordance with a preset priority and outputting the selected signal in three bits. In the present embodiment, the data stored in the memory is 3-bit data, and the 3-bit data is decoded and output as an area signal from “0” to “7”. The area signals “1” to “7” output from the decode circuit 909 are directly treated as values “1” to “7” in the subsequent circuit.
A circuit including blocks from the reset register 902 to the priority order circuit 910 is a code conversion circuit 916 that converts data (code) stored in the bitmap memory 907 into a 3-bit signal and outputs the signal. Therefore, in that case, the arithmetic circuit 917 is composed of the counter 901 and the code conversion circuit 916.

The operation when the reset position is set to the position indicated by the arrow 1006 in FIG. 1 is as follows.
When the reset position is set at the position of arrow 1006 in FIG. 1, a reset signal is generated at the timing of arrow 1102 in FIG. When the reset position is set at the position of the arrow 1006 in FIG. 1, the value of the timing during scanning in the main scanning direction indicating the reset position is set in the reset register 902. The counter 901 whose count value has been cleared by the input of the line synchronization signal lsync starts counting up by the clock input. The reset signal generation circuit 903 compares the value of the counter 901 with the value set in the reset register 902, and outputs a reset signal (pulse signal) when the comparison result matches. The reset signal 911 output from the reset signal generation circuit 903 is counted by the reset counter 904 whose count value has been cleared by the input of the line synchronization signal lsync. The counter value of the reset counter 904 is input to the selector 906. The count value of the reset counter 904 at the reset position 1006 is input to the read start address register 905 in advance together with the read start address data. The input count value enables input of a plurality of count values, that is, count values corresponding to a plurality of reset positions. Also,
In this embodiment, the read start address data is stored in the bit map memory 90 corresponding to the reset position 1006.
The address in 7 is the read start address. The read start address data of the read start address register 905 selected by the selector 906 based on the count value of the reset counter 904 is output to the read control circuit 90.
8 is input.

The read control circuit 908 receives the reset signal 911 from the reset signal generation circuit 903, the read start address data from the selector 906, and the line synchronization signal lsync, and receives the line synchronization signal lsync.
Reading is started from address 0 of the bit map memory 907 by c. When the reset signal 911 is Hi, the read control circuit 908 generates an initial value of the read address 912 in the bitmap memory 907 from the read start address 915, and
And a control signal 914 of the bitmap memory 907 to the bitmap memory 907,
The data 913 is read from 07. Read control circuit 9
The data 913 read by 08 is input to the decoding circuit 909, converted into a region signal, and output to the priority order circuit 910. The priority order is selected by the priority order circuit 910 according to the magnitude of the numerical value assigned to each area signal output from the decode circuit 909, and the selected area signal is output from the priority order circuit 910. When the configuration and operation are performed as described above, the priority order circuit 91
The signal output from 0 is like output 1101 in FIG. Further, the area obtained by the signal of the output 1101 is as shown in FIG. 4, and after the reset position 1006, the area 2 (1202) and the area 3 (1203) are output. It is possible to specify and specify a process (image processing) different from the surroundings.

Next, a second embodiment capable of repeatedly executing the reset processing of the first embodiment will be described with reference to FIGS. 5 and 6. FIG. FIG. 5A is a diagram showing each area in a case where the areas (area 1, area 2, and area 3) in which the area signals are “1,” “2,” and “3” are specified by the operator. FIG. 5B and FIG. 5C are diagrams showing an area where the area specified in FIG. 5A is processed and output by the circuit of FIG. 6 described later, and FIG.
FIG. 4 is a block diagram illustrating a circuit that performs the arithmetic processing according to the embodiment. In the present embodiment, as shown in FIG. 5A, different areas 1, 2, and 3 are designated so as not to overlap. Also, the reset positions 1402 and 1403 are specified, and the images within the area width 1401 from the left end of the image area to the reset position 1402 are reset.
03 is repeated. In FIG. 5A, a region 1 portion is a region portion 1411, a region 2 portion is a region portion 1412, and a region 3 portion is a region portion 1413. The arithmetic circuit in FIG. 6 includes a register 1301 for storing a timing value corresponding to an area width 1401 for performing repetition processing in an image area, a clock input for obtaining a timing for performing repetition processing, and a line synchronization signal lsync. A counter 1302 reset by an input and an area width 1 stored in a register 1301
A repetition timing signal generation circuit 1303 that compares the timing value corresponding to 401 with the count value of the counter 1302 and outputs a repetition processing timing signal, and calculates an OR logic between the input of the line synchronization signal lsync and the repetition processing timing signal input An OR logic circuit 1304 that outputs the result to the counter 901 and the counter 90 shown in FIG.
1 and the same code conversion circuit 916 as the counter 901 and the code conversion circuit 916.

Next, the operation when the area specified as shown in FIG. 5A is repeatedly processed and output as shown in FIG. 5B will be described. First, FIG.
When the reset position is set at the positions of arrows 1402 and 1403 in FIG. 2A, the value of the timing during scanning in the main scanning direction indicating the reset position is set in the reset register 902 in FIG.
In 05, the count value of the reset counter 904 at the reset positions 1402 and 1403 is input together with the read start address data. In the read start address data in the case of the present embodiment, the address in the bitmap memory 907 corresponding to the left end of the image area is the read start address. Further, the timing value corresponding to the area width 1401 of the range in which the repetitive processing is performed is stored in the register 13.
Set to 01. The counter 1302 counts the clock input after being reset by the input of the line synchronization signal lsync, and outputs a count value. The repetition timing signal generation circuit 1303 stores the timing value corresponding to the area width 1401 stored in the register 1301 and the counter 1
If the count values of 302 are compared and they match, a timing signal (pulse signal) for the repetition processing is output. The OR logic circuit 1304 calculates the OR logic of the input of the line synchronization signal lsync and the timing signal input of the repetition processing, and outputs the calculation result to the counter 901. Counter 901
Subsequent operations are the same as in the first embodiment, and a description thereof will be omitted. In this manner, the counter 901 can be reset at a timing corresponding to the area width 1401. Therefore, the area specified as shown in FIG. 5A can be repeatedly processed and output as shown in FIG. 5B.

Next, a description will be given of the operation in the case where the designated area as shown in FIG. 5A is repeatedly processed and output as shown in FIG. 5C. In FIG. 5B, the same graphic is output after each reset processing repeated a plurality of times, but in FIG. 5C, a different graphic is output after each reset processing repeated a plurality of times. In the case of output as shown in FIG.
The operation is the same as the case where the designated area is repeatedly processed and output as shown in FIG. 5B, as shown in FIG. 5B. The read start address data input to the read start address register 905 of the
This is data read from an address in the bit map memory 907 corresponding to 403. That is, the read start address after the reset is set to the reset position 1402, 1
FIG. 5 (b)
As shown in FIG. 5, the same area data output after the repeated reset processing can be output as different area data after the repeated reset processing as shown in FIG. In this manner, in the present embodiment, it is possible to repeatedly specify and output only one area included in another area specified in the image area, and to further output one area in the original image area. The area can be output to a position different from the position.

Next, similarly to the first embodiment, FIG. 7 shows another embodiment which is capable of obtaining an output as shown in FIG. 4 from a designated area as shown in FIG. , FIG. 8, FIG. 9, and FIG. FIG.
FIG. 9 is a block diagram illustrating a circuit that performs arithmetic processing according to a third embodiment. In the arithmetic circuit of FIG. 7, a counter 1501 is counted up by a clock input in order to obtain a reset generation timing, and a count value is cleared by an input of a line synchronization signal lsync, and a value of a timing for resetting a region signal is set. Reset register 1
502, a reset signal generation circuit 1503 for comparing the count value of the counter 1501 with the value set in the reset register 1502 and outputting a reset signal, and a bit for storing area data and outputting data 1511 via a data bus A read control circuit 1505 that reads out the data 1511 from the map memory 1504 and the bit map memory 1504 and outputs the data 1511 as 3-bit data, and the data stored in the bit map memory 1504 as area signals shown in the areas 1 to 7 in FIG. A decoding circuit 1506 for converting the signal into a signal for each region number, a priority circuit 1507 for selecting, from the region signal converted by the decoding circuit 1506, a region portion where a plurality of region signals overlap, and outputting 3-bit data; It is composed of In the present embodiment, similarly to the first embodiment, the data stored in the memory is 3-bit data, and the 3-bit data is decoded as an area signal from “0” to “7”. Output. The area signals “1” to “7” output from the decode circuit 1506 are treated as they are in the subsequent circuits as values “1” to “7”.

FIG. 8 is a block diagram showing a part of the decoding circuit 1506 of FIG. 7 in further detail. 8 are provided in accordance with the number of area numbers set in the decoding circuit 1506 in FIG. Further, the arithmetic circuit of FIG.
OR of 602 input and input of line sync signal lsync
An OR circuit 1603 for calculating the logic and a line synchronization signal l
First, one output terminal 1607 is input by the input of sync.
1604 that outputs "0" from the other terminal and outputs "1" from the other output terminal 1608, and a selector 1609 that selects and outputs one of the output from the output terminal 1607 and the output from the output terminal 1608. It is composed of The clock 1601 and the output of the selector 1609 are input to the flip-flop 1604. The selector 1609 includes a bitmap memory 150.
The data signal 1706 for each area number from 4 is input. The operation when the reset position is set to the position of arrow 1006 in FIG. 1 is as follows. When the reset position is set to the position of arrow 1006 in FIG. 1, a reset signal is generated at the timing of arrow 1801 in FIG. When the reset position is set at the position of the arrow 1006 in FIG. 1, the value of the timing during scanning in the main scanning direction indicating the reset position is set in the reset register 1502. The counter 1501 whose count value has been cleared by the input of the line synchronization signal lsync starts counting up by the clock input. The reset signal generation circuit 1503 compares the value of the counter 1501 with the value set in the reset register 1502, and outputs a reset signal (pulse signal) when the comparison result matches.
The reset signal 1602 output from the reset signal generation circuit 1503 is input to the decode circuit 1506.
The read control circuit 1505 stores the bit map memory 15
The read address 1510 and the control signal 1512 of the bitmap memory 1504 are output to the bitmap memory 1504, and the data 1511 is read from the bitmap memory 1504. Data 1511 read by the read control circuit 1505 is input to the decode circuit 1506. In the case of the present embodiment, the data 1511 for all area numbers is the decode circuit 1506.
Is input to

In the decoding circuit 1506, data 1511 is input to each arithmetic circuit shown in FIG. 8 for each area number, and an area signal for each area number is output from the priority order circuit 1507. The priority order circuit 1507 selects a high-priority region signal based on a numerical value assigned to each of the region signals output from the decode circuit 1506, and outputs the selected region signal from the priority order circuit 1507. When the reset signal 1602 is Hi, the decode circuit 1506 is input to the decode circuit 1506, converted into a region signal, and output to the priority order circuit 1507. The priority order of each area signal output from the decode circuit 1506 is selected by the priority order circuit 1507, and the selected area signal is output from the priority order circuit 1507.
When configured and operated as described above, the signal output from the priority order circuit 1507 is output from the output 180 of FIG.
It looks like 2. FIG. 10 shows a decoding circuit 15 in the case where the reset according to the present embodiment is performed at the timing of arrow 1801 in FIG.
FIG. 16 is a diagram showing an output of each area 06 and an output 1802 from the priority order circuit 1507. FIG. 9 for comparison with FIG.
Is a decoding circuit 1506 when the reset is not performed according to the present embodiment on the area specified as shown in FIG.
Of each region and the output 17 from the priority order circuit 1507
FIG. In the case of FIG. 9, only the area 4 is output as shown in the output 1701. Therefore, output 1
The area obtained by the signal 802 is as shown in FIG. 4 similarly to the first embodiment, and the reset position 100
After area 6, area 2 (1202) and area 3 (1203)
Since only these regions are shown, these regions 1202, 1203
Can be specified, and a process (image processing) different from the surroundings can be specified. Thus, also in the present embodiment,
As in the first embodiment, since the area 2 (1202) and the area 3 (1203) are output after the reset position 1006, these areas 1202 and 1203 are designated and processed differently from the surroundings (image processing). Can be specified.

[0021]

As described above, according to the first and third aspects of the present invention, it is possible to output a region signal of another region which is completely overlapped inside one region. The task of designating another area portion can be facilitated, and image processing to be performed on the other area portion can be easily designated. According to the second aspect of the present invention, it is possible to repeatedly specify and output only one area included in another area specified in the image area, and to further output the position of one area in the original image area. The area can be output to a position different from the above.

[Brief description of the drawings]

FIG. 1 shows that the area signal is “1”, “2”, “3”, and
Regions that are "4" (region 1, region 2, region 3, region 4)
FIG. 7 is a diagram showing an area when is designated by an operator.

FIG. 2 is a block diagram illustrating a circuit that performs arithmetic processing according to the first embodiment.

FIG. 3 is a diagram illustrating each area signal and each signal that has been subjected to arithmetic processing in each unit in FIG. 2;

FIG. 4 is a diagram showing a region output by performing arithmetic processing on the region designated in FIG. 1 by the circuit in FIG. 2;

FIG. 5 (a) shows that the area signal is “1”, “2”, and
FIG. 9 is a diagram illustrating an area (area 1, area 2, area 3) that is “3” when the operator specifies the area;
(B) and (c) are the figures which showed the area which computed and processed the area designated in (a), and were outputted.

FIG. 6 is a block diagram illustrating a circuit that performs arithmetic processing according to a second embodiment.

FIG. 7 is a block diagram of a circuit that performs arithmetic processing according to a third embodiment.

8 is a block diagram showing a part of the decoding circuit 1506 of FIG. 7 in further detail.

FIG. 9 is a diagram illustrating an output for each area of the decoding circuit and an output from the priority order circuit when the reset according to the present embodiment is not performed on the area specified as in FIG. 1; .

10 shows an output of each area of the decoding circuit and an output from the priority order circuit when a reset according to the present embodiment is performed at a timing indicated by an arrow in FIG. 10 for an area designated as in FIG. FIG.

FIG. 11 is a block diagram illustrating an overall configuration of the image processing apparatus.

FIG. 12 illustrates an example of a configuration of an image processing unit in a case where three inputs of RGB are input and four outputs of YMCK are output.

13A is a diagram illustrating a region (region 1) in which a region signal is “1”, and FIG. 13B is a diagram illustrating a description position of data designating region 1 in a bitmap memory;

FIG. 14 (a) is a diagram showing a state in FIG.
5 is a diagram showing a detailed description position of data designating region 1 of No. 5, (b) is a diagram showing a region signal, and (c) is a diagram showing a region output signal.

FIG. 15A is a diagram showing a designated region when a plurality of regions (region 1) whose region signal is “1” are designated;
(B) is a diagram showing a position where data specifying an area is described in the bitmap memory.

FIG. 16 (a) is a diagram showing a state in FIG.
7 is a diagram showing a detailed description position of data designating region 1 of No. 7, (b) is a diagram showing a region signal, and (c) is a diagram showing a region output signal.

FIG. 17A is a diagram showing a specified area when different area signals “1” and “2” (areas 1 and 2) are specified, and FIG. 17B is a diagram showing a bit map memory; FIG. 8 is a diagram showing a position where data designating an area in FIG.

FIG. 18 (a) is a diagram showing FIG. 1 on a bit map memory.
9 is a diagram showing detailed description positions of data designating region 1 and region 2 of FIG. 9, (b) and (c) are diagrams showing region signals, and (d) is a diagram showing region output signals. .

[Explanation of symbols]

101: scanner, 102: image processing unit,
103: operation unit, 104: display / coordinate instruction unit,
105: storage unit, 106: CPU, 107 ...
ROM, 108, printer, 201, magnification unit, 202, RGB gamma correction unit, 203, RGB
Filter part, 204 ... Create part, 205 ...
Color correction unit, 206 ... CMYK filter unit, 207
..CMYK.gamma. Correction section, 208 ... gradation processing section, 20
9 area signal generator, 210 memory, 211
... CPU, 901, 904, 1302, 1501
.. Counter, 902, 1502 reset register, 903, 1303, 1503 reset signal generation circuit, 905 address register, 906, 16
09 selector, 907, 1504 bitmap memory, 908, 1505 read control circuit, 909, 1506 decode circuit, 910, 1
507: priority circuit, 916: code conversion circuit, 917: arithmetic circuit, 1307, 1603 ...
OR logic circuit, 1303... Repetition timing signal generation circuit

Claims (3)

[Claims] An image reading unit that outputs image data obtained by reading an image on a document; an image display unit that displays an image based on the image data; and an image display unit that outputs an image based on the image data. Area specifying means for specifying a specified area for performing image processing; area signal generating means for generating an area signal corresponding to each of the specified area and an image display area other than the specified area; A bitmap memory that has a storage area to be stored and stores an area signal corresponding to the specified area in a storage area corresponding to the specified area. It is possible to specify a reset position for resetting the read processing of the area signal in the bit map memory at an arbitrary position in the main scanning direction within the above. Wherein the area signal generating means includes a reset position register for storing the reset position, and reset means for resetting a read processing of the area signal, and the area signal generating means is provided at a position stored in the reset position register during the read processing. An image processing apparatus, wherein when the read processing arrives, the read processing is reset. 2. The image processing apparatus according to claim 1, wherein the area signal generating means can repeatedly execute a process of resetting the read processing when reading the area signal from the bitmap memory. 3. The image according to claim 1, wherein the area signal generating means can perform a reset process on only an area signal of an area at a position designated by the reset position register during the read processing. Processing equipment.