JP2001156333A - AlGaInP LIGHT EMITTING DIODE - Google Patents

AlGaInP LIGHT EMITTING DIODE

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Publication number
JP2001156333A
JP2001156333A JP33907099A JP33907099A JP2001156333A JP 2001156333 A JP2001156333 A JP 2001156333A JP 33907099 A JP33907099 A JP 33907099A JP 33907099 A JP33907099 A JP 33907099A JP 2001156333 A JP2001156333 A JP 2001156333A
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
iii
light emitting
pedestal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33907099A
Other languages
Japanese (ja)
Other versions
JP4050435B2 (en
Inventor
Ryoichi Takeuchi
良一 竹内
Wataru Nabekura
亙 鍋倉
Takashi Udagawa
隆 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
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Publication date
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Priority to JP33907099A priority Critical patent/JP4050435B2/en
Publication of JP2001156333A publication Critical patent/JP2001156333A/en
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Publication of JP4050435B2 publication Critical patent/JP4050435B2/en
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Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a high-luminance AlGaInP LED which has a window layer and the light emitting area of which is expanded by preferentially and uniformly diffusing an operating current in an open light emitting area, by suppressing the leakage of the operating current to the area immediately below a pedestal electrode. SOLUTION: A III-V compound semiconductor junction layer which forms a p-n junction is provided in the area immediately below the pedestal electrode and ohmic electrodes are dispersedly arranged in the open light emitting area.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、(AlMGa1-M
NIn1-NP(0≦M≦1、0<N<1)(以後、AlG
aInPと略す)層を発光部に有する発光ダイオード
(AlGaInP系LED)に関し、さらに詳しくは、
駆動電流を発光領域に優先的に流通できる構成を備えた
高輝度のAlGaInP系可視発光ダイオードを得るた
めの技術に関する。
[0001] The present invention relates to (Al M Ga 1-M )
N In 1- NP (0 ≦ M ≦ 1, 0 <N <1) (hereinafter referred to as AlG
a light emitting diode (AlGaInP-based LED) having a light emitting portion in its light emitting portion.
The present invention relates to a technique for obtaining a high-brightness AlGaInP-based visible light emitting diode having a configuration in which a drive current can be preferentially passed through a light emitting region.

【0002】[0002]

【従来の技術】高輝度のAlGaInP系LEDを得る
従来手段の一つとして、(AlXGa1 -X0.5In0.5
からなるpn接合型ダブルヘテロ(DH)構造の発光部
の上方に酸化インジウム・錫(英略称:ITO)などの
導電性透明酸化物材料からなる窓層を設ける手段が知ら
れている(特開平11−4020号公報明細書参照)。
しかし、特開平11−4020号公報に記載される発明
では、結線(ボンディング)用台座電極が敷設されたI
TO透明電極層とAlGaInP系LED構成層との間
に亜鉛(元素記号:Zn)等の金属薄膜が具備されてい
る。この従来技術では、Zn等の金属膜がITO電極層
とIII−V族化合物半導体構成層との密着性を増強す
る目的で、発光部表面の略全面に一様に万遍なく配置さ
れる構成となっている。従って、ITO透明電極層の直
下に配置された金属膜に発光層からの発光が金属材料膜
に容赦なく吸収されてしまうため、高輝度のAlGaI
nP系LEDを得るのに妨げとなっている。
2. Description of the Related Art As one of conventional means for obtaining a high-brightness AlGaInP-based LED, (Al X Ga 1 -X ) 0.5 In 0.5 P
Means for providing a window layer made of a conductive transparent oxide material such as indium oxide / tin (ITO) in the upper part of a light emitting portion having a pn junction type double hetero (DH) structure made of No. 11-4020).
However, according to the invention described in Japanese Patent Application Laid-Open No. H11-4020, the I-type pedestal electrode for connection (bonding) is laid.
A metal thin film such as zinc (element symbol: Zn) is provided between the TO transparent electrode layer and the AlGaInP-based LED constituent layer. In this prior art, a metal film of Zn or the like is arranged evenly and almost over the entire surface of the light emitting portion in order to enhance the adhesion between the ITO electrode layer and the III-V compound semiconductor constituent layer. It has become. Accordingly, since the light emitted from the light emitting layer is relentlessly absorbed by the metal film disposed on the metal film disposed immediately below the ITO transparent electrode layer, the high brightness AlGaI
This is an obstacle to obtaining nP-based LEDs.

【0003】電極層または窓層を構成するITO等の酸
化物層とLEDを構成する(AlXGa1-X0.5In0.5
P等のIII−V族化合物半導体層とを直接、接合させ
たのみでは比較的に高い接合障壁が形成され、よって、
徒に高い順方向電圧(所謂、Vf)が帰結されることも
知られている。窒化ガリウム・インジウム(組成式Ga
ZIn1-ZN:0≦Z≦1)系LEDに関する最近の研究
報告に依れば、III族窒化物半導体層とITO窓層と
の接合構成を具備したLEDのVfは一般なVf値の約
2倍の7ボルト(単位:V)を越えるものとなると報告
されている(Appl.Phys.Lett.,74
(26)(1999)、3930〜3932頁参照)。
また、この接合障壁の形成に依り、駆動電流の発光領域
への広範な拡散が果たせず、従って、高輝度のAlGa
InP系LEDを得るのに支障を来している。
[0003] (Al x Ga 1 -x ) 0.5 In 0.5 constituting an LED with an oxide layer such as ITO constituting an electrode layer or a window layer
Only by directly joining a III-V group compound semiconductor layer such as P directly forms a relatively high junction barrier,
It is also known that a high forward voltage (so-called Vf) is unnecessarily obtained. Gallium indium nitride (composition formula Ga
Z In 1-Z N: 0 ≦ Z ≦ 1) According to recent research reports on system LED, the LED of Vf provided with the junction structure of the group III nitride semiconductor layer and the ITO window layer generally a Vf value (Appl. Phys. Lett., 74).
(26) (1999), p. 3930-3932).
In addition, due to the formation of the junction barrier, the drive current cannot be diffused widely into the light emitting region, and therefore, the high brightness AlGa
There is a problem in obtaining InP-based LEDs.

【0004】従来では、ITO等の透明酸化物層とLE
Dを構成するIII−V族化合物半導体構成層との間に
コンタクト(contact)層を配置して、酸化物層
とIII−V族化合物半導体構成層との間のオーミック
(Ohmic)接触性を向上させる技術が開示されてい
る(特開平11−17220号公報明細書参照)。特開
平11−17220号公報に開示される従来例では、コ
ンタクト層はGaAs、砒化リン化ガリウム(組成式:
GaAs1-ZZ:0≦Z≦1)等から構成されるものと
なっている。しかし、従来では、(AlXGa1-X0.5
In0.5P(0≦X≦1)発光層からの発光波長に対応
するよりも禁止帯幅を小とするコンタクト層が発光領域
の表面を被覆して敷設されている(上記の特開平11−
17220号公報参照)。この構成ではコンタクト層に
因り発光が吸収され、高輝度のIII−V族化合物半導
体LEDを得るのに支障となっている。
Conventionally, a transparent oxide layer such as ITO has been
A contact layer is arranged between the III-V compound semiconductor constituent layer constituting D and the ohmic contact between the oxide layer and the III-V compound semiconductor constituent layer is improved. A technique for causing such a phenomenon is disclosed (see Japanese Patent Application Laid-Open No. H11-17220). In the conventional example disclosed in Japanese Patent Application Laid-Open No. 11-17220, GaAs and gallium arsenide phosphide (composition formula:
GaAs 1-Z P Z : 0 ≦ Z ≦ 1) and the like. However, conventionally, (Al X Ga 1 -X ) 0.5
A contact layer having a smaller forbidden band width than that corresponding to the emission wavelength from the In 0.5 P (0 ≦ X ≦ 1) light emitting layer is laid to cover the surface of the light emitting region (see Japanese Patent Application Laid-Open No.
No. 17220). In this configuration, light emission is absorbed by the contact layer, which hinders obtaining a high-luminance III-V compound semiconductor LED.

【0005】[0005]

【発明が解決しようとする課題】透明酸化物層を窓層等
として備えた従来のAlGaInP系LEDにあって、
透明酸化物層の上表面に設けた台座電極の直下の領域で
は、一応は比較的高い接合障壁を形成するITOとLE
DをなすIII−V族化合物半導体構成層とを直接、接
合させる構成としている(特開平11−17220号公
報明細書参照)。ところが、高い障壁と云えどもVfを
2倍程度に増加させるに過ぎない。このため、台座電極
の直下の、台座電極の射影領域への動作電流の流入を充
分に阻止できない。台座電極の直下の領域(台座電極の
射影領域)での発光は台座電極に遮蔽されるため、効率
的に外部へ取り出せない。即ち、台座電極の直下の領域
に流入した動作電流は外部への発光取り出し効率に然し
たる向上を来すことなく、浪費されることとなる。
In a conventional AlGaInP-based LED having a transparent oxide layer as a window layer or the like,
In a region immediately below the pedestal electrode provided on the upper surface of the transparent oxide layer, ITO and LE which form a relatively high junction barrier are used.
The structure is such that the D-group III-V compound semiconductor constituent layer is directly joined (see JP-A-11-17220). However, even though it is a high barrier, it only increases Vf about twice. Therefore, it is not possible to sufficiently prevent the operation current from flowing into the projection area of the pedestal electrode immediately below the pedestal electrode. Light emission in a region immediately below the pedestal electrode (projection region of the pedestal electrode) is shielded by the pedestal electrode, and thus cannot be efficiently extracted to the outside. That is, the operating current flowing into the region immediately below the pedestal electrode is wasted without improving the efficiency of extracting light to the outside.

【0006】高輝度化を果たすには、台座電極の直下領
域への動作電流の浪費を回避して、透明窓層を介して外
部に発光を取り出すことができる台座電極の射影領域外
(所謂、開放発光領域)に優先的に分散できる構成が求
められる。また、開放発光領域に優先的に動作電流を流
通できる構成とした上で、更に、従来の如く発光を吸収
する薄膜層を開放発光領域の全域に設ける構成を必要と
せずに、発光を徒に遮蔽することなく優先的に供給され
る動作電流を拡散させる手段を講ずる必要がある。
In order to achieve high brightness, it is possible to avoid wasting operating current to a region immediately below the pedestal electrode and to take out light emission to the outside through the transparent window layer (so-called “outside projection region”). A configuration that can be preferentially dispersed in an open light emitting region) is required. In addition, the configuration allows the operating current to flow preferentially to the open light emitting region, and furthermore, it is not necessary to provide a thin film layer that absorbs light emission as in the related art over the entire open light emitting region. It is necessary to take measures to spread the preferentially supplied operating current without shielding.

【0007】本発明は、上記の従来技術に於ける問題点
を解決して高輝度のAlGaInP系LEDを提供する
ことを目的に成されたものであって、特に、発光の遮蔽
領域への動作電流の漏洩を充分に阻止できる構成と、発
光層からの発光を遮蔽する度合いが小さく、且つ、発光
領域に広範に動作電流を拡散できるオーミック電極の構
成とを備えた高輝度のAlGaInP系LEDを提供す
ることを趣旨としている。
An object of the present invention is to provide a high-luminance AlGaInP-based LED by solving the above-mentioned problems in the prior art. A high-brightness AlGaInP-based LED having a configuration that can sufficiently prevent current leakage and a configuration of an ohmic electrode that has a small degree of blocking light emission from the light-emitting layer and that can widely diffuse an operation current into a light-emitting region. It is intended to provide.

【0008】[0008]

【課題を解決するための手段】本発明者らは上記課題を
解決すべく鋭意努力検討した結果本発明に到達した。即
ち本発明は、[1]III−V族化合物半導体構成層、
オーミック電極、および台座電極が各々発光透過用窓層
と接した構造を有するAlGaInP系発光ダイオード
において、III−V族化合物半導体構成層と反対の伝
導形のIII−V族化合物半導体層(以後、III−V
族化合物半導体接合層とする)が素子平面における台座
電極の射影領域に形成され、該射影領域以外にオーミッ
ク電極が分散されて配置されていることを特徴とするA
lGaInP系発光ダイオード、[2]III−V族化
合物半導体接合層の素子平面における外形状が、台座電
極の底面形状と相似形であり、且つ中心が一致して設け
られていることを特徴とする[1]に記載のAlGaI
nP系発光ダイオード、[3]III−V族化合物半導
体接合層の素子平面における外形状が、台座電極の底面
積の0.5倍以上で1.5倍以下であることを特徴とす
る[1]または[2]に記載のAlGaInP系発光ダ
イオード、[4]発光層が、(AlXGa1-X0.5In
0.5P(0≦X≦1)から形成されていることを特徴と
する[1]〜[3]の何れか1項に記載のAlGaIn
P系発光ダイオード、[5]III−V族化合物半導体
接合層が、(AlYGa1-Y0.5In0.5P(X≦Y≦
1)から構成されていることを特徴とする[4]に記載
のAlGaInP系発光ダイオード、に関する。
Means for Solving the Problems The present inventors have intensively studied to solve the above-mentioned problems, and have arrived at the present invention. That is, the present invention provides [1] a group III-V compound semiconductor constituent layer,
In an AlGaInP-based light-emitting diode having a structure in which an ohmic electrode and a pedestal electrode are each in contact with a light-emitting / transmitting window layer, a III-V compound semiconductor layer (hereinafter referred to as III) having a conductivity type opposite to that of a III-V compound semiconductor constituent layer -V
A) is formed in the projection area of the pedestal electrode on the element plane, and the ohmic electrodes are dispersed and arranged in areas other than the projection area.
The outer shape of the 1GaInP-based light emitting diode, [2] III-V compound semiconductor junction layer in the element plane is similar to the bottom shape of the pedestal electrode, and is provided so that the center is coincident. AlGaI according to [1]
The outer shape of the nP-based light emitting diode and the [3] III-V compound semiconductor bonding layer in the element plane is 0.5 times or more and 1.5 times or less the bottom area of the pedestal electrode. ] Or [2], wherein the [4] light emitting layer is made of (Al x Ga 1 -x ) 0.5 In.
AlGaIn according to any one of [1] to [3], wherein the AlGaIn is formed from 0.5 P (0 ≦ X ≦ 1).
P-based light emitting diode, [5] III-V compound semiconductor junction layer is (Al Y Ga 1 -Y ) 0.5 In 0.5 P (X ≦ Y ≦
The present invention relates to the AlGaInP-based light-emitting diode according to [4], which is configured from 1).

【0009】[0009]

【発明の実施の形態】本発明のAlGaInP系LED
は、III−V族化合物半導体構成層、オーミック電
極、および台座電極が各々発光透過用窓層と接した基本
構造を有する。本発明に係わるAlGaInP系LED
の断面模式図を図1に例示する。図1を利用して説明す
ると、本発明の請求項1に記載の発明に係わる第1の実
施形態のLED10は、主として導電性の単結晶基板1
01の表面上にエピタキシャル成長法に依り積層され
た、例えば(AlXGa1-X0.5In0.5Pからなるn形
またはp形クラッド(clad)層104、106と、
(AlXGa1-X0.5In0.5Pからなる発光層105と
のヘテロ(hetero)接合からなる発光部10a
と、発光部10aを構成する上部クラッド層106上に
冠された導電性の透明酸化物層からなる窓層108とを
基本的に備えて構成されている。下部クラッド層104
と緩衝層102との中間には、ブラッグ反射(DBR)
103を挿入した構成としても差し支えはない。窓層1
08の上表面の中央部にはLED駆動電流を供給するた
めの台座電極109を設ける。また、本発明のLED1
0に特徴的なのは、窓層108をなす透明酸化物層が堆
積された例えばAlGaInP上部クラッド層106と
の間に、その上部クラッド層106とは反対の伝導形の
III−V族化合物半導体接合層107が配置されてい
ることにある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS AlGaInP LED of the present invention
Has a basic structure in which a III-V compound semiconductor constituent layer, an ohmic electrode, and a pedestal electrode are each in contact with a light-emitting and transmitting window layer. AlGaInP-based LED according to the present invention
1 is exemplified in FIG. Referring to FIG. 1, the LED 10 of the first embodiment according to the first embodiment of the present invention mainly includes a conductive single crystal substrate 1.
And n-type or p-type clad layers 104 and 106 made of, for example, (Al x Ga 1 -x ) 0.5 In 0.5 P, which are stacked on the surface of the semiconductor device 01 by an epitaxial growth method.
A light emitting section 10a formed by a hetero junction with a light emitting layer 105 made of (Al x Ga 1 -x) 0.5 In 0.5 P
And a window layer 108 made of a conductive transparent oxide layer covered on the upper cladding layer 106 constituting the light emitting portion 10a. Lower cladding layer 104
Bragg reflection (DBR)
There is no problem even if a configuration in which 103 is inserted is used. Window layer 1
A pedestal electrode 109 for supplying an LED driving current is provided at the center of the upper surface of the substrate 08. In addition, the LED 1 of the present invention
0 is characterized by a III-V compound semiconductor bonding layer having a conductivity type opposite to that of the upper cladding layer 106 between, for example, the AlGaInP upper cladding layer 106 on which the transparent oxide layer forming the window layer 108 is deposited. 107 is arranged.

【0010】III−V族化合物半導体接合層107
は、図1に例示したLED10の断面構造図に示す如
く、例えば、上部クラッド層106の表面の、台座電極
109の射影領域109aに限定して設ける。例えば、
p形の上部クラッド層106上には、n形のIII−V
族化合物半導体接合層107を設ける。n形のIII−
V族化合物半導体構成層上には、p形のIII−V族化
合物半導体接合層を設ける。例えば、上部クラッド層1
06等のLED10を構成するIII−V族化合物半導
体構成層に当該接合層とは反対の伝導形の接合層を接合
させてpn接合を形成することとする。台座電極109
の射影領域109aに電流の通流を阻害するpn接合を
形成すれば、台座電極109より供給される動作電流の
発光部10aへの短絡的な漏洩が避けられる。換言すれ
ば、動作電流を台座電極109の射影領域109a周辺
の開放発光領域106aに優先的に流入させられる効果
が上げられる。即ち、発光の遮蔽領域での動作電流の浪
費が抑えられ、発光を外部へ取り出せる開放発光領域1
06aに優先的に配分することができ、高輝度化を達成
するに優位となる。
III-V compound semiconductor bonding layer 107
As shown in the sectional structural view of the LED 10 illustrated in FIG. 1, for example, the LED is provided only on the projection region 109 a of the pedestal electrode 109 on the surface of the upper cladding layer 106. For example,
On the p-type upper cladding layer 106, an n-type III-V
A group III compound semiconductor bonding layer 107 is provided. n-type III-
A p-type group III-V compound semiconductor junction layer is provided on the group V compound semiconductor constituent layer. For example, the upper cladding layer 1
A pn junction is formed by bonding a bonding layer of the conductivity type opposite to the bonding layer to the III-V compound semiconductor constituent layer constituting the LED 10 such as 06. Pedestal electrode 109
By forming a pn junction in the projection region 109a of the pn junction that obstructs current flow, short-circuit leakage of the operating current supplied from the pedestal electrode 109 to the light emitting unit 10a can be avoided. In other words, the effect that the operating current is preferentially flown into the open light emitting area 106a around the projection area 109a of the pedestal electrode 109 is improved. That is, waste of the operating current in the light-shielding region is suppressed, and the open light-emitting region 1 from which light can be extracted to the outside can be obtained.
06a can be preferentially allocated, which is advantageous for achieving higher luminance.

【0011】III−V族化合物半導体接合層107
は、例えば、上部クラッド層106上に有機金属熱分解
化学的堆積(英略称:MOCVD)法や分子線エピタキ
シャル(英略称:MBE)法等のエピタキシャル成長手
段により成膜できる。成膜されたIII−V族化合物半
導体接合層107に公知のフォトグラフィー技術を利用
してパターニングを施し、不要部分を除去すれば、台座
電極109の射影領域109aのみにIII−V族化合
物半導体接合層107を残置できる。III−V族化合
物半導体接合層107の層厚は透明酸化物からなる窓層
108の層厚を超過しないものとするのが望ましい。I
II−V族化合物半導体接合層107の層厚を窓層10
8のそれを越えて大とすると、接合層107とその被堆
積層との段差が増し、接合層107の周囲を空隙なく被
覆するに困難となる不都合が生ずる。窓層108の厚さ
は発光層105から放射される発光に対し最大の透過率
を帰結する厚さに設定するのが望まれることからして、
接合層107の層厚は、従って、発光波長に対して最大
の透過率を与える窓層108の層厚以下とするのが望ま
しい。
III-V compound semiconductor bonding layer 107
Can be formed on the upper cladding layer 106 by an epitaxial growth means such as a metal organic chemical decomposition (MOCVD) method or a molecular beam epitaxial (MBE) method. By patterning the formed III-V compound semiconductor bonding layer 107 using a known photographic technique and removing unnecessary portions, the III-V compound semiconductor bonding layer is formed only in the projection region 109a of the pedestal electrode 109. Layer 107 can be left. It is desirable that the layer thickness of the III-V compound semiconductor bonding layer 107 does not exceed the layer thickness of the window layer 108 made of a transparent oxide. I
The layer thickness of the II-V compound semiconductor bonding layer 107 is changed to the window layer 10.
If it is larger than that of 8, the step between the bonding layer 107 and the layer to be deposited is increased, and it becomes difficult to cover the periphery of the bonding layer 107 without voids. Since it is desired to set the thickness of the window layer 108 to a thickness that results in the maximum transmittance for the light emitted from the light emitting layer 105,
Therefore, it is desirable that the thickness of the bonding layer 107 be equal to or less than the thickness of the window layer 108 that provides the maximum transmittance for the emission wavelength.

【0012】III−V族化合物半導体接合層107
に、台座電極109の直下の領域への動作電流の漏洩を
下層とのpn接合の形成により阻止するための作用をよ
り効率的に発揮させるためには、III−V族化合物半
導体接合層107のキャリア濃度は、例えば上部クラッ
ド層の如くの被堆積層のキャリア濃度の約1/10以上
とするのが望ましい。被堆積層が例えば、キャリア濃度
を1×1018cm-3とするn形III−V族化合物半導
体層であれば、III−V族化合物半導体接合層107
はp形であり、そのキャリア濃度は1×1017cm-3
上であるのが好ましい。更には、1×1017cm-3以上
で1×1019cm-3以下であるのが好ましい。III−
V族化合物半導体接合層107のキャリア濃度を、1×
1019cm -3を越えて大であると、結晶性は劣るものと
なり耐圧不良を招きかねないため好ましくはない。
III-V compound semiconductor bonding layer 107
In addition, the leakage of the operating current to the area immediately below the pedestal electrode 109 is reduced.
The effect of blocking by forming a pn junction with the lower layer is better.
In order to exhibit the efficiency more efficiently, a group III-V compound
The carrier concentration of the conductor bonding layer 107 is, for example,
About 1/10 or more of the carrier concentration of the layer to be deposited such as
It is desirable that The layer to be deposited has, for example, a carrier concentration
Is 1 × 1018cm-3N-type III-V compound semiconductor
If it is a body layer, the III-V compound semiconductor bonding layer 107
Is p-type and its carrier concentration is 1 × 1017cm-3Less than
It is preferably above. Furthermore, 1 × 1017cm-3that's all
At 1 × 1019cm-3It is preferred that: III-
The carrier concentration of the group V compound semiconductor bonding layer 107 is 1 ×
1019cm -3If it exceeds, the crystallinity is inferior.
This is not preferable because it may cause a breakdown voltage failure.

【0013】III−V族化合物半導体接合層107
は、下地となる被堆積層と良好な格子整合を果たすII
I−V族化合物半導体層から好ましく構成できる。良好
な格子整合性とは格子定数の差異を被堆積層の格子定数
で除した値で与えられる格子のミスマッチ度が概ね、5
%以下であることを云う。例えば、(AlPGa1-P0.
5In0.5Pからなる被堆積層に対し、III−V族化合
物半導体接合層107を砒化アルミニウム・ガリウム
(組成式AlCGa1-CAs:0≦C≦1)から構成する
例が挙げられる。
III-V compound semiconductor bonding layer 107
Achieves good lattice matching with the underlying layer II
It can be preferably composed of an IV group compound semiconductor layer. Good lattice matching means that the degree of lattice mismatch given by the value obtained by dividing the difference in lattice constant by the lattice constant of the layer to be deposited is approximately 5%.
% Or less. For example, (Al P Ga 1-P ) 0.
There is an example in which the III-V compound semiconductor bonding layer 107 is composed of aluminum / gallium arsenide (composition formula: Al C Ga 1-C As: 0 ≦ C ≦ 1) for the layer to be deposited made of 5 In 0.5 P. .

【0014】上記の如くの台座電極109の直下の領域
への動作電流の漏洩を防止できるIII−V族化合物半
導体接合層107を配備した上で、本発明では更に開放
発光領域106aに複数のオーミック電極110を分散
させて設ける。開放発光領域106aとは、台座電極1
09が敷設されている領域以外の発光を外部に取り出す
ことができる領域(素子平面における台座電極の射影領
域以外)を指す。図1に例示するLED10では、平面
形状を円形とするオーミック電極110が開放発光領域
106aに分散されて配置されている。オーミック電極
110の平面形状は楕円形、方形或いは多角形であって
構わない。分散して配置するオーミック電極110の個
数にも限定はない。オーミック電極110は例えば、金
(Au)・ゲルマニウム(Ge)合金、金(Au)・亜
鉛(Zn)合金等から構成できる。III−V族化合物
半導体接合層とのpn接合により、台座電極109の直
下の領域への動作電流の漏洩を抑止し、動作電流を開放
発光領域106aに優先的に配分できる状況を創出した
上で、開放発光領域106aにオーミック電極110を
分散させて設けことにより、各オーミック電極110を
介して動作電流が開放領域106aの広範囲に亘り拡散
できる。
After providing the III-V compound semiconductor bonding layer 107 which can prevent the leakage of the operating current to the region immediately below the pedestal electrode 109 as described above, the present invention further provides a plurality of ohmic contacts in the open light emitting region 106a. The electrodes 110 are provided in a dispersed manner. The open light emitting area 106a is the pedestal electrode 1
09 refers to a region other than the region where the laying is provided, from which light can be extracted to the outside (other than the projection region of the pedestal electrode on the element plane). In the LED 10 illustrated in FIG. 1, ohmic electrodes 110 each having a circular planar shape are arranged in the open light emitting region 106a. The planar shape of the ohmic electrode 110 may be elliptical, square, or polygonal. There is no limitation on the number of the ohmic electrodes 110 to be dispersed. The ohmic electrode 110 can be made of, for example, a gold (Au) / germanium (Ge) alloy, a gold (Au) / zinc (Zn) alloy, or the like. The pn junction with the III-V compound semiconductor junction layer suppresses the leakage of the operating current to the region directly below the pedestal electrode 109, and creates a situation where the operating current can be preferentially distributed to the open light emitting region 106a. By dispersing and providing the ohmic electrodes 110 in the open light emitting region 106a, the operating current can be spread over a wide range of the open region 106a through each ohmic electrode 110.

【0015】本発明の請求項2に記載の発明に係わる第
2の実施形態では、III−V族化合物半導体接合層1
07を、台座電極109の素子平面における外形状と相
似の関係にある結晶層から構成する。即ち、円形の台座
電極については平面形状を円形としたIII−V族化合
物半導体接合層107を配置する。多角形の台座電極に
ついては多角形の高抵抗III−V族化合物半導体層を
設ける。方形の台座電極に対しては方形のIII−V族
化合物半導体接合層を設置する。特に、III−V族化
合物半導体接合層107の平面形状は窓層108と接触
する台座電極109の底面の形状と相似形とするのが望
ましい。
According to a second embodiment of the present invention, a III-V compound semiconductor bonding layer 1 is provided.
07 is made of a crystal layer having a similar relationship to the outer shape of the pedestal electrode 109 in the element plane. That is, for the circular pedestal electrode, the group III-V compound semiconductor bonding layer 107 having a circular planar shape is disposed. A polygonal high-resistance III-V compound semiconductor layer is provided for a polygonal pedestal electrode. For the square base electrode, a square group III-V compound semiconductor bonding layer is provided. In particular, it is desirable that the planar shape of the III-V compound semiconductor bonding layer 107 be similar to the shape of the bottom surface of the pedestal electrode 109 that contacts the window layer 108.

【0016】また、III−V族化合物半導体接合層1
07はその平面形状の中心Mを、台座電極109の平面
形状の中心点Cに合致させて設ける。III−V族化合
物半導体接合層107の平面形状を台座電極109の底
面形状と相似形とした上に、互いに中心点M、Cを一致
させて配置することにより、台座電極109の底面の全
般的な領域に於いて発光部10aへの短絡的な動作電流
の流通を効率的に防止できる。例えば、上部クラッド層
106上に一旦、III−V族化合物半導体接合層10
7を、例えば、有機金属熱分解気相成長(MOCVD)
法で積層した後、一般的なフォトリソグラフィー技術を
利用したパターニング技法に依り、台座電極109の射
影領域109aの中心に、中心を合致させてIII−V
族化合物半導体接合層107を残置させると好適とな
る。III−V族化合物半導体接合層107と台座電極
109との平面形状の中心点M、Cとを一致させること
により、平面形状の中心の“ずれ”に因る動作電流の発
光部10aへの偏流を防止することができる。上記の中
心点C、Mが合致させないと、台座電極109から供給
される動作電流は中心点C、Mの“ずれ”のために発生
した、台座電極109の射影領域109aに於けるII
I−V族化合物半導体接合層107の非被覆領域を通過
して発光部10aに短絡的に流通してしまう不都合が生
ずる。
Further, the III-V compound semiconductor bonding layer 1
Reference numeral 07 is provided such that the center M of the planar shape matches the center point C of the planar shape of the pedestal electrode 109. By making the planar shape of the III-V compound semiconductor bonding layer 107 similar to the bottom shape of the pedestal electrode 109 and arranging the center points M and C so as to match each other, the overall bottom surface of the pedestal electrode 109 is formed. It is possible to efficiently prevent the short-circuiting operation current from flowing to the light-emitting portion 10a in the appropriate region. For example, once on the upper cladding layer 106, the III-V compound semiconductor bonding layer 10
7, for example, metalorganic thermal decomposition vapor deposition (MOCVD)
After stacking by the method, the center is matched with the center of the projection region 109a of the pedestal electrode 109 by a patterning technique using a general photolithography technique, and the III-V
It is preferable to leave the group III compound semiconductor bonding layer 107. By aligning the center points M and C of the planar shapes of the III-V compound semiconductor bonding layer 107 and the pedestal electrode 109, the operating current is caused to drift to the light emitting portion 10a due to the "deviation" of the planar shape center. Can be prevented. If the center points C and M do not match, the operating current supplied from the pedestal electrode 109 will be II due to the "shift" of the center points C and M in the projection area 109a of the pedestal electrode 109.
The inconvenience of short-circuiting to the light emitting portion 10a through the uncovered region of the IV compound semiconductor bonding layer 107 occurs.

【0017】台座電極109の底面積に対するIII−
V族化合物半導体接合層107の素子平面における外形
状の面積の比率には好適な範囲がある。台座電極109
の底面積に対してIII−V族化合物半導体接合層10
7の占める面積が極端に小であると発光部10aへの短
絡的な電流が増える。一方、III−V族化合物半導体
接合層107の面積が極端に大であると開放発光面積が
減少し、発光の高輝度化が難となる。従って、本発明の
請求項3に記載の発明に係わる第3の実施形態では、I
II−V族化合物半導体接合層107の素子平面におけ
る外形状の面積は台座面積の底面積に比して大凡、0.
5倍以上で3倍以下とするのが望ましい。更には、0.
7倍以上で1.2倍以下とするのを好ましいとする。
III- with respect to the bottom area of the pedestal electrode 109
There is a suitable range for the ratio of the area of the outer shape on the element plane of the group V compound semiconductor bonding layer 107. Pedestal electrode 109
III-V compound semiconductor bonding layer 10 with respect to the bottom area of
If the area occupied by 7 is extremely small, a short-circuit current to the light emitting unit 10a increases. On the other hand, if the area of the III-V compound semiconductor bonding layer 107 is extremely large, the open light-emitting area decreases, and it becomes difficult to increase the luminance of light emission. Therefore, in the third embodiment according to the third aspect of the present invention,
The area of the outer shape of the II-V compound semiconductor bonding layer 107 in the element plane is approximately 0.1 mm as compared with the bottom area of the pedestal area.
It is desirable to set it to 5 times or more and 3 times or less. Furthermore, 0.
It is preferable that the ratio be 7 times or more and 1.2 times or less.

【0018】本発明の請求項4および5に記載の発明に
係わる第4および5の実施形態では、発光層105をG
aAs基板と格子整合しやすい(AlXGa1-X0.5
0.5P(0≦X≦1)層から形成し、III−V族化
合物半導体接合接合層107を、発光層105を構成す
る(AlXGa1-X0.5In0.5P(0≦X≦1)層のア
ルミニウム(Al)組成比(=X)以上の、アルミニウ
ム組成比(=Y)の(AlYGa1-Y0.5In0.5P(即
ち、X≦Y≦1)から構成するのを特徴とする。(Al
YGa1-Y0.5In0.5Pはアルミニウム組成比(=Y)
の如何に拘わらず、(AlXGa1-X0.5In0.5Pと良
好な格子整合性を果たすのみでなく、アルミニウム組成
比(=Y)の増大と共に禁止帯幅(bandgap)も
増加する。アルミニウム組成比(=Y)を発光層105
のそれ(=X)以上とする(AlYGa1-Y0.5In0.5
Pは発光を透過できる。従って、発光層105以上の禁
止帯幅の(AlYGa1-Y0.5In0.5Pからは、発光を
透過しつつ電流阻止層としての機能を発揮するIII−
V族化合物半導体接合層107が構成できる。
In the fourth and fifth embodiments according to the fourth and fifth aspects of the present invention, the light emitting layer 105 is made of G
(Al x Ga 1-x ) 0.5 I that is easily lattice-matched to the aAs substrate
An n 0.5 P (0 ≦ X ≦ 1) layer is formed, and the III-V compound semiconductor junction bonding layer 107 forms the (Al x Ga 1-x ) 0.5 In 0.5 P (0 ≦ X ≦ 1) The layer is composed of (Al Y Ga 1-Y ) 0.5 In 0.5 P (that is, X ≦ Y ≦ 1) having an aluminum composition ratio (= Y) which is equal to or more than the aluminum (Al) composition ratio (= X) of the layer. It is characterized by. (Al
Y Ga 1-Y ) 0.5 In 0.5 P is the aluminum composition ratio (= Y)
In addition to achieving good lattice matching with (Al X Ga 1 -x ) 0.5 In 0.5 P, the band gap increases with an increase in the aluminum composition ratio (= Y). The aluminum composition ratio (= Y) was changed to
(= X) or more (Al Y Ga 1 -Y ) 0.5 In 0.5
P can transmit light. Therefore, from the band gap of (Al Y Ga 1 -Y ) 0.5 In 0.5 P having a band gap equal to or larger than that of the light emitting layer 105, III- which exhibits a function as a current blocking layer while transmitting light emission.
The group V compound semiconductor bonding layer 107 can be formed.

【0019】[0019]

【実施例】以下、本発明をIII−V族化合物半導体接
合層を具備するAlGaInP系LEDを構成する場合
を例にして詳細に説明する。図2に本実施例に係わるA
lGaInP系LED20の平面模式図を示す。また、
図3は図2に示すLED20の破線A−A’に沿った断
面模式図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail by taking as an example the case of forming an AlGaInP-based LED having a III-V compound semiconductor junction layer. FIG. 2 shows A according to this embodiment.
1 shows a schematic plan view of an lGaInP-based LED 20. FIG. Also,
FIG. 3 is a schematic cross-sectional view of the LED 20 shown in FIG. 2 along the broken line AA ′.

【0020】LED20は、直径約50mmの亜鉛(Z
n)ドープp形(001)−GaAs単結晶円形基板2
01上に順次、積層されたZnドープp形GaAs緩衝
層202、何れもZnをドーピングしたp形Al0.40
0.60As層とp形Al0.95Ga0.05As層とを交互に
10層積層した周期構造からなるブラッグ反射(DB
R)層203、Znドープp形(Al0.7Ga0.30.5
In0.5Pから成る下部クラッド層204、アンドープ
のn形(Al0.2Ga0.80.5In0.5P混晶から成る発
光層205、Siドープn形(Al0.7Ga0.30.5
0.5Pから成る上部クラッド層206、Znドープp
形(Al0.3Ga0.70.5In0.5Pから成るIII−V
族化合物半導体接合層207から構成されるエピタキシ
ャル積層構造体(ウェハ)2Aを母体材料として構成し
た。
The LED 20 is made of zinc (Z) having a diameter of about 50 mm.
n) Doped p-type (001) -GaAs single crystal circular substrate 2
01, a Zn-doped p-type GaAs buffer layer 202, which is sequentially stacked, and a Zn-doped p-type Al 0.40 G
a Bragg reflection (DB) having a periodic structure in which ten a 0.60 As layers and ten p-type Al 0.95 Ga 0.05 As layers are alternately stacked.
R) layer 203, Zn-doped p-type (Al 0.7 Ga 0.3 ) 0.5
A lower cladding layer 204 made of In 0.5 P, a light emitting layer 205 made of an undoped n-type (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P mixed crystal, and a Si-doped n-type (Al 0.7 Ga 0.3 ) 0.5 I
n 0.5 P upper cladding layer 206, Zn-doped p
III-V consisting of (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P
The epitaxial laminated structure (wafer) 2A composed of the group III compound semiconductor bonding layer 207 was formed as a base material.

【0021】積層構造体2Aを構成する各構成層202
〜207はトリメチルアルミニウム((CH33
l)、トリメチルガリウム((CH33Ga)及びトリ
メチルインジウム((CH33In)をIII族構成元
素の原料とする減圧MOCVD法により成膜した。亜鉛
(Zn)のドーピング源にはジエチル亜鉛((C25
2Zn)を利用した。珪素(Si)のドーパント源には
ジシラン(Si26)を使用した。各構成層202〜2
07の成膜温度は730℃に統一した。緩衝層202の
キャリア濃度は約5×1018cm-3に、また、層厚は約
1μmとした。DBR層203をなすp形Al0.40Ga
0.60As層とp形Al0.95Ga0.05As層の層厚は各
々、約40nmとした。キャリア濃度は各々、約1×1
18cm-3とした。下部クラッド層204のキャリア濃
度は約3×1018cm-3に、また、層厚は約1.5μm
とした。発光層205の層厚は約750nmとし、キャ
リア濃度は約5×1016cm-3とした。上部クラッド層
206のキャリア濃度は約1×1018cm-3とし、ま
た、層厚は約5μmとした。Znドープp形(Al0.7
Ga0 .30.5In0.5P層207のキャリア濃度は約5
×1018cm-3とし、層厚は約100nmとした。
Each constituent layer 202 constituting the laminated structure 2A
To 207 are trimethyl aluminum ((CH 3 ) 3 A)
l), trimethylgallium ((CH 3 ) 3 Ga) and trimethyl indium ((CH 3 ) 3 In) were formed by a low-pressure MOCVD method using a group III constituent element as a raw material. Diethyl zinc ((C 2 H 5 )) is used as a zinc (Zn) doping source.
2 Zn) was used. Disilane (Si 2 H 6 ) was used as a silicon (Si) dopant source. Each constituent layer 202-2
The film forming temperature of 07 was unified to 730 ° C. The carrier concentration of the buffer layer 202 was about 5 × 10 18 cm −3 , and the layer thickness was about 1 μm. P-type Al 0.40 Ga forming the DBR layer 203
The thickness of each of the 0.60 As layer and the p-type Al 0.95 Ga 0.05 As layer was about 40 nm. Each carrier concentration is about 1 × 1
0 18 cm −3 . The lower cladding layer 204 has a carrier concentration of about 3 × 10 18 cm −3 and a thickness of about 1.5 μm.
And The thickness of the light emitting layer 205 was about 750 nm, and the carrier concentration was about 5 × 10 16 cm −3 . The carrier concentration of the upper cladding layer 206 was about 1 × 10 18 cm −3, and the layer thickness was about 5 μm. Zn-doped p-type (Al 0.7
Ga 0 .3) 0.5 In 0.5 the carrier concentration of the P layer 207 is about 5
× 10 18 cm -3 and a layer thickness of about 100 nm.

【0022】次に、公知のフォトリソグラフィー技術を
利用して、窓層208表面上の台座電極209を形成す
る予定の領域に対応する射影領域209aに限り、直径
を110μmとする円形にZnドープp形(Al0.7
0.30.5In0.5P層207を残置させた。台座電極
209の射影領域209aの中心点Cと、下層のIII
−V族化合物半導体接合層207との中心点Mとは合致
させた。その後、射影領域209a以外の領域に露呈し
ているZnドープp形(Al0.7Ga0.30.5In0.5
層207の表面に全面に一旦、金(Au88重量%)・
ゲルマニウム(Ge12重量%)合金膜を一般的な真空
蒸着法により被着させた。合金膜の厚さは約100nm
とした。次に、フォトリソグラフィー技術を利用して再
びパターニングを施し、今度は、オーミック電極210
を形成する領域に限り、上記のAu・Ge合金膜を残置
させた。合金膜を残置させた領域は一辺を20μmとす
る正方形とした。然る後、アルゴン(元素記号:Ar)
気流中に於いて420℃で10分間の合金化熱処理を施
した。オーミック電極210は上部クラッド層206の
開放発光領域206aの表面上に合計8箇所に互いに5
0μmの等距離をもって分散させて形成した。
Next, using a known photolithography technique, only the projection region 209a corresponding to the region where the pedestal electrode 209 is to be formed on the surface of the window layer 208 is formed in a circular shape with a Zn-doped p-type having a diameter of 110 μm. Shape (Al 0.7 G
a 0.3 ) 0.5 In 0.5 P layer 207 was left. The center point C of the projection region 209a of the pedestal electrode 209 and the lower layer III
The center point M of the −V group compound semiconductor bonding layer 207 was matched. After that, the Zn-doped p-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P exposed in a region other than the projection region 209a
Once on the entire surface of the layer 207, gold (Au 88% by weight)
A germanium (Ge 12 wt%) alloy film was deposited by a common vacuum deposition method. Alloy film thickness is about 100nm
And Next, patterning is performed again using photolithography technology, and this time, ohmic electrodes 210 are formed.
The above Au / Ge alloy film was left only in the region where was formed. The region where the alloy film was left was a square having a side of 20 μm. After that, argon (element symbol: Ar)
An alloying heat treatment was performed at 420 ° C. for 10 minutes in an air stream. The ohmic electrodes 210 are located on the surface of the open light-emitting region 206a of the upper cladding layer 206 at a total of eight locations.
It was formed by dispersing at an equal distance of 0 μm.

【0023】次に、オーミック電極210と、分散させ
たオーミック電極210以外の上部クラッド層206の
表面と、台座電極209の射影領域209aに限定して
残置したIII−V族化合物半導体接合層207を被覆
する様に発光を外部に透過する窓層208として酸化イ
ンジウム・錫(ITO)膜を被着させた。ITO膜は一
般的なマグネトロンスパッタリング法により被着させ
た。ITO層の比抵抗は約5×10-4Ω・cmであり、
層厚は約600nmとした。次に、窓層208上の全面
に一般的な有機フォトレジスト材料を塗布した後、台座
電極209を設けるべき領域を、公知のフォトリソグラ
フィー技術を利用してパターニングした。然る後、パタ
ーニングされたレジスト材料を残置させたままで、全面
に金(Au)膜を真空蒸着法により被着させた。金(A
u)膜の厚さは約700nmとした。その後、周知のリ
フト−オフ(lift−off)手段に依り、レジスト
材料を剥離するに併せて台座電極209の形成予定領域
に限定してAu膜を残留させた。これより、直径を約1
10μmとする円形の台座電極209を形成した。即
ち、III−V族化合物半導体接合層207との表面積
は同一とした。
Next, the ohmic electrode 210, the surface of the upper cladding layer 206 other than the dispersed ohmic electrode 210, and the group III-V compound semiconductor bonding layer 207 left only in the projection region 209a of the pedestal electrode 209 are removed. An indium tin oxide (ITO) film was applied as a window layer 208 for transmitting light emission to the outside so as to cover the film. The ITO film was applied by a general magnetron sputtering method. The specific resistance of the ITO layer is about 5 × 10 −4 Ω · cm,
The layer thickness was about 600 nm. Next, after a general organic photoresist material was applied to the entire surface of the window layer 208, a region where the pedestal electrode 209 was to be provided was patterned using a known photolithography technique. Thereafter, a gold (Au) film was deposited on the entire surface by a vacuum deposition method while the patterned resist material was left. Gold (A
u) The thickness of the film was about 700 nm. After that, according to a well-known lift-off means, the Au film was left only in the region where the pedestal electrode 209 was to be formed while the resist material was peeled off. From this, the diameter is about 1
A circular pedestal electrode 209 having a thickness of 10 μm was formed. That is, the surface area of the group III-V compound semiconductor bonding layer 207 was the same.

【0024】p形GaAs単結晶基板201の裏面に
は、金・亜鉛(Au・Zn)合金からなるp形オーミッ
ク電極211を形成した後、通常のスクライブ法により
積層構造体(ウェハ)2Aを裁断して個別に細分化し、
一辺の長さを260μmとするLED20となした。p
形オーミック電極211及び台座電極209間に順方向
に電流を通流したところ、開放発光領域206aを通し
て波長を約620nmとする赤橙色が出射された。発光
スペクトルの半値幅は約20nmであり、単色性に優れ
る発光であった。20ミリアンペア(mA)の電流を通
流した際の順方向電圧(Vf:@20mA)は、分配し
て配置した型オーミック電極210の良好なオーミック
特性を反映して約2.1ボルト(V)となった。また、
分配してオーミック性電極210を配置した効果に依
り、チップ20の周縁20bの領域に於いても発光が認
められ、視感度補正をした状態で簡易的に測定される発
光の強度は約70ミリカンデラ(mcd)であった。更
に、本実施例のLED20では、近視野発光パターンの
観点からしても開放発光面206aに於ける発光強度の
分布は、オーミック電極210に依る動作電流の均一な
分配の効果により均等であった。
After a p-type ohmic electrode 211 made of a gold-zinc (Au-Zn) alloy is formed on the back surface of the p-type GaAs single crystal substrate 201, the laminated structure (wafer) 2A is cut by a usual scribing method. And subdivide it individually,
The LED 20 had a side length of 260 μm. p
When a current was passed between the ohmic electrode 211 and the pedestal electrode 209 in the forward direction, red-orange light having a wavelength of about 620 nm was emitted through the open light emitting region 206a. The half width of the light emission spectrum was about 20 nm, and the light emission was excellent in monochromaticity. The forward voltage (Vf: @ 20 mA) when a current of 20 milliamperes (mA) flows is about 2.1 volts (V), reflecting the good ohmic characteristics of the distributed ohmic electrode 210. It became. Also,
Due to the effect of distributing and arranging the ohmic electrodes 210, light emission is also observed in the region of the peripheral edge 20b of the chip 20, and the light emission intensity measured simply with the visibility corrected is about 70 mm. Candela (mcd). Further, in the LED 20 of the present embodiment, even from the viewpoint of the near-field light emission pattern, the distribution of the light emission intensity on the open light emission surface 206a was uniform due to the effect of the uniform distribution of the operation current by the ohmic electrode 210. .

【0025】[0025]

【発明の効果】本発明の請求項1に記載の発明に依れ
ば、台座電極の射影領域外の開放発光領域にオーミック
電極を分散して設けた上に、台座電極の直下の領域にp
n接合をなすIII−V族化合物半導体接合層を設ける
構成としたので、台座電極の直下の発光部への動作電流
の短絡的な漏洩を抑制して開放発光領域に優先的に供給
される動作電流を同領域に広範囲に分散できるため、発
光領域が拡大された高輝度のAlGaInP系発光ダイ
オードが提供できる。
According to the first aspect of the present invention, the ohmic electrodes are dispersedly provided in the open light-emitting area outside the projection area of the pedestal electrode, and the p-type is formed in the area immediately below the pedestal electrode.
Since the structure is such that the III-V compound semiconductor junction layer forming the n-junction is provided, the short-circuit leakage of the operating current to the light emitting portion immediately below the pedestal electrode is suppressed, and the operation is preferentially supplied to the open light emitting region. Since the current can be widely distributed in the same region, an AlGaInP-based light-emitting diode having a high luminance and an enlarged light-emitting region can be provided.

【0026】また、本発明の請求項2に記載の発明に依
れば、台座電極と相似形のIII−V族化合物半導体接
合層を台座電極の平面形状の中心に合致させて設ける構
成としたので、特に、効率的に動作電流の台座電極の直
下領域への漏洩が防止され、開放発光領域に優先的に動
作電流を配分できるため、高輝度のAlGaInP系発
光ダイオードが提供できる。
According to the second aspect of the present invention, a III-V compound semiconductor bonding layer similar in shape to the pedestal electrode is provided so as to match the center of the planar shape of the pedestal electrode. Therefore, particularly, the leakage of the operating current to the region immediately below the pedestal electrode can be efficiently prevented, and the operating current can be preferentially distributed to the open light emitting region, so that a high-luminance AlGaInP-based light emitting diode can be provided.

【0027】また、本発明の請求項3に記載の発明に依
れば、III−V族化合物半導体接合層の表面積を台座
電極の表面積に対して規定することとしたので、特に、
効率的に動作電流の台座電極の直下領域への漏洩を防止
するに効果が上げられ、高輝度のAlGaInP系発光
ダイオードが提供できる。
According to the third aspect of the present invention, the surface area of the III-V compound semiconductor bonding layer is defined with respect to the surface area of the pedestal electrode.
The effect of efficiently preventing the operating current from leaking to the region immediately below the pedestal electrode is improved, and a high-luminance AlGaInP-based light-emitting diode can be provided.

【0028】また、本発明の請求項4および5に記載の
発明に依れば、基板と格子整合する(AlXGa1-X
0.5In0.5Pからなる発光層、および発光層以上の禁止
帯幅を有する(AlYGa1-Y0.5In0.5PからIII
−V族化合物半導体接合層を構成することとしたので、
台座電極直下への動作電流の漏洩を抑制しつつ、且つ発
光を透過できるため、高輝度のAlGaInP系発光ダ
イオードが提供できる。
According to the fourth and fifth aspects of the present invention, the substrate is lattice-matched (Al x Ga 1 -x ).
A light emitting layer composed of 0.5 In 0.5 P, and a (Al Y Ga 1-Y ) 0.5 In 0.5 P to III having a band gap greater than or equal to the light emitting layer
Since a -V compound semiconductor junction layer is to be formed,
Since light emission can be transmitted while suppressing leakage of an operating current directly below the pedestal electrode, a high-luminance AlGaInP-based light-emitting diode can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係わるAlGaInP系LEDの断面
模式図である。
FIG. 1 is a schematic sectional view of an AlGaInP-based LED according to the present invention.

【図2】実施例1に記載のAlGaInP系LEDの平
面模式図である。
FIG. 2 is a schematic plan view of the AlGaInP-based LED described in Example 1.

【図3】図2のLEDの破線A−A’に沿った断面模式
図である。
FIG. 3 is a schematic cross-sectional view of the LED of FIG. 2 along a broken line AA ′.

【符号の説明】[Explanation of symbols]

10 AlGaInP系LED 10a pn接合型ダブルヘテロ接合発光部 101 単結晶基板 102 緩衝層 103 ブラッグ反射層 104 下部クラッド層 105 発光層 106 上部クラッド層 106a 開放発光領域 107 III−V族化合物半導体接合層 108 窓層 109 台座電極 109a 台座電極の射影領域 110 オーミック電極 111 基板裏面オーミック電極 C 台座電極の中心点 M III−V族化合物半導体接合層の中心点 2A 積層構造体 20 AlGaInP系LED 20b LEDチップの外縁 201 p形方GaAs単結晶基板 202 p形GaAs緩衝層 203 ブラッグ反射層 204 AlGaInP系下部クラッド層 205 AlGaInP系発光層 206 AlGaInP系上部クラッド層 206a 開放発光領域 207 III−V族化合物半導体接合層 208 導電性透明酸化物窓層 209 台座電極 209a 台座電極の射影領域 210 オーミック電極 211 p形オーミック電極 REFERENCE SIGNS LIST 10 AlGaInP-based LED 10 a pn junction type double hetero junction light emitting unit 101 single crystal substrate 102 buffer layer 103 Bragg reflection layer 104 lower cladding layer 105 light emitting layer 106 upper cladding layer 106 a open light emitting region 107 III-V compound semiconductor bonding layer 108 window Layer 109 Pedestal electrode 109a Projection area of pedestal electrode 110 Ohmic electrode 111 Ohmic electrode on backside of substrate C Center point of pedestal electrode M Center point of MIII-V compound semiconductor bonding layer 2A Stacked structure 20 AlGaInP LED 20b Outer edge of LED chip 201 p-type GaAs single crystal substrate 202 p-type GaAs buffer layer 203 Bragg reflection layer 204 AlGaInP-based lower clad layer 205 AlGaInP-based light-emitting layer 206 AlGaInP-based upper clad layer 206a open light emission Projection region 210 ohmic electrode 211 p-type ohmic electrode band 207 III-V group compound semiconductor junction layer 208 conductive transparent oxide window layer 209 the base electrode 209a seat electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 宇田川 隆 埼玉県秩父市下影森1505番地 昭和電工株 式会社総合研究所秩父研究室内 Fターム(参考) 5F041 AA03 CA04 CA34 CA36 CA65 CA73 CA74 CA83 CA85 CA88 CA93 CA98 CB15  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Udagawa 1505 Shimokagemori, Chichibu-shi, Saitama F-term (reference) 5F041 AA03 CA04 CA34 CA36 CA65 CA73 CA74 CA83 CA85 CA88 CA93 CA98 CB15

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】III−V族化合物半導体構成層、オーミ
ック電極、および台座電極が各々発光透過用窓層と接し
た構造を有するAlGaInP系発光ダイオードにおい
て、III−V族化合物半導体構成層と反対の伝導形の
III−V族化合物半導体層(以後、III−V族化合
物半導体接合層とする)が素子平面における台座電極の
射影領域に形成され、該射影領域以外にオーミック電極
が分散されて配置されていることを特徴とするAlGa
InP系発光ダイオード。
1. An AlGaInP-based light-emitting diode having a structure in which a III-V compound semiconductor constituent layer, an ohmic electrode, and a pedestal electrode are each in contact with a light-emitting / transmitting window layer, the opposite of the III-V compound semiconductor constituent layer. A conductive type III-V compound semiconductor layer (hereinafter referred to as a III-V compound semiconductor junction layer) is formed in a projection area of a pedestal electrode on an element plane, and ohmic electrodes are dispersed and arranged in areas other than the projection area. AlGa characterized in that
InP-based light emitting diode.
【請求項2】III−V族化合物半導体接合層の素子平
面における外形状が、台座電極の底面形状と相似形であ
り、且つ中心が一致して設けられていることを特徴とす
る請求項1に記載のAlGaInP系発光ダイオード。
2. The semiconductor device according to claim 1, wherein the outer shape of the III-V compound semiconductor bonding layer in the element plane is similar to the bottom shape of the pedestal electrode, and is provided so as to coincide with the center. 2. An AlGaInP-based light-emitting diode according to item 1.
【請求項3】III−V族化合物半導体接合層の素子平
面における外形状が、台座電極の底面積の0.5倍以上
で1.5倍以下であることを特徴とする請求項1または
2に記載のAlGaInP系発光ダイオード。
3. The device according to claim 1, wherein the outer shape of the III-V compound semiconductor bonding layer in the element plane is 0.5 times or more and 1.5 times or less the bottom area of the pedestal electrode. 2. An AlGaInP-based light-emitting diode according to item 1.
【請求項4】発光層が、(AlXGa1-X0.5In0.5
(0≦X≦1)から形成されていることを特徴とする請
求項1〜3の何れか1項に記載のAlGaInP系発光
ダイオード。
4. A light-emitting layer comprising: (Al X Ga 1 -X ) 0.5 In 0.5 P
The AlGaInP-based light-emitting diode according to claim 1, wherein the AlGaInP-based light-emitting diode is formed from (0 ≦ X ≦ 1).
【請求項5】III−V族化合物半導体接合層が、(A
YGa1-Y0.5In0.5P(X≦Y≦1)から構成され
ていることを特徴とする請求項4に記載のAlGaIn
P系発光ダイオード。
5. The method according to claim 1, wherein the group III-V compound semiconductor bonding layer comprises (A)
5. The AlGaIn according to claim 4, wherein the AlGaIn is composed of (L Y Ga 1-Y ) 0.5 In 0.5 P (X ≦ Y ≦ 1).
P-based light emitting diode.
JP33907099A 1999-11-30 1999-11-30 AlGaInP light emitting diode Expired - Fee Related JP4050435B2 (en)

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JP33907099A JP4050435B2 (en) 1999-11-30 1999-11-30 AlGaInP light emitting diode

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JP2001156333A true JP2001156333A (en) 2001-06-08
JP4050435B2 JP4050435B2 (en) 2008-02-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156590A (en) * 2004-11-26 2006-06-15 Mitsubishi Cable Ind Ltd Light emitting diode
JP2013197350A (en) * 2012-03-21 2013-09-30 Sharp Corp Semiconductor light-emitting element and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156590A (en) * 2004-11-26 2006-06-15 Mitsubishi Cable Ind Ltd Light emitting diode
JP2013197350A (en) * 2012-03-21 2013-09-30 Sharp Corp Semiconductor light-emitting element and manufacturing method of the same

Also Published As

Publication number Publication date
JP4050435B2 (en) 2008-02-20

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