JP2001148680A - Radio communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a radio communication system capable of easily detecting synchronizing signals and simplifying the constitution of a detecting circuit while maintaining detection accuracy in the case of forming the synchronizing signals by OFDM modulation waves. SOLUTION: This radio communication system is constituted of a plurality of radio communication terminals and a radio communication control terminal for controlling radio communications. Among the individual radio communication terminals and the radio communication control terminal, data communications are performed by an OFDM system. The radio control terminals sends the synchronizing signals to the radio communication terminals for respective frames and the individual radio communication terminals receive the synchronizing signals, set a timer by the reception timing and set the timing of transmission and reception with the timer as a reference. Since the synchronizing signals are formed by using a real part or an imaginary part in the complex modulation data obtained by OFDM modulation of synchronizing codes, the synchronizing signals are detected in a small-scaled and simple correlation computing circuit on the reception side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication system such as a wireless LAN for connecting a plurality of terminals wirelessly.

[0002]

2. Description of the Related Art As computers become more sophisticated, a plurality of computers are connected to form a LAN (Local Area Network).
In order to share files and data, and to transfer e-mails and data, it is actively performed. In a conventional LAN, each computer is connected in a wired manner using an optical fiber, a coaxial cable, or a twisted pair cable.

However, such a wired LAN requires construction for connection, making it difficult to construct the LAN easily, and the cable becomes complicated in the wired LAN. Therefore, L by the conventional wired system
Wireless LANs have attracted attention as a system that frees users from AN wiring.

Conventionally, as a wireless LAN, CDMA (Code Division Multiple Acce
ss) is proposed for performing data communication. In the CDMA system, a PN code (Psuede
o Noise Code) and the spectrum of the transmission data is expanded. The data spread and transmitted in this manner is demodulated by multiplying by the same PN code as that on the transmitting side. The CDMA system is characterized by high confidentiality and excellent interference resistance.

[0005]

In recent years, the use of multimedia has been advanced, and data having a large data amount, such as image data and audio data, has been increasingly used. For this reason, there has been a demand for a wireless LAN to increase the transfer rate so that large data such as image data and audio data can be sent. However, in spread spectrum modulation, for example,
When data transfer is performed at a high rate of about 30 Mbps,
A bandwidth of 300 MHz or more is required. Such a wide bandwidth cannot be secured by the current frequency allocation, and it is difficult to perform communication while securing such a wide bandwidth.

[0006] In the spread spectrum, to demodulate a received signal, the phase of the code of the transmitted data is set to
A synchronization acquisition time for adjusting the phase of a clock signal generated in a receiver for demodulation is required. For this reason, in spread spectrum, a bit string for synchronization is inserted into each packet in order to acquire synchronization at high speed, and the number of bits other than valid data increases due to such a bit string for synchronization, There is a problem that communication efficiency is reduced.

One method for solving this problem is to use OFDM (Orthogonal FDM) instead of spread spectrum modulation.
The transmission data is modulated by frequency division multiplexing. In each wireless communication terminal, a transmission / reception device for transmitting / receiving data in accordance with the OFDM modulation method is provided, a synchronization code generation circuit for generating a synchronization code for synchronization acquisition in the transmission device, and a synchronization code detected in the reception device;
A synchronization detection circuit that controls reception timing in accordance with the detection timing of the synchronization code; and a timing control circuit. Further, in a wireless LAN system that performs communication between each of a plurality of communication terminals, each communication terminal modulates transmission data according to an OFDM modulation scheme to form a symbol that is a transmission unit of an OFDM modulation signal, and generates a predetermined symbol. A so-called TDMA (Time division multiple acces) that multiplexes data in a time-division manner with a number frame structure.
s) The method is adopted. Then, a synchronization code for acquiring synchronization is added to each frame and transmitted together with the OFDM-modulated information data. Thus, in the communication terminal receiving the transmission data, the synchronization code can be detected, a local timer can be set according to the detection timing, and the transmission / reception timing can be controlled using the timer as a time reference.

Hitherto, a PN code, that is, a code composed of a pseudo-random number sequence, has been used as a synchronization code for acquiring synchronization. For example, in various wireless communication systems proposed so far, an M sequence is generally used as a synchronization code. In these wireless communication systems, data is transmitted by OFDM modulation, and TDM is transmitted in units of one frame.
Data communication is performed by DMA. Then, an M sequence is sent as a synchronization signal at the beginning of one frame. On the receiving side, this M
The transmission / reception timing is set based on the sequence. The transmission and reception time of each wireless communication control terminal is instructed by control information from the wireless communication control terminal. OF
When the DM method is used, the transfer rate can be increased due to the property of OFDM, and even if jitter occurs, demodulation can be performed without error. Since the transmission / reception timing is set based on the first M sequence of one frame, the timer of each wireless communication terminal is set to be equal, and at the time of reception, only the necessary symbols in the frame are used by using this time information. Data can be reproduced by demodulation. Therefore, it is not necessary to acquire synchronization for each burst prior to reception, and it is not necessary to arrange synchronization bits for each burst. Therefore, the bits in the frame can be used efficiently.

However, when a PN code is used as a synchronization signal, a generation circuit for generating the PN code is required.
For this reason, a method has been proposed in which a specific data sequence modulated by OFDM is used as a synchronization signal instead of a PN code. Thereby, in the transmitting device of the communication terminal,
Generation of a synchronization signal is easy and simple. On the other hand, OFD
A problem arises in that the synchronization timing is inaccurate during M demodulation. Further, the OFDM modulated signal is different from the PN code,
Since it is a complex number, in the receiving device of the communication terminal, a complex multiplication process is required to detect a synchronization signal by a correlation operation, which increases the circuit scale.

Consider, for example, the use of data of 32 samples as a synchronization signal. Sync signal to P
When the correlator is composed of N codes, the correlator can be composed of 32 stages of multiplication circuits of complex numbers and real numbers. On the other hand, when the synchronization signal is constituted by an OFDM modulation signal,
In order to construct a correlator, a multiplication circuit of complex numbers
You have to be ready. For this reason, when detecting a synchronization signal of a complex OFDM modulation signal, there is a disadvantage that the scale of the correlator expands almost four times as compared with a case of detecting a synchronization signal of a PN code consisting of only a real part. Further, in the case of the PN code, the multiplier can be substantially realized by an adder circuit and can be realized by a very simple circuit configuration.
In the case of an OFDM modulated signal that is a complex number, it is difficult to realize this simply with an adder circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to easily detect a synchronization signal when an OFDM modulation signal is used to form the synchronization signal, and to maintain the detection accuracy while maintaining the detection accuracy. An object of the present invention is to provide a wireless communication system capable of simplifying the configuration of a detection circuit.

[0012]

To achieve the above object, a wireless communication system according to the present invention is a wireless communication system having a wireless communication terminal and a wireless communication control terminal for controlling the wireless communication terminal, The wireless communication control terminal,
A transmitting unit and a receiving unit for transmitting and receiving data by the OFDM method, and a synchronous signal generating unit for OFDM modulating the code sequence for synchronous detection and generating a synchronous signal using a predetermined partial signal of the modulated signal, The wireless communication terminal includes transmission means and reception means for transmitting and receiving data in an OFDM system, synchronization detection means for detecting a synchronization signal, and timer means set by the synchronization detection means. Between the wireless communication control terminal, data is modulated by the OFDM method, and T is expressed by a frame structure of a predetermined number of symbols.
The wireless communication control terminal performs multiplexing of data by a DMA system, the wireless communication control terminal transmits the synchronization signal to the wireless communication terminal for each frame, and the synchronization signal transmission means. Communication control means for setting the timer according to the timing at which the synchronization signal is detected, and setting transmission and reception timings based on the timer.

A wireless communication system according to the present invention is a wireless communication system comprising a plurality of wireless communication terminals for performing data communication and a wireless communication control terminal for controlling wireless communication. , Send and receive data OF
The wireless communication terminal includes a transmitting unit and a receiving unit that perform the DM method, and a synchronizing signal generating unit that OFDM modulates the code sequence for synchronizing detection and generates a synchronizing signal using a predetermined partial signal of the modulated signal. A transmission unit and a reception unit for transmitting and receiving data in an OFDM system; a synchronization detection unit for detecting a synchronization signal; and a timer unit set by the synchronization detection unit. Between each of the control terminals, the data is modulated by the OFDM system, and the data is multiplexed by the TDMA system in a frame structure of a predetermined number of symbols. The synchronization signal transmitting means for transmitting the synchronization signal to the wireless communication terminals, and each of the wireless communication terminals according to a timing at which the synchronization signal is detected by the synchronization detection means Set the serial timer, and a communication control means for setting a transmission and reception timing based on the above timer.

In the present invention, preferably, the synchronizing signal generating means generates the synchronizing signal using data of a real part of the OFDM modulated signal. Further, the synchronization signal generating means generates the synchronization signal using data of an imaginary part of the OFDM modulated signal.

In the present invention, preferably, the synchronization signal transmitting means transmits the synchronization signal at least twice.
Among them, the first and / or last synchronization signal is a signal obtained by rotating the generated synchronization signal by 180 degrees.

Further, in the present invention, preferably, the synchronization detecting means performs a correlation operation between a real part and an imaginary part of the received signal with predetermined synchronization detection pattern data, respectively, and calculates a correlation between the real part and the imaginary part. A correlation operation circuit for calculating a value, an absolute value operation circuit for calculating an absolute value based on the correlation value of the real part and the imaginary part, and comparing the absolute value with a predetermined threshold value. And a comparator for outputting a synchronization detection signal indicating the detection timing of the synchronization signal.

[0017]

FIG. 1 is a circuit diagram showing a first embodiment of a wireless communication system according to the present invention. FIG. 1 illustrates a wireless communication system including wireless communication terminals 101A and 101B and a wireless communication control terminal 102. As shown, the wireless communication terminals 101A and 101A
1B is data terminals 103A and 103 such as computers.
B is connected to the wireless communication units 104A and 104B, respectively. The wireless communication control terminal 102
The wireless communication unit 105 is connected to the data terminal 106. Plurality of wireless communication terminals 101A, 101B
And data communication between the wireless communication terminals 101A and 101B is controlled by the wireless communication control terminal 102. Note that the wireless communication control terminal 102
The wireless communication unit 105 alone can be used.

The wireless communication units 104A and 104B on the wireless communication terminals 101A and 101B respectively
1A and 111B, receiving units 112A and 112B, and control units 113A and 113B. Transmission units 111A, 111
B and the receiving units 112A and 112B are configured to wirelessly transmit information data modulated by the OFDM modulation method.

The wireless communication unit 105 on the side of the wireless communication control terminal 102 includes a transmitting unit 115, a receiving unit 116,
17 The transmitting unit 115 and the receiving unit 116
The data communication can be performed wirelessly by the DM modulation method. Further, the wireless communication unit 105 on the side of the wireless communication control terminal 102 is provided with a resource information memory 118 for storing resource information relating to the allocated time of data communication of the wireless communication terminal.

In this system, data communication is based on OFDM.
This is performed by a modulation method. And, for example, 147 of OFDM
One frame includes 455 symbols (corresponding to about 4 ms), and data is transmitted in this frame by the TDMA method.

At the beginning of one frame, a synchronization signal for acquiring synchronization is transmitted from the wireless communication unit 105 of the wireless communication control terminal 102. The code of this synchronization signal is used for each wireless communication terminal 101A, 101B wireless communication unit 104A,
The transmission / reception timing is set on the basis of the reception timing of the synchronization signal.

When there is a data communication request from the wireless communication terminals 101A and 101B, the wireless communication terminals 101A and 101B
From the wireless communication units 104A and 104B of 101B,
A transmission request is sent to the wireless communication unit 105 of the communication control terminal 102. In the wireless communication unit 105 of the wireless communication control terminal 102, the transmission allocation time of each of the wireless communication terminals 101A and 101B is determined based on the transmission request and the resource information, and the control information including the transmission allocation time is transmitted to the wireless communication control terminal. The wireless communication unit 105 of each wireless communication terminal 101A, 101B from the wireless communication unit 105 of 102
04A and 104B. Each wireless communication terminal 101
A, 101B wireless communication units 104A, 104B
Then, data transmission / reception is performed according to the transmission allocation time. At this time, the data transmission / reception timing
It is set on the basis of a synchronization signal for synchronization acquisition sent at the beginning of one frame.

FIG. 2 shows the configuration of the wireless communication unit 105 on the wireless communication control terminal 102 side. In FIG. 2, reference numeral 11 denotes a communication controller through which data is exchanged with a data terminal.

The transmission data from the communication controller 11 is a differentially encoded quadrature (DQPSK).
(Phase Shift Keying) modulation circuit 12. DQ
The PSK modulation circuit 12 modulates transmission data with DQPSK.

The output of the DQPSK modulation circuit 12 is serial
/ It is supplied to the parallel conversion circuit 13. The serial / parallel conversion circuit 13 converts the serial data into parallel data. The output of the serial / parallel conversion circuit 13 is an IFFT (Inverse Fast Fourier Transform) circuit 1
4 is supplied. The transmission data is mapped to data in the frequency domain by the IFFT circuit 14, and this is subjected to an inverse Fourier transform to be converted to data in the time domain. IFF
The output of the T circuit 14 is supplied to a parallel / serial conversion circuit 15.

Serial / parallel conversion circuit 13, IFF
The T circuit 14 and the parallel / serial conversion circuit 15
It is converted into a multi-carrier signal by the DM method. The OFDM system uses a plurality of subcarriers in which each carrier is orthogonalized by setting the frequency interval to f0 so that there is no intersymbol interference, assigns a low bit rate signal to each subcarrier, and increases the overall high bit rate. It is intended to be obtained.

FIG. 3 shows a spectrum of a transmission waveform of the OFDM system. As shown in FIG.
In the method, using the sub-carrier frequency interval f ₀ which are orthogonal to each other, a signal is transmitted.

In the OFDM system, a modulated signal is generated by mapping transmission data in the frequency domain and performing inverse FFT.
By converting from the frequency domain to the time domain. Conversely, decoding is performed by taking in a waveform received at intervals of f ₀ and converting a signal in the time domain into a signal in the frequency domain by FFT.

In this example, as shown in FIG.
/ DQPSK modulation circuit 1 by the parallel conversion circuit 13
51 samples of the output of 2 are converted into parallel data,
Maps to the frequency domain. The output of the serial / parallel conversion circuit 13 is converted into data in the time domain by the IFFT circuit 14, and is output from the IFFT circuit 14 to
Four samples of effective symbols are output. A guard interval of 8 symbols is added to the effective symbols of 64 samples by a parallel / serial conversion circuit 15 constituted by a shift register.

Therefore, in this example, as shown in FIG.
One symbol which is one transmission unit of the OFDM modulation signal has 6 symbols.
It consists of 4 samples of valid symbols and 72 samples of an 8 sample guard interval. Symbol period Tsymb
ol is, for example, (Tsymbol = 1.953 μsec), and the sample period Tsample is, for example, (Tsample = 27.12)
7 nsec), and the sample frequency fsample is, for example, (fsample = 36.864 MHz).

In the OFDM system, data is transmitted by being distributed to a plurality of subcarriers, so that the time per symbol becomes longer. Since the guard interval is provided on the time axis, it has a feature that it is hardly affected by jitter and multipath. Note that the guard interval is selected to be about 1 to 20% of the effective symbol length.

That is, in the OFDM system, the FF
At the time of T, it is necessary to cut out the effective symbol length from the continuous reception signal and perform FFT. Even if there is such an error in extracting an effective symbol due to jitter or the like, since the guard interval exists, the frequency component does not change and only the phase difference occurs. For this reason, it is possible to perform demodulation by inserting a known pattern into the signal to perform phase correction, or by canceling the phase difference using differential coding. In the case of only normal QPSK modulation, it is necessary to match the timing for each bit. In the case of the OFDM system,
Demodulation is possible even if the bit is shifted by several bits, only by deteriorating the sensitivity by several dB.

FIG. 6 shows an example in which a known pattern is inserted into a transmission signal for phase correction. As shown in the drawing, four subcarriers out of a total of 52 subcarriers are subjected to BPSK modulation using known data.
The other 48 subcarriers are used for data transmission, and are modulated and transmitted according to transmission data, for example, by the QPSK modulation method or the 16QAM modulation method.
The four subcarriers inserted in a known pattern are called pilot carriers, while the other carriers modulated according to the transmission data are called data carriers. FIG. 7 shows an arrangement of signal points of a data carrier and a pilot carrier. On the receiving side, a pilot carrier is received, phase correction is performed on other data carriers according to the phase of the pilot carrier, and occurrence of a demodulation error is suppressed.

In FIG. 2, the output of the parallel / serial conversion circuit 15 is supplied to a terminal 16 A of a switch circuit 16. A synchronization signal composed of a predetermined OFDM modulation signal generated by the synchronization signal generation circuit 31 is supplied to a terminal 16B of the switch circuit 16.

The output of the switch circuit 16 is supplied to the frequency conversion circuit 17. A local oscillation signal is supplied from the PLL synthesizer 18 to the frequency conversion circuit 17. The transmission signal is converted to a predetermined frequency by the frequency conversion circuit 17. The transmission frequency is, for example, 2.4 GHz, 5.2 GHz, 5.8 GHz, 19 GHz in the quasi-microwave band.
It is conceivable to use the z, 24 GHz and 60 GHz bands.

The output of the frequency conversion circuit 17 is supplied to a power amplifier 19. The transmission signal is power-amplified by the power amplifier 19. The output of the power amplifier 19 is supplied to a terminal 20A of the switch circuit 20. The switch circuit 20
Switching is performed between transmission and reception. During data transmission, the switch circuit 20 is switched to the terminal 20A side. The output of the switch circuit 20 is supplied to the antenna 21.

The received signal from the antenna 21 is supplied to the switch circuit 20. At the time of data reception, the switch circuit 20 is switched to the terminal 20B side. The output of the switch circuit 20 is an LNA (Low Noise Amplifier) 22
, And then supplied to the frequency conversion circuit 23.

A local oscillation signal is supplied from the PLL synthesizer 18 to the frequency conversion circuit 23. The frequency conversion circuit 23 converts the received signal into an intermediate frequency signal.

The output of the frequency conversion circuit 23 is supplied to a serial / parallel conversion circuit 24. The output of the serial / parallel conversion circuit 24 is supplied to the FFT circuit 25. The output of the FFT circuit 25 is supplied to a parallel / serial conversion circuit 26.

Serial / parallel conversion circuit 24, FFT
Circuit 25, parallel / serial conversion circuit 26, OFD
This is to perform M-method decoding. In other words, the serial / parallel conversion circuit 24, effective data is cut out, the reception waveform is captured every f ₀ intervals is converted into parallel data. The output of the serial / parallel conversion circuit 24 is supplied to an FFT circuit 25, which converts a signal in a time domain into a signal in a frequency domain. Thus, by FFT the sampled waveform every f ₀ intervals, decoding the OFDM method is performed.

The output of the parallel / serial conversion circuit 26 is supplied to a DQPSK demodulation circuit 27. The DQPSK demodulation circuit 27 performs a DQPSK demodulation process. DQP
The output of the SK demodulation circuit 27 is supplied to the communication controller 11. Received data is output from the output of the communication controller 11.

The whole operation of the wireless communication unit 105 is as follows.
It is controlled by the controller 28. Transmission and reception of data are controlled by the communication controller 11 based on a command from the controller 28.

In this radio communication system, data is transmitted in units of one frame by the TDMA system, and a synchronization signal is transmitted to the first symbol of one frame. In order to realize such control, the wireless communication unit 105 of the wireless communication control terminal 102 includes a synchronization signal generation circuit 31, a resource information memory 30, a timer 29
Are provided. At the timing of the first symbol of one frame, the switch circuit 16 is switched to the terminal 16B. As a result, the synchronization signal of one symbol is transmitted at the timing of the head of the frame.

When transmission requests are sent from the wireless communication units 104A and 104B of each of the wireless communication terminals 101A and 101B, the transmission requests are received by the antenna 21 and the FFT is performed.
The OFDM demodulation is performed by the circuit 25, the DQPSK demodulation is performed by the DQPSK demodulation circuit 27, and the DQPSK is supplied to the communication controller 11. Then, the demodulated received data is sent from the communication controller 11 to the controller 28.

The controller 28 has a resource information memory 3
0 is provided. This resource information memory 30 has 1
Each wireless communication terminal 101A, 101B sent in a frame
Is stored. The controller 28 determines the transmission allocation time of each of the wireless communication terminals 101A and 101B based on the received transmission request and the remaining communication resources. The control information for this transmission assignment is sent from the controller 28 to the communication controller 11. The data from the communication controller 11 is DQPSK-modulated by the DQPSK modulation circuit 12,
The conversion by OFDM is performed in the FFT circuit 14, and the signal is transmitted from the antenna 21 to the wireless communication units 104A and 104B of the wireless communication terminals 101A and 101B.

FIG. 8 shows wireless communication terminals 101A and 101B.
1 shows a configuration of the wireless communication units 104A and 104B. In FIG. 8, transmission data is input via a communication controller 51. Communication controller 51
Is supplied to the DQPSK modulation circuit 52. The DQPSK modulation circuit 52 converts the transmission data to D
Modulated with QPSK.

The output of the DQPSK modulation circuit 52 is serial
/ It is supplied to the parallel conversion circuit 53. The serial / parallel conversion circuit 53 converts the serial data into parallel data. The output of the serial / parallel conversion circuit 53 is supplied to the IFFT circuit 54. The transmission data is mapped by the IFFT circuit 54 to data in the frequency domain, which is subjected to inverse Fourier transform, and is converted into data in the time domain. The output of the IFFT circuit 54 is supplied to a parallel / serial conversion circuit 55. The serial / parallel conversion circuit 53, the IFFT circuit 54, and the parallel / serial conversion circuit 55 convert the signals into multicarrier signals by the OFDM method.

The output of the parallel / serial conversion circuit 55 is supplied to the frequency conversion circuit 57. Frequency conversion circuit 57
Is supplied with a local oscillation signal from the PLL synthesizer 58. The transmission signal is converted to a predetermined frequency by the frequency conversion circuit 57.

The output of the frequency conversion circuit 57 is supplied to a power amplifier 59. The transmission signal is power-amplified by the power amplifier 59. The output of the power amplifier 59 is supplied to a terminal 60A of the switch circuit 60. At the time of data transmission, the switch circuit 60 is switched to the terminal 60A side. The output of the switch circuit 60 is supplied to the antenna 61.

The received signal from the antenna 61 is supplied to the switch circuit 60. At the time of data reception, the switch circuit 60 is switched to the terminal 60B side. The output of the switch circuit 60 is supplied to the frequency conversion circuit 63 after being amplified via the LNA 62.

A local oscillation signal is supplied from the PLL synthesizer 68 to the frequency conversion circuit 63. The frequency conversion circuit 63 converts the received signal into an intermediate frequency signal. The output of the frequency conversion circuit 63 is supplied to the serial / parallel conversion circuit 64 and also to the synchronization detection circuit 71.

The output of the serial / parallel conversion circuit 64 is supplied to the FFT circuit 65. The output of the FFT circuit 65 is supplied to a parallel / serial conversion circuit 66. Serial / parallel conversion circuit 64, FFT circuit 65, parallel /
The serial conversion circuit 66 performs OFDM demodulation.

The output of the parallel / serial conversion circuit 66 is supplied to a DQPSK demodulation circuit 67. The DQPSK demodulation circuit 67 performs a DQPSK demodulation process. DQP
The output of the SK demodulation circuit 67 is supplied to the communication controller 51. Received data is output from the output of the communication controller 51.

Radio communication unit 104A or 104B
Is controlled by the controller 68.
Data transmission and data reception are controlled by the communication controller 51 based on a command from the controller 68.

In this system, data is transmitted in units of one frame by the TDMA method, and a synchronization signal for acquiring synchronization is transmitted from the wireless communication unit 105 of the wireless communication control terminal 102 to the first symbol of one frame. Come. In order to realize such control, the wireless communication units 104A and 104B are provided with a synchronization detection circuit 71 for detecting a synchronization signal and a timer 72. At the beginning of the frame, the wireless communication control terminal 102
The synchronization signal sent from the wireless communication unit 105 is received by the antenna 61 and sent to the synchronization detection circuit 71. The synchronization detection circuit 71 detects a correlation between the received code and a preset code, and outputs a correlation detection signal when it is determined that the correlation is strong. Such a synchronization detection circuit 71 can be realized by, for example, a matched filter. The output of the synchronization detection circuit 71 is sent to the timer 72.
The time of the timer 72 is set based on a synchronization detection signal from the synchronization detection circuit 71.

If there is data to be sent, a transmission request is sent from the communication controller 51 in accordance with a command from the controller 68. This transmission request is DQPSK-modulated by the DQPSK modulation circuit 52, and
The signal is converted by FDM and sent from the antenna 61 to the wireless communication control terminal 102. This transmission request
The wireless communication control terminal 102 receives the control information, and the wireless communication control terminal 102 returns control information including the transmission allocation time.

This control information is received by the antenna 61, OFDM demodulation is performed by the FFT circuit 65, and the DQP
The SK demodulation circuit 67 demodulates DQPSK and supplies the demodulated signal to the communication controller 51. The demodulated received data is transmitted from the communication controller 51 to the controller 6.
8

The control information includes information on the transmission time. These times are set based on the time of the timer 72. The timer 72 includes the synchronization detection circuit 7
1 is set based on the timing of the synchronization signal sent from the wireless communication control terminal.

When it is determined by the timer 72 that the transmission start time has come, the command from the controller 68
Transmission data is output from the communication controller 51. The transmission data is DQPSK-modulated by the DQPSK modulation circuit 52, converted by OFDM by the IFFT circuit 54, and output from the antenna 61. When the timer 72 determines that the reception time has come, the controller 6
The demodulation process of the received data is performed by the FFT circuit 65 in accordance with the instruction from 8.

As described above, in this wireless communication system,
Data is transmitted using multicarrier by OFDM. As described above, the OFDM wave is resistant to jitter, and can be demodulated even if it is shifted by several samples. However, demodulation cannot be carried out if it shifts by two symbols and straddles two symbols. Therefore, it is necessary to set a certain amount of timing. Therefore, in this system, for example, 147455 symbols (4 ms) are defined as one frame, and data is transmitted in this frame by the TDMA method.
A synchronization signal is arranged in the first symbol of each frame, and the synchronization signal is used to set the demodulation timing.

If the received clock has a shift of 6.8 ppm (1 ppm is 1 / million) with respect to the received OFDM wave, a time difference of 27.2 nsec occurs in one frame of 4 msec. accumulate. This corresponds to a sampling rate of 36.864 MHz. Therefore, if a clock having an accuracy of about 6.8 ppm is prepared, demodulation can be performed reliably.

FIG. 9 shows the structure of one frame. As shown in FIG. 9, one frame is divided into a control data transmission time and an information data transmission time. During the control data transmission time, data communication is performed asynchronously, and during the information transmission time, data communication is performed isochronously (isochronously). A synchronization symbol composed of a synchronization signal is transmitted from the wireless communication control terminal 102, and each wireless communication terminal 101A,
101B transmits a transmission request to the wireless communication control terminal 102, and the wireless communication control terminal 102
Communication that sends control information including the transmission allocation time to A and 101B is performed by asynchronous communication during the control data transmission time. Then, according to the transmission allocation time, the data communication performed between the wireless communication terminals 101A and 101B is performed isochronously during the information transmission time.

Hereinafter, the operating principle of the synchronization signal generation circuit and the synchronization detection circuit in the communication terminal and the communication control terminal of the present embodiment will be described. The synchronization signal generation circuit is, for example, the synchronization signal generation circuit 31 included in the wireless communication unit 105 of the wireless communication control terminal 102 illustrated in FIG.
For example, the synchronization detection circuit 71 included in the wireless communication units 104A and 104B of the wireless communication terminals 101A and 101B shown in FIG.

FIG. 10 is a diagram showing a method of generating a synchronization signal of an OFDM wave. As shown in FIG.
The M-wave synchronization code is a predetermined code sequence, for example, a code sequence {x ₀ , x ₁ , x ₂ ,.
x ₆₃ }, a 64-point inverse Fourier transform (IF
FT). 64 data {y ₀ , y ₁ , y ₂ ,..., Y ₆₃ } generated by IFFT
Is transmitted at the beginning of each frame as a synchronization code sequence.

By the IFFT processing, a data sequence composed of 64 data is obtained as a real part and an imaginary part. If the real and imaginary data sequences are combined and transmitted as a synchronization signal at the beginning of each frame, the receiving side will need to perform a complex multiplication operation for synchronization detection, which complicates the configuration of the synchronization detection circuit. And there is a problem that the circuit scale becomes large. For this reason, in the present embodiment, one of the data series of the real part and the imaginary part generated by the IFFT processing is used as a synchronization signal. That is, as a result of the IFFT processing, the data sequence of the real part or the imaginary part is transmitted as a synchronization signal to the beginning of each frame. Accordingly, on the receiving side, synchronization detection can be performed on the received signal by normal correlation processing on real number data, and the circuit configuration is simple. For example, the circuit scale is substantially the same as that of a synchronization signal formed of a normal PN sequence. Enables synchronization detection.

As a method of generating the data sequence of the synchronization code,
In the 64 data sequences, a predetermined value is inserted every fourth data sequence, and all other data are held at “0”. That is, the data series {x ₀ , x ₁ , x ₂ ,..., X ₆₃ }
, Each of the data x ₀ , x ₄ , x ₈ ,..., X ₆₀ has a predetermined value, and the other data x ₁ , x ₂ , x
₃ , x ₅ ... Are all held at “0”.

FIG. 10 (b) shows the data sequence {x
_{0, x 1, x 2,} ..., with respect to x _63}, shows the results of IFFT. As shown, the data sequence {y ₀ , y ₁ , y ₂ ,..., Y ₆₃ } obtained by IFFT is a data sequence having four repetitive waveforms.

In the synchronization signal generating circuit 31 of the wireless communication unit 105 of the wireless communication control terminal 102 shown in FIG.
The data sequence {x ₀ , x ₁ , x ₂ ,..., X
₆₃ }, a data sequence {y ₀ , y ₁ , y ₂ ,..., Y ₆₃ } generated by IFFT is provided as a synchronization signal. Note that the synchronization signal generation circuit 31 outputs the data sequence {x
_{0, x 1, x 2,} ..., it is also possible to provide x _63}.
In this case, the data sequence {x ₀ , x ₁ , x ₂ ,..., X ₆₃ } output by the synchronization signal generation circuit 31 is input to the IFFT circuit 14 at a predetermined timing, and
4 to perform an inverse Fourier transform to obtain a data sequence {y ₀ ,
y ₁ , y ₂ ,..., y ₆₃ } are generated. Further, it is converted into a serial code sequence on the time axis by the parallel / serial conversion circuit 15 and transmitted as a synchronization signal to the beginning of the frame.

FIGS. 11, 12 and 13 are block diagrams showing some configuration examples of the OFDM modulation part and the transmission part circuit in the wireless communication unit 105 of the wireless communication control terminal 102. FIG. 11 shows a circuit configuration in a case where the synchronization code generated by the synchronization code generation circuit 31 is converted by the IFFT conversion circuit and transmitted. As shown, the information data sequence and the synchronization code sequence are
10 serial / parallel conversion circuit 1
The data is converted into parallel data by 13 and input to the IFFT circuit 114. As a result of the IFFT processing, a real part data series Re and an imaginary part data series Im are respectively generated.

The switch 116 selects the imaginary part data Im or data “0” and inputs it to the parallel / serial conversion circuit 115. The serial data output by the parallel / serial conversion circuit 115 is D /
Converted into an analog signal by the A converter 120,
Then, the signal is orthogonally modulated by the orthogonal modulation circuit 121, amplified by the transmission circuit 122, and transmitted by the antenna.

[0071] Switches 110 and 116, in response to the selection control signal S _W, selects an input signal. The selection control signal _SW is supplied, for example, by the controller 28 of the communication unit 105. When transmitting a synchronization signal to the beginning of each frame, a synchronization code sequence is selected by the switch 110 and the serial / parallel conversion circuit 113
And input to the IFFT circuit 114.
In this case, the synchronization code generated by the synchronization signal generation circuit 31 is, for example, a data sequence {x ₀ , x shown in FIG.
_1, x _2, ..., a x _63}. The data series is IFF
After the T processing, a real part and an imaginary part are respectively generated.

The data of the real part is input to the parallel / serial conversion circuit 115, and the data of the imaginary part is
6 are all replaced with data "0". That is, when transmitting a synchronization signal, only the data of the real part obtained by IFFT is transmitted, and the data of the imaginary part are all set to “0”.

After transmitting the synchronization signal, the information data is transmitted. In this case, the information data series is selected by the switch 110 and the serial / parallel conversion circuit 113
Is input to The switch 116 selects the imaginary part data Im output from the IFFT circuit 114,
Since the data is input to the parallel / serial conversion circuit 115 together with the real part data Re, the OFD corresponding to the information data is
An M-modulated signal is transmitted.

FIG. 12 shows a circuit configuration in the case where the synchronization code generated by the synchronization code generation circuit 31 is directly transmitted without performing IFFT conversion. As shown, the information data is transmitted through the serial / parallel conversion circuit 113 to the IF
The data is input to the FT circuit 114, and as a result of the IFFT processing, a real part data series Re and an imaginary part data series Im are respectively generated. Real part data series Re and imaginary part data series I
m is converted into serial data by the parallel / serial conversion circuit 115.

Either the output data of the parallel / serial conversion circuit 115 or the synchronization code generated by the synchronization signal generation circuit 31 is selected by the switches 130 and 132 and output to the D / A converter 120. When transmitting a synchronization signal to the beginning of a frame, the switch 13
0 selects a synchronization code, and the D / A converter 12
Input to 0. Further, data “0” is input to the D / A converter 120 by the switch 132. The data input from the switches 130 and 132 are converted into analog signals as the real part and the imaginary part of the transmission data, respectively, and further modulated by the quadrature modulation circuit 121 and transmitted. In this case, the synchronization code supplied by the synchronization signal generation circuit 31 is a data sequence that has been subjected to IFFT processing in advance, for example, a data sequence Δy shown in FIG.
_{0, y 1, y 2,} ..., a y _63}. That is, the synchronization code generated by the synchronization signal generation circuit 31 is a real part, and a synchronization signal is generated by a data sequence in which all the imaginary parts are set to data “0” and transmitted to the beginning of the frame.

After transmitting the synchronizing signal, information data is transmitted. In this case, the data series of the real part and the imaginary part output from the parallel / serial conversion circuit 115 are selected by the switches 130 and 132, respectively, and input to the D / A converter 120.
An FDM modulated signal is transmitted. The selection control signal S _W for selecting the switches 130 and 132, as in the example shown in FIG. 11, for example, supplied by the controller 28 of the wireless communication unit 105.

FIG. 13 shows a case where the synchronization code is input to the IFFT circuit 114 via the serial / parallel conversion circuit 113, and only the real part data of the real part data and the imaginary part data obtained from the IFFT circuit 114 is synchronized. 4 shows an example of forming a signal. However, in this example, unlike the circuit shown in FIG. 11, when forming a synchronization signal, the same data as the real part data is set without setting the imaginary part data to “0”.

In the data sequence constituting the synchronization code, a value is set every four bits, and all other data are set to “0”.
Energy is given to every four carriers. For this reason, the energy of the OFDM modulated wave of the synchronization signal is only about 1/4 that of a normal OFDM modulated signal. Further, when the circuit of FIG. 11 is used, only the real part data of the real part data and the imaginary part data obtained by the IFFT is used, and all the imaginary part data are replaced with “0”.
For this reason, the energy of the transmitted synchronization signal is only about 1/8 that of a normal OFDM modulated wave. On the receiving side, if the energy of the received synchronization signal is weak, the synchronization detection accuracy may be reduced.

In order to solve this, it is necessary for the transmitting side to increase the energy of the synchronization signal by eight times. That is, the amplitude of the synchronization signal may be multiplied by 2√2. To achieve this,
In the circuit example shown in FIG. 13, when transmitting a synchronization signal,
The real part data output by the IFFT circuit 114 is doubled, and the same data as the real part is set in the imaginary part. Accordingly, the amplitude of the synchronization signal orthogonally modulated by the orthogonal modulation circuit 121 is 2√2 times as compared with the case where only the real part of the output data of the IFFT circuit 114 is used, and the energy of the synchronization signal is reduced by the ordinary OFDM modulation. It is almost the same as the signal.

Although FIGS. 11, 12 and 13 show examples in which only the real part data of the output signal of the IFFT circuit 114 is used to generate a synchronization signal, the present invention is not limited to this. It is not a thing, for example, FIG.
Of the output data of the IFFT circuit 114,
All the data of the real part can be replaced with “0”, and only the data of the imaginary part can be output as it is to transmit the synchronization signal. In the circuit of FIG. 12, a synchronization signal can be transmitted based on a complex number in which data “0” is set in the real part and a synchronization code is set in the imaginary part. further,
In the case of FIG. 13, the imaginary part data output by the IFFT circuit 114 can be doubled to generate a synchronization signal.

Next, in the wireless communication unit 105,
A specific configuration example of the synchronization signal generation circuit 31 will be described. FIG. 14 illustrates an example of a synchronization signal generation circuit configured by the shift register 211. Here, for example, 6
A synchronization signal is generated by the 4-word shift register 211. FIG. 15 is a waveform chart showing the operation when the synchronization signal is generated.

As shown in FIG. 15, the shift register 21
1 is supplied with a clock signal CK. In response to the rising edge of the load signal LD, 64-word data is loaded into the shift register 211, and 8-bit code data is sequentially output according to the rising edge of the clock signal CK. Since the load signal LD is controlled, for example, in accordance with the start timing of each frame, the code sequence output by the shift register 211 is output to the circuit shown in FIG.
Sent at the beginning of each frame.

FIG. 16 shows the ROM 211 and the counter 22.
2 shows an example of a synchronization signal generation circuit constituted by 2. Data for forming a synchronization signal is stored in the ROM 221 in advance in the order of addresses. When outputting the synchronization signal, the data stored at the address generated by the counter 222 is read. Note that RO
The capacity of M221 requires at least the number of data series to be stored. For example, when storing 64 words of data, a minimum capacity of 64 words is required. Also,
As described above, only one-fourth of the data sequence that forms the synchronization signal is substantially meaningful. Therefore, the ROM 221 only needs to have a capacity enough to store only necessary data.

FIG. 17 shows waveforms during the operation of the synchronization signal generating circuit shown in FIG. The clock signal CK is supplied to the counter 222. In response to the load signal LD, the counter 222 is reset, the counting operation starts,
For example, the count value of the counter 222 increases by +1 according to the input timing of the clock signal CK. The count value is input to the ROM 221 as an address. RO
M221 reads and outputs the storage data at the memory address specified by the input address. Thus, for example, data is output from the ROM 221 in units of 8 bits according to the timing of the clock signal CK. This output data is output as a synchronization code to the circuit shown in FIG. 11, 12 or 13 as a synchronization code, and is transmitted to the head of each frame.

FIG. 18 shows a communication terminal 1 according to this embodiment.
01A, 101B wireless communication unit 104A or 1
FIG. 4 is a block diagram showing a configuration of a synchronization detection circuit 71 of FIG. This synchronization detection circuit uses a synchronization detection pattern data set in advance to calculate a correlation with a received signal.
A synchronization signal transmitted at the head of each frame is detected, and a synchronization detection signal _Sor is output. The sync detection signal S _or is a reference time of the timer in the wireless communication unit 104A or 104B.

The synchronization detection circuit shown in FIG. 18 is composed of shift registers 200 and 204, addition circuits 202 and 206, an absolute value calculation circuit 208, and a comparison circuit 210. The data of the real part and the imaginary part of the received signal output from the receiving circuit are input to the shift registers 200 and 204, respectively. These received data are sequentially shifted by the respective shift registers, and the data of each register is respectively subjected to coefficients h _n−1 , h by a plurality of multipliers.
_n-2, ..., is multiplied by h _1, h _0, the result of the multiplication is input to adder circuits 202 and 206.

The multiplier coefficients h _n−1 , h _n−2 ,..., H ₁ ,
h ₀ is set according to the synchronization detection pattern data.
For example, each coefficient is “−1”, “0” of data.
Or, it is constituted by “+1”.

The correlation values of the real part and the imaginary part are output by the adders 202 and 206, respectively.
08 and the absolute value _Cor is calculated. Absolute value C _or
There are compared by the comparison circuit 210 with a predetermined threshold value TH, according to the result of the comparison, for example, the absolute value C _or is when exceeding the threshold value TH, the synchronization detection signal S _sync is output.

As described above, in the radio communication system, the synchronization signal is transmitted at the head of the frame by the transmission side. The receiving side detects a synchronization signal from the received signal based on a synchronization detection pattern obtained in advance. The detection pattern is, for example, a data sequence {h ₀ , h ₁ , h ₂ ,..., H _n-1 } composed of n pieces of data based on a synchronization code for generating a synchronization signal. The multiplier coefficient is set according to the synchronization detection pattern.

By the above-described synchronization detection circuit, a so-called matched filter process for obtaining the correlation between the received signal and the synchronization detection pattern is performed. Correlation processing result, when it exceeds the threshold value TH by the correlation function C _or preset, as a synchronizing signal is detected, the synchronization detection signal S _sync is output. The receiving device controls the timer according to the timing of the synchronization detection signal _Ssync . Each communication terminal transmits and receives signals at a timing controlled by a timer. For example, FFT by a timer at the time of reception
A window is set, and the FFT window
FT processing is performed, and the received signal is OFDM demodulated.

Each data of the data series {h ₀ , h ₁ , h ₂ ,..., H _n-1 } forming the synchronization detection pattern is
For example, it is constituted by +1, 0 or -1.
Here, for example, assuming that each data is composed of either +1 or -1, the configuration of the synchronization detection circuit for obtaining the correlation function can be further simplified.

FIG. 19 shows a configuration example of the synchronization detection circuit in this case. As shown, according to each data h _i (i = 0, 1, 2,..., N−1) of the synchronization pattern,
When h _i is "-1" is multiplied by -1 to the corresponding input data, when the h _i is "+1", the corresponding data is directly input to the adder circuit 202 or 206, the adder circuit 20
The correlation value between the real part and the imaginary number is calculated by 2 or 206, respectively. The absolute value calculation circuit 208 calculates the absolute value, and outputs a synchronization detection signal _or according to the result of comparison with the threshold value TH. In the synchronization detection circuit of this example, the calculation for obtaining the correlation function can be easily realized, and the synchronization detection circuit can be constituted by a simple logic circuit.

FIGS. 20 and 21 show an improved example for improving the synchronization detection accuracy. As shown in FIG. 20, the synchronization signal SYNC is continuously transmitted twice at the beginning of the frame. On the receiving side, a correlation operation is performed on the received signal using the synchronization detection pattern, and as a result, a synchronization detection signal is output for each synchronization signal SYNC. Therefore, as compared with the case where only one synchronization signal is used, synchronization detection can be performed more reliably, and the reliability of synchronization detection is improved.

FIG. 21 shows an improved example for further improving the synchronization detection accuracy. In this example, the synchronization signal is output three times at the beginning of the frame. FIG. 3A shows an example in which the same synchronization signal SYNC is output three times in succession. In this case, on the receiving side, a correlation operation with the received signal is performed according to a preset synchronization detection pattern, and as a result, the synchronization detection signal is output three times, so that the reliability of the synchronization detection is further improved.

FIG. 21 (b) shows that among the three synchronization signals,
The first two are SYNC, and the third is an inverted signal -SYNC of SYNC (a signal obtained by rotating the synchronization signal SYNC by 180 degrees). Further, FIG. 21C shows that among the three synchronization signals, the first synchronization signal is a synchronization signal −SYNC rotated by 180 degrees in phase, and the other two synchronization signals are SYNC.
It is as it is. In this way, three synchronization signals are formed in the same pattern, and one of them has a phase of 180.
By using the synchronization signal rotated by degrees, the receiving side performs correlation processing using the synchronization detection pattern,
Since the number of synchronization signals detected among the three synchronization signals can be determined based on the result of the correlation operation, the reliability of synchronization detection is improved, and the timer can be controlled with high accuracy in accordance with the detection timing. .

[0096]

As described above, according to the radio communication system and the synchronization signal detecting circuit of the present invention, data is transmitted by the OFDM method and TDMA is transmitted in units of one frame.
To perform data communication. Then, a synchronization signal of the OFDM wave is transmitted to the head of each frame. By forming a synchronization signal using either the real part or the imaginary part of the code sequence OFDM-modulated for the synchronization code,
On the receiving side, there is an advantage that the synchronization signal can be detected only by the real number correlation calculation process, the synchronization detection circuit can be simplified, the synchronization signal can be detected by a small-scale circuit, and the transmission / reception timing can be controlled with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of a wireless communication system according to the present invention, and is a block diagram illustrating a configuration of an entire wireless communication system.

FIG. 2 is a block diagram illustrating an example of a wireless communication unit of a communication control terminal in a wireless communication system to which the present invention is applied.

FIG. 3 is a spectrum diagram for explaining an OFDM modulation scheme.

FIG. 4 is a block diagram illustrating OFDM modulation in a wireless communication system to which the present invention is applied.

FIG. 5 is a configuration diagram of a symbol of an OFDM modulated signal in a wireless communication system to which the present invention is applied.

FIG. 6 is a diagram showing an arrangement of subcarriers when a pilot carrier for phase correction is inserted.

FIG. 7 is a diagram showing a signal point arrangement of data carriers and pilots.

FIG. 8 is a block diagram illustrating an example of a wireless communication unit of a communication terminal in a wireless communication system to which the present invention is applied.

FIG. 9 is a diagram for explaining a frame configuration of a wireless communication system to which the present invention is applied.

FIG. 10 shows an OF used in the wireless communication system of the present invention.
FIG. 3 is a diagram for explaining a method of generating a DM wave synchronization signal.

FIG. 11 is a circuit diagram illustrating an example of a partial circuit that transmits a synchronization signal and information data in a wireless communication unit of the communication control terminal.

FIG. 12 is a circuit diagram illustrating another example of a partial circuit that transmits a synchronization signal and information data in a wireless communication unit of a communication control terminal.

FIG. 13 is a circuit diagram illustrating a partial circuit that transmits a synchronization signal and information data in a wireless communication unit of the communication control terminal, and that prevents a decrease in transmission energy of the synchronization signal.

FIG. 14 is a circuit diagram illustrating an example of a synchronization signal generation circuit.

15 is a waveform diagram during operation of the synchronization signal generation circuit shown in FIG.

FIG. 16 is a circuit diagram showing another example of the synchronization signal generation circuit.

17 is a waveform chart at the time of operation of the synchronization signal generation circuit shown in FIG.

FIG. 18 is a block diagram illustrating a configuration of a synchronization signal detection circuit.

FIG. 19 is a block diagram illustrating another configuration example of the synchronization signal detection circuit.

FIG. 20 is a diagram illustrating a method for improving synchronization detection accuracy.

FIG. 21 is a diagram showing another method for improving the synchronization detection accuracy.

[Explanation of symbols]

14, 54 ... IFFT circuit, 31 ... synchronization signal generation circuit,
71: synchronization detection circuit, 101, 101B: wireless communication terminal, 102: wireless communication control terminal, 104A, 104B,
105: wireless communication unit, 211: shift register,
221 ROM, 222 counter.

Claims (21)

[Claims] 1. A wireless communication system comprising: a wireless communication terminal; and a wireless communication control terminal for controlling the wireless communication terminal, wherein the wireless communication control terminal transmits and receives data by an OFDM method, Means for OFDM-modulating a code sequence for synchronization detection, and a synchronization signal generating means for generating a synchronization signal using a predetermined partial signal of the modulated signal, wherein the wireless communication terminal transmits and receives data by an OFDM method. Transmitting means and receiving means, a synchronous detecting means for detecting a synchronous signal, and a timer means set by the synchronous detecting means.
The wireless communication control terminal modulates data by the FDM method and multiplexes the data by the TDMA method in a frame structure of a predetermined number of symbols. The wireless communication control terminal transmits the synchronization signal to the wireless communication terminal for each frame. Means, and the wireless communication terminal comprises: a communication controller configured to set the timer in accordance with a timing at which the synchronization signal is detected by the synchronization detector, and to set transmission and reception timings based on the timer. system. 2. The radio communication system according to claim 1, wherein said synchronization signal generating means generates said synchronization signal using data of a real part of said OFDM modulated signal. 3. The wireless communication system according to claim 1, wherein said synchronization signal generating means generates said synchronization signal using data of an imaginary part of said OFDM modulated signal. 4. The wireless communication system according to claim 1, wherein said synchronization signal transmitting means transmits said synchronization signal at least twice. 5. The synchronizing signal transmitting means transmits the synchronizing signal at least twice, and the first and / or last synchronizing signal is obtained by rotating the synchronizing signal generated by the synchronizing signal generating means by 180 degrees. Claim 1 which is a signal
A wireless communication system as described. 6. The synchronizing signal generating means, when generating the synchronizing signal, performs modulation by setting data every m (m is a natural number, m> 1) out of a plurality of subcarriers. 2. The wireless communication system according to 1. 7. The synchronization detecting means includes a correlation operation circuit for performing a correlation operation between a real part and an imaginary part of the received signal with predetermined synchronization detection pattern data and calculating a correlation value between the real part and the imaginary part. The wireless communication system according to claim 1, comprising: 8. The synchronization detecting means, comprising: an absolute value calculating circuit for calculating an absolute value based on a correlation value between the real part and the imaginary part; and comparing the absolute value with a predetermined threshold value. The wireless communication system according to claim 7, further comprising: a comparison circuit that outputs a synchronization detection signal indicating a detection timing of the synchronization signal according to a result. 9. A plurality of wireless communication terminals for performing data communication,
What is claimed is: 1. A wireless communication system, comprising: a wireless communication control terminal for controlling wireless communication, wherein the wireless communication control terminal transmits and receives data by an OFDM method, and a OFDM modulation code sequence for synchronization detection. And a synchronizing signal generating means for generating a synchronizing signal using a predetermined partial signal of the modulated signal, wherein the wireless communication terminal transmits and receives data by the OFDM method, and a synchronizing signal. And a timer means set by the synchronization detection means for detecting the data. Between each of the plurality of wireless communication terminals and the wireless communication control terminal, data is modulated by an OFDM method and a predetermined number of symbols are transmitted. The wireless communication control terminal performs multiplexing of data by the TDMA method with the frame structure of Synchronizing signal transmitting means for transmitting a signal, and each of the wireless communication terminals sets the timer in accordance with the timing at which the synchronizing signal is detected by the synchronizing detecting means, and sets transmission and receiving timings based on the timer. A wireless communication system having communication control means. 10. The OFDM synchronization signal generating means according to claim 1, wherein:
10. The wireless communication system according to claim 9, wherein the synchronization signal is generated using data of a real part of the modulated signal. 11. The OFDM synchronizing signal generating means according to claim 1,
10. The radio communication system according to claim 9, wherein the synchronization signal is generated using data of an imaginary part of the modulated signal. 12. The radio communication system according to claim 9, wherein said synchronization signal transmitting means transmits said synchronization signal at least twice. 13. The synchronizing signal transmitting means transmits the synchronizing signal at least twice, and the first and / or last synchronizing signal is obtained by rotating the synchronizing signal generated by the synchronizing signal generating means by 180 degrees. The wireless communication system according to claim 9, which is a signal. 14. The synchronizing signal generating means, when generating the synchronizing signal, performs modulation by setting data every m (m is a natural number, m> 1) out of a plurality of subcarriers. 10. The wireless communication system according to 9. 15. The synchronization detecting means includes a correlation operation circuit for performing a correlation operation between a real part and an imaginary part of a received signal with predetermined synchronization detection pattern data and calculating a correlation value between the real part and the imaginary part. The wireless communication system according to claim 9, comprising: 16. The synchronization detecting means compares an absolute value with a predetermined threshold value, based on a correlation value between the real part and the imaginary part, and compares the absolute value with a predetermined threshold value. The wireless communication system according to claim 15, further comprising: a comparison circuit that outputs a synchronization detection signal indicating a detection timing of the synchronization signal according to a result. 17. Each subcarrier of the OFDM system is D
The wireless communication system according to claim 9, wherein mapping processing is performed by a QPSK modulation scheme. 18. Each subcarrier of the OFDM system is Q
The wireless communication system according to claim 9, wherein mapping processing is performed by an AM modulation method. 19. Each of the subcarriers in the OFDM system is Q
The wireless communication system according to claim 9, wherein mapping processing is performed by a PSK modulation method. 20. Each subcarrier of the OFDM system is B
10. The wireless communication system according to claim 9, wherein mapping processing is performed using a combination of a PSK modulation scheme and a QPSK modulation scheme. 21. Each subcarrier of the OFDM system is B
The wireless communication system according to claim 9, wherein the mapping process is performed by a combination of the PSK modulation method and the QAM modulation method.