JP2001148489A - Manufacturing method for compound semiconductor solar battery - Google Patents

Manufacturing method for compound semiconductor solar battery

Info

Publication number
JP2001148489A
JP2001148489A JP36703999A JP36703999A JP2001148489A JP 2001148489 A JP2001148489 A JP 2001148489A JP 36703999 A JP36703999 A JP 36703999A JP 36703999 A JP36703999 A JP 36703999A JP 2001148489 A JP2001148489 A JP 2001148489A
Authority
JP
Japan
Prior art keywords
layer
type semiconductor
semiconductor layer
indium
solar cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP36703999A
Other languages
Japanese (ja)
Other versions
JP3777280B2 (en
Inventor
Kenji Takeuchi
健司 竹内
Yoshio Konuma
良雄 小沼
Sumihiro Ichikawa
純廣 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP36703999A priority Critical patent/JP3777280B2/en
Priority to US09/535,246 priority patent/US6307148B1/en
Priority to EP00302565A priority patent/EP1041645A3/en
Publication of JP2001148489A publication Critical patent/JP2001148489A/en
Application granted granted Critical
Publication of JP3777280B2 publication Critical patent/JP3777280B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/541CuInSe2 material PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a compound semiconductor solar battery for improving crystallinity in a p-type semiconductor layer in manufacturing the compound semiconductor solar battery of pn-junction, which is provided with the p-type semiconductor layer that is mainly formed of copper (Cu) and indium (In). SOLUTION: A metallic film where an indium layer 13 and a copper layer 15 are laminated is formed on a molybdenum layer 12 as an electrode film formed on one side of a glass substrate 10. A solfuration processing is executed on the metallic film and a p-type semiconductor layer 14 formed of CUInS2 is formed. Then, the p-type semiconductor layer 14 is cleaned by KCN solution and a KCN processing for removing the impurity of copper sulfide is executed. An n-type semiconductor layer 16 is formed on the p-type semiconductor layer 14. In manufacturing a compound semiconductor solar battery, the indium layer 13 is formed by evaporation while it is heated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は化合物半導体太陽電
池の製造方法に関し、更に詳細にはpn接合の化合物半
導体太陽電池の製造方法に関する。
The present invention relates to a method of manufacturing a compound semiconductor solar cell, and more particularly, to a method of manufacturing a pn junction compound semiconductor solar cell.

【0002】[0002]

【従来の技術】図4に示すpn接合の光吸収層を有する
化合物半導体太陽電池がある。図4において、図4
(a)は化合物半導体太陽電池の正面図であり、図4
(b)は化合物半導体太陽電池の縦断面図である。この
化合物半導体太陽電池(以下、単に太陽電池と称するこ
とがある)は、ガラス基板100上に電極膜としてモリ
ブデン層102が形成されている。このモリブデン層1
02上には、p型半導体層104とn型半導体層106
とが順次積層されて形成されており、n型半導体層10
6上に透明電極108が形成されている。更に、透明電
極108上には櫛形電極110が形成されている。この
櫛形電極110は、図4(a)に示す様に、電極が枝別
れ状(櫛形状)に形成されているものである。
2. Description of the Related Art There is a compound semiconductor solar cell having a pn junction light absorbing layer shown in FIG. In FIG.
(A) is a front view of the compound semiconductor solar cell, and FIG.
(B) is a longitudinal sectional view of the compound semiconductor solar cell. In this compound semiconductor solar cell (hereinafter sometimes simply referred to as a solar cell), a molybdenum layer 102 is formed on a glass substrate 100 as an electrode film. This molybdenum layer 1
02, a p-type semiconductor layer 104 and an n-type semiconductor layer 106
Are sequentially laminated, and the n-type semiconductor layer 10 is formed.
A transparent electrode 108 is formed on 6. Further, a comb electrode 110 is formed on the transparent electrode 108. As shown in FIG. 4A, the comb-shaped electrode 110 has electrodes formed in a branched shape (comb shape).

【0003】かかる図4に示す太陽電池は、図5に示す
方法で製造できる。先ず、ガラス基板100の一面側
に、モリブデン層102から成る電極膜を蒸着又はスパ
ッタリングで形成した後、インジウム層103を室温下
での蒸着によって形成し、更にインジウム層103上に
銅層105を室温下での蒸着によって形成する〔図5
(a)の工程〕。このインジウム層103と銅層105
とから成る金属膜を、硫化水素雰囲気中で加熱処理する
硫化処理を施してCuInS2のp型半導体層104と
した後、p型半導体層104に生成された硫化物(Cu
xY)等の不純物を取り除きp型半導体層104の特性
を適正化して安定した特性とすべく、KCNが5〜10
重量%含有されたKCN溶液によってp型半導体層10
4の表面を洗浄するKCN処理を施す〔図5(b)の工
程〕。更に、p型半導体層104上には、化学的溶液析
出法によりn型半導体層106を形成し〔図5(c)の
工程〕、更にn型半導体層106上にスパッタリングに
よりZnO:Al又はIn23から成る透明電極108
を形成する〔図5(d)の工程〕。その後、透明電極1
08上に、アルミニウムから成る櫛形電極110を形成
することによって、図4に示す太陽電池を得ることがで
きる。
The solar cell shown in FIG. 4 can be manufactured by a method shown in FIG. First, an electrode film made of a molybdenum layer 102 is formed on one surface side of a glass substrate 100 by evaporation or sputtering, an indium layer 103 is formed by evaporation at room temperature, and a copper layer 105 is formed on the indium layer 103 at room temperature. [FIG. 5]
Step (a)]. The indium layer 103 and the copper layer 105
Is subjected to heat treatment in a hydrogen sulfide atmosphere to form a p-type semiconductor layer 104 of CuInS 2 , and then the sulfide (Cu
In order to remove impurities such as xS Y ) and optimize the characteristics of the p-type semiconductor layer 104 to obtain stable characteristics,
The p-type semiconductor layer 10 is formed by a KCN solution containing
The surface of No. 4 is subjected to a KCN treatment for cleaning [step of FIG. 5 (b)]. Further, an n-type semiconductor layer 106 is formed on the p-type semiconductor layer 104 by a chemical solution deposition method (step of FIG. 5C), and ZnO: Al or In is further formed on the n-type semiconductor layer 106 by sputtering. Transparent electrode 108 made of 2 O 3
[Step (FIG. 5D)]. Then, the transparent electrode 1
By forming a comb-shaped electrode 110 made of aluminum on 08, the solar cell shown in FIG. 4 can be obtained.

【0004】[0004]

【発明が解決しようとする課題】図4に示す太陽電池に
おいては、KCN処理前のp型半導体層104を形成す
るCu及びInのCu/In原子濃度比率(以下、単に
Cu/In原子濃度比率と示す場合は、KCN処理前の
p型半導体層を形成するCu及びInのCu/In原子
濃度比率のことを示表する)を可及的に高くすること、
及び/又はp型半導体層104を可及的に厚くすること
によって、p型半導体層104内の結晶性を向上でき、
太陽電池の発電効率を向上できる。しかしながら、現状
においては、p型半導体層104のCu/In原子濃度
比率は、最終的に得られる太陽電池の歩留まり率等の観
点から略1.6が限界である。かかるCu/In原子濃
度比率が1.6を超えて高くすると、KCN処理工程に
おいて、p型半導体層104が電極膜102から剥離し
易くなるからである。このため、従来の太陽電池の製造
方法では、p型半導体層内の結晶性を向上することによ
って、太陽電池の発電効率を向上することは極めて困難
である。また、p型半導体層104の層厚も2μm程度
が限界である。層厚が2μmを超えるp型半導体層10
4を形成すべく、インジウム層103と銅層105とか
ら成る金属膜を厚くすると、KCN処理工程においてp
型半導体層104の剥離が発生するためである。ところ
で、p型半導体層104の層厚を厚く形成できれば、形
成されたp型半導体層104に化学エッチングを施すこ
とによって、p型半導体層の層厚を可及的に一様とする
ことができる。しかし、従来の太陽電池の製造方法で
は、化学エッチングを施して層厚を調整し得る厚さのp
型半導体層104を形成できず、層厚が可及的に一様な
p型半導体層104を、スパッタリングや蒸着のみによ
って形成しなければならなかった。このため、従来の太
陽電池の製造方法では、スパッタリングや蒸着の条件管
理を極めて厳格に行う必要があった。そこで、本発明の
課題は、主として銅(Cu)及びインジウム(In)によって形
成されて成るp型半導体層を具備するpn接合の化合物
半導体太陽電池を製造する際に、p型半導体層内の結晶
性を容易に向上し得る化合物半導体太陽電池の製造方法
を提供することにある。
In the solar cell shown in FIG. 4, the Cu / In atomic concentration ratio of Cu and In forming the p-type semiconductor layer 104 before the KCN treatment (hereinafter simply referred to as Cu / In atomic concentration ratio). Indicates the Cu / In atomic concentration ratio of Cu and In forming the p-type semiconductor layer before the KCN treatment) as much as possible;
And / or by making the p-type semiconductor layer 104 as thick as possible, the crystallinity in the p-type semiconductor layer 104 can be improved,
The power generation efficiency of the solar cell can be improved. However, at present, the limit of the Cu / In atomic concentration ratio of the p-type semiconductor layer 104 is about 1.6 from the viewpoint of the yield rate of the finally obtained solar cell. If the Cu / In atomic concentration ratio is higher than 1.6, the p-type semiconductor layer 104 is easily separated from the electrode film 102 in the KCN processing step. For this reason, in the conventional method of manufacturing a solar cell, it is extremely difficult to improve the power generation efficiency of the solar cell by improving the crystallinity in the p-type semiconductor layer. Also, the layer thickness of the p-type semiconductor layer 104 is limited to about 2 μm. P-type semiconductor layer 10 having a layer thickness exceeding 2 μm
4 is formed, the metal film composed of the indium layer 103 and the copper layer 105 is made thicker.
This is because peeling of the mold semiconductor layer 104 occurs. By the way, if the p-type semiconductor layer 104 can be formed to have a large thickness, the formed p-type semiconductor layer 104 can be chemically etched to make the p-type semiconductor layer as uniform as possible. . However, in the conventional method of manufacturing a solar cell, the thickness p is adjusted to a thickness that can be adjusted by chemical etching.
Since the p-type semiconductor layer 104 cannot be formed and the p-type semiconductor layer 104 has a thickness as uniform as possible, the p-type semiconductor layer 104 must be formed only by sputtering or vapor deposition. For this reason, in the conventional solar cell manufacturing method, it was necessary to very strictly manage the conditions of sputtering and vapor deposition. Accordingly, an object of the present invention is to provide a pn junction compound semiconductor solar cell including a p-type semiconductor layer mainly formed of copper (Cu) and indium (In), It is an object of the present invention to provide a method of manufacturing a compound semiconductor solar cell capable of easily improving the performance.

【0005】[0005]

【課題を解決するための手段】本発明者等は、前記課題
を解決すべく検討した結果、基板の一面側に形成した電
極膜上に形成したインジウム層と銅層のうち、インジウ
ム層を加熱しつつ形成することによって、p型半導体層
のCu/In原子濃度比率を1.8以上とし、且つ最終
的に得られるp型半導体層の層厚を2μm以上となるよ
うに、インジウム層と銅層との金属膜を厚くしても、K
CN処理の工程において、p型半導体層の剥離を可及的
に抑制できることを知り、本発明に到達した。すなわ
ち、本発明は、基板の一面側に形成された電極膜上にイ
ンジウム層と銅層とを積層して成る金属膜を形成した
後、前記金属膜に硫化処理又はセレン化処理を施してC
uInS2又はCuInSe2から成るp型半導体層を形
成し、次いで、前記p型半導体層をKCN溶液による洗
浄によって、硫化銅やセレン化銅等の不純物を除去する
KCN処理を施した後、前記p型半導体層上にn型半導
体層を形成して化合物半導体太陽電池を製造する際に、
該インジウム層を加熱しつつ形成すること、又は形成し
た前記インジウム層の表面を露出させた状態で、前記イ
ンジウム層に加熱処理を施すことを特徴とする化合物半
導体太陽電池の製造方法にある。
Means for Solving the Problems The present inventors have studied to solve the above problems, and as a result, of the indium layer and the copper layer formed on the electrode film formed on one side of the substrate, the indium layer is heated. The indium layer and the copper layer are formed such that the Cu / In atomic concentration ratio of the p-type semiconductor layer is 1.8 or more and the thickness of the finally obtained p-type semiconductor layer is 2 μm or more. Even if the metal film with the layer is thickened, K
The present inventors have found that in the step of CN treatment, the separation of the p-type semiconductor layer can be suppressed as much as possible, and have reached the present invention. That is, according to the present invention, a metal film formed by laminating an indium layer and a copper layer on an electrode film formed on one surface side of a substrate is formed, and then the metal film is subjected to a sulfurizing treatment or a selenization treatment to form a C film.
After forming a p-type semiconductor layer made of uInS 2 or CuInSe 2 , and then subjecting the p-type semiconductor layer to KCN treatment for removing impurities such as copper sulfide and copper selenide by washing with a KCN solution, When manufacturing a compound semiconductor solar cell by forming an n-type semiconductor layer on the type semiconductor layer,
A method of manufacturing a compound semiconductor solar cell, characterized in that the indium layer is formed while being heated, or the indium layer is subjected to heat treatment in a state where the surface of the formed indium layer is exposed.

【0006】かかる本発明において、インジウム層の形
成温度又はインジウム層に施す加熱処理の温度を、基板
が120〜210℃に加熱される温度とすることによっ
て、KCN処理工程でのp型半導体層の剥離を一層防止
できる。また、インジウム層と銅層とを積層して成る金
属膜を、KCN処理を施す前のp型半導体層を形成する
銅(Cu)及びインジウム(In)のCu/In原子濃度比
率が1.8以上となるように形成することによって、最
終的に得られる太陽電池の特性を向上できる。更に、K
CN処理を施す前のp型半導体層を、最終的に形成する
p型半導体層の厚さよりも厚くなるように形成し、KC
N処理後に化学エッチングによって所定の厚さに形成す
ることにより、p型半導体層を形成する蒸着やスパッタ
リングの条件管理を緩和しても、或いはp型半導体層の
層厚のコントロールが蒸着やスパッタリングに比較して
困難なめっきによっても、最終的に形成するp型半導体
層の厚さを容易にコントロールできる。特に、インジウ
ム層と銅層とを積層して成る金属膜を、KCN処理後又
は化学エッチング後のp型半導体層の厚さが2〜10μ
mとなるように形成することによって、最終的に得られ
る太陽電池の特性も向上できる。
In the present invention, the temperature of the formation of the indium layer or the temperature of the heat treatment applied to the indium layer is set to a temperature at which the substrate is heated to 120 to 210 ° C., whereby the p-type semiconductor layer in the KCN processing step is formed. Peeling can be further prevented. In addition, a metal film formed by laminating an indium layer and a copper layer is formed so that the Cu / In atom concentration ratio of copper (Cu) and indium (In) forming the p-type semiconductor layer before KCN treatment is 1.8. By forming as described above, the characteristics of the finally obtained solar cell can be improved. Furthermore, K
The p-type semiconductor layer before the CN treatment is formed so as to be thicker than the thickness of the p-type semiconductor layer to be finally formed.
By forming the layer to a predetermined thickness by chemical etching after the N treatment, the control of the conditions for vapor deposition or sputtering for forming the p-type semiconductor layer can be relaxed, or the control of the layer thickness of the p-type semiconductor layer can be controlled by vapor deposition or sputtering. The thickness of the finally formed p-type semiconductor layer can be easily controlled even by plating which is relatively difficult. In particular, a metal film formed by laminating an indium layer and a copper layer has a p-type semiconductor layer having a thickness of 2 to 10 μm after KCN treatment or chemical etching.
By forming so as to be m, the characteristics of the solar cell finally obtained can also be improved.

【0007】従来の化合物半導体太陽電池の製造方法で
は、KCN処理工程でのp型半導体層の剥離を防止すべ
く、p型半導体層のCu/In原子濃度比率を1.6以
下で且つ最終的に得られるp型半導体層の層厚を2μm
以下となるように、インジウム層と銅層とから成る金属
膜の膜厚を調整している。このため、最終的に得られた
p型半導体層の結晶粒径が小さく、太陽電池の発電効率
も低いものである。この点、本発明では、インジウム層
を加熱しつつ形成すること、又は形成したインジウム層
の表面を露出させた状態で、このインジウム層に加熱処
理を施すことによって、p型半導体層のCu/In原子
濃度比率を1.8以上とし、且つ最終的に得られるp型
半導体層の層厚が2μm以上となるように、インジウム
層と銅層とから成る金属膜の膜厚を調整しても、KCN
処理工程でのp型半導体層の剥離を防止できる。このた
め、本発明の製造方法では、p型半導体層のCu/In
原子濃度比率を従来よりも高くでき、且つ最終的に得ら
れるp型半導体層の層厚を従来よりも厚く形成できるよ
うに、インジウム層と銅層とから成る金属膜の膜厚を調
整できる結果、p型半導体層内の結晶性を向上でき、本
発明によって得られたpn接合の化合物半導体太陽電池
の発電効率を、従来の化合物半導体太陽電池の発電効率
よりも向上できる。更に、KCN処理を施した後のp型
半導体層の層厚も、従来の化合物半導体太陽電池の製造
方法によってKCN処理を施して得られたp型半導体層
の層厚よりも厚くすることができ、化学エッチングを施
してp型半導体層の層厚を調整できる。このため、p型
半導体層を形成するためのスパッタリングや蒸着の条件
管理の緩和を図ることができ、或いはp型半導体層の層
厚のコントロールが蒸着やスパッタリングに比較して困
難なめっきによっても、最終的に形成するp型半導体層
の厚さを容易にコントロールできる。
In the conventional method for manufacturing a compound semiconductor solar cell, in order to prevent the p-type semiconductor layer from peeling off in the KCN treatment step, the p-type semiconductor layer has a Cu / In atomic concentration ratio of 1.6 or less and a final concentration of 1.6% or less. The thickness of the p-type semiconductor layer obtained at
The thickness of the metal film composed of the indium layer and the copper layer is adjusted as described below. For this reason, the crystal grain size of the finally obtained p-type semiconductor layer is small, and the power generation efficiency of the solar cell is low. In this respect, in the present invention, the Cu / In of the p-type semiconductor layer is formed by heating the indium layer while heating the indium layer or performing heat treatment on the indium layer while exposing the surface of the formed indium layer. Even if the thickness of the metal film composed of the indium layer and the copper layer is adjusted so that the atomic concentration ratio is at least 1.8 and the layer thickness of the finally obtained p-type semiconductor layer is at least 2 μm, KCN
Peeling of the p-type semiconductor layer in the processing step can be prevented. Therefore, according to the manufacturing method of the present invention, Cu / In of the p-type semiconductor layer is used.
The result that the thickness of the metal film composed of the indium layer and the copper layer can be adjusted so that the atomic concentration ratio can be higher than before and the finally obtained p-type semiconductor layer can be formed thicker than before. In addition, the crystallinity in the p-type semiconductor layer can be improved, and the power generation efficiency of the pn junction compound semiconductor solar cell obtained by the present invention can be improved more than the power generation efficiency of the conventional compound semiconductor solar cell. Furthermore, the layer thickness of the p-type semiconductor layer after the KCN treatment can be made larger than the layer thickness of the p-type semiconductor layer obtained by performing the KCN treatment by the conventional method for manufacturing a compound semiconductor solar cell. The thickness of the p-type semiconductor layer can be adjusted by performing chemical etching. For this reason, it is possible to relax the control of the conditions of sputtering and vapor deposition for forming the p-type semiconductor layer, or even by plating in which the control of the layer thickness of the p-type semiconductor layer is difficult as compared with vapor deposition or sputtering. The thickness of the finally formed p-type semiconductor layer can be easily controlled.

【0008】[0008]

【発明の実施の形態】本発明に係る化合物半導体太陽電
池の製造方法の一例を図1に示す。図1に示す製造方法
では、先ず、ガラス基板10の一面側に、モリブデン層
12から成る電極膜を蒸着又はスパッタリングで形成し
た後[図1(a)の工程]、ガラス基板10をヒータ
(図示せず)で加熱しつつインジウム層13を蒸着によ
って形成する[図1(b)の工程]。かかるヒータによ
る加熱は、真空雰囲気下でガラス基板10に装着した熱
電対等の温度センサーで測定したガラス基板10が12
0〜210℃(好ましくは140〜190℃)となるよ
うに加熱する。また、かかる加熱は、室温下での蒸着に
よってインジウム層13を形成した後、このインジウム
層13の表面を露出させた状態で施してもよく、窒素ガ
ス等の非酸化性ガスの雰囲気下で施してもよい。
FIG. 1 shows an example of a method for manufacturing a compound semiconductor solar cell according to the present invention. In the manufacturing method shown in FIG. 1, first, an electrode film composed of a molybdenum layer 12 is formed on one surface side of the glass substrate 10 by vapor deposition or sputtering (step of FIG. 1A), and then the glass substrate 10 is heated (see FIG. 1A). (Not shown), the indium layer 13 is formed by vapor deposition (step of FIG. 1B). The heating by the heater is performed when the glass substrate 10 measured by a temperature sensor such as a thermocouple mounted on the glass substrate 10 under a vacuum atmosphere
The heating is performed so as to be 0 to 210 ° C (preferably 140 to 190 ° C). The heating may be performed after forming the indium layer 13 by vapor deposition at room temperature and then exposing the surface of the indium layer 13 or in an atmosphere of a non-oxidizing gas such as nitrogen gas. You may.

【0009】この様に、加熱しつつインジウム層13を
形成した後、或いは形成したインジウム層13の表面を
露出させた状態で、このインジウム層13に加熱処理を
施した後、インジウム層13上に銅層15を蒸着によっ
て形成する〔図1(c)の工程〕。この銅層15は、ヒ
ータによってガラス基板10を加熱しつつ蒸着によって
形成してもよく、室温下での蒸着によって形成してもよ
い。但し、室温下での蒸着によって形成したインジウム
層13上に銅層15を形成した後に加熱処理を施して
も、p型半導体層14のCu/In原子濃度比率を1.
8以上とすることは極めて困難である。ここで、図1
(b)(c)の工程では、インジウム層13を形成した
後、銅層15をインジウム層13上に形成したが、室温
下で銅層15を電極膜12上に形成した後、ガラス基板
10を加熱しつつ銅層15上にインジウム層13を形成
してもよく、又は室温下で銅層15上にインジウム層1
3を形成した後に、インジウム層13の表面を露出させ
た状態で、このインジウム層13に加熱処理を施しても
よい。尚、図1(b)(c)の工程では、インジウム層
13及び銅層15を蒸着によって形成しているが、スパ
ッタリングやめっきによって形成してもよく、蒸着、ス
パッタリング、及びめっきを併用してもよい。
As described above, after the indium layer 13 is formed while being heated, or after the surface of the formed indium layer 13 is exposed, the indium layer 13 is subjected to a heat treatment, and then the indium layer 13 is formed on the indium layer 13. A copper layer 15 is formed by vapor deposition (step of FIG. 1C). The copper layer 15 may be formed by vapor deposition while heating the glass substrate 10 by a heater, or may be formed by vapor deposition at room temperature. However, even if a heat treatment is performed after forming the copper layer 15 on the indium layer 13 formed by vapor deposition at room temperature, the Cu / In atomic concentration ratio of the p-type semiconductor layer 14 is 1.
It is extremely difficult to set it to 8 or more. Here, FIG.
In the steps (b) and (c), after the indium layer 13 was formed, the copper layer 15 was formed on the indium layer 13, but after the copper layer 15 was formed on the electrode film 12 at room temperature, the glass substrate 10 was formed. May be formed on the copper layer 15 while heating, or the indium layer 1 may be formed on the copper layer 15 at room temperature.
After forming the layer 3, the indium layer 13 may be subjected to a heat treatment in a state where the surface of the indium layer 13 is exposed. In the steps of FIGS. 1B and 1C, the indium layer 13 and the copper layer 15 are formed by vapor deposition, but may be formed by sputtering or plating, or by using vapor deposition, sputtering, and plating in combination. Is also good.

【0010】このインジウム層13と銅層15とから成
る金属膜を、硫化水素雰囲気中で加熱処理する硫化処理
を施してCuInS2のp型半導体層14とする。この
硫化処理は、アルゴンガス等の不活性ガス中に硫化水素
(H2S)が5vol %加えられた気体を、540℃の温
度雰囲気下で約2時間ほど流すことによって施すことが
できる。この様にして得られたp型半導体層14の表面
を、KCNが5〜10重量%含有されたKCN溶液によ
って洗浄し、p型半導体層14に生成された硫化物(C
xY)等の不純物を取り除きp型半導体層14の特性
を適正化して安定した特性とするKCN処理を施す〔図
1(d)の工程〕。かかるKCN処理において、p型半
導体層14の洗浄は、p型半導体層14を1〜5分間程
度浸漬することによって行うことができる。このKCN
処理の工程において、インジウム層13を加熱しつつ形
成することによって[図1(b)の工程]、硫化処理し
て形成したp型半導体層14のCu/In原子濃度比率
を1.8以上としても、p型半導体層14のKCN処理
によって剥離現象は発生しない。他方、図5に示す従来
の製造工程の如く、非加熱下でインジウム層103を形
成した場合、硫化処理して形成したp型半導体層104
では、KCN処理直前のp型半導体層のCu/In原子
濃度比率を1.6よりも高くすると、KCN処理によっ
てモリブデン層12からp型半導体層14が剥離する現
象が発生する。また、p型半導体層14の層厚を2μm
以上としても、p型半導体層14の剥離が生じないた
め、KCN処理を施したp型半導体層14に化学エッチ
ングを施し、層厚を調整すると共に、層厚が一様なp型
半導体層14を形成できる。この様に、p型半導体層1
4に化学エッチングを施すことができるため、インジウ
ム層13及び銅層15を形成する蒸着やスパッタリング
の条件管理を緩和でき、或いは,後述する様に、蒸着や
スパッタリングに比較して層厚のコントロールが困難な
めっきによってインジウム層13及び銅層15を形成で
きる。
[0010] The metal film comprising the indium layer 13 and the copper layer 15 is subjected to a heat treatment in a hydrogen sulfide atmosphere to form a CuInS 2 p-type semiconductor layer 14. This sulfurating treatment can be performed by flowing a gas in which 5 vol% of hydrogen sulfide (H 2 S) is added to an inert gas such as an argon gas at a temperature of 540 ° C. for about 2 hours. The surface of the p-type semiconductor layer 14 thus obtained is washed with a KCN solution containing 5 to 10% by weight of KCN, and the sulfide (C
u x S Y) or the like characteristics of the p-type semiconductor layer 14 remove impurities by optimizing subjected to KCN process to stable characteristics of [step shown in FIG. 1 (d)]. In such a KCN treatment, cleaning of the p-type semiconductor layer 14 can be performed by immersing the p-type semiconductor layer 14 for about 1 to 5 minutes. This KCN
In the processing step, the indium layer 13 is formed while being heated (step in FIG. 1B), so that the Cu / In atomic concentration ratio of the p-type semiconductor layer 14 formed by the sulfurization treatment is set to 1.8 or more. Also, the separation phenomenon does not occur due to the KCN treatment of the p-type semiconductor layer 14. On the other hand, when the indium layer 103 is formed without heating as in the conventional manufacturing process shown in FIG. 5, the p-type semiconductor layer 104 formed by the sulfurating treatment is formed.
If the Cu / In atomic concentration ratio of the p-type semiconductor layer immediately before the KCN treatment is higher than 1.6, a phenomenon occurs in which the p-type semiconductor layer 14 is separated from the molybdenum layer 12 by the KCN treatment. The thickness of the p-type semiconductor layer 14 is 2 μm.
Even with the above, since the p-type semiconductor layer 14 does not peel off, the p-type semiconductor layer 14 subjected to the KCN treatment is subjected to chemical etching to adjust the layer thickness and to form the p-type semiconductor layer 14 having a uniform layer thickness. Can be formed. Thus, the p-type semiconductor layer 1
4 can be subjected to chemical etching, so that the control of the conditions of the vapor deposition and sputtering for forming the indium layer 13 and the copper layer 15 can be eased, or the layer thickness can be controlled as compared with vapor deposition and sputtering as described later. The indium layer 13 and the copper layer 15 can be formed by difficult plating.

【0011】この様に形成したp型半導体層14上に
は、化学的溶液析出法によってn型半導体層16を形成
する〔図1(e)の工程〕。かかるn型半導体層16
は、ZnSO4(0.1mol/リットル)、チオ尿素
(0.6mol/リットル)及びNH3水溶液(3mo
l/リットル)が混合されて80℃に維持された混合液
に、p型半導体層14を形成したガラス基板10を約1
0分間程浸漬することによって形成できる。この工程は
n型半導体層14がZnSの場合であり、n型半導体層
14をCdSとする場合は、ヨウ化カドミウム(0.0
015mol/リットル)、NH3水溶液(1.0mo
l/リットル)及びヨウ化アンモニウム(0.01mo
l/リットル)を混合した液に基板を入れ、加温して約
40℃になったところで、チオ尿素(0.15mol/
リットル)を入れ、80℃で5分間浸漬することによっ
て形成できる。更に、n型半導体層16上に、Alがド
ープされたZnOから成る透明電極18を形成する〔図
1(f)の工程〕。その後、透明電極18上に、アルミ
ニウムから成る櫛形電極110を形成して太陽電池を得
ることができる。
An n-type semiconductor layer 16 is formed on the p-type semiconductor layer 14 thus formed by a chemical solution deposition method (step of FIG. 1E). Such n-type semiconductor layer 16
Are ZnSO 4 (0.1 mol / l), thiourea (0.6 mol / l) and NH 3 aqueous solution ( 3 mol / l)
1 / liter) was mixed and maintained at 80 ° C., and about 1 glass substrate 10 on which the p-type semiconductor layer 14 was formed was added.
It can be formed by immersion for about 0 minutes. This step is for the case where the n-type semiconductor layer 14 is made of ZnS, and when the n-type semiconductor layer 14 is made of CdS, cadmium iodide (0.0
015 mol / liter), NH 3 aqueous solution (1.0 mol
l / liter) and ammonium iodide (0.01 mol
1 / liter), and the mixture was heated. When the temperature reached about 40 ° C., thiourea (0.15 mol /
Liter) and immersion at 80 ° C. for 5 minutes. Further, a transparent electrode 18 made of ZnO doped with Al is formed on the n-type semiconductor layer 16 [step of FIG. 1 (f)]. Thereafter, a comb electrode 110 made of aluminum is formed on the transparent electrode 18 to obtain a solar cell.

【0012】図1に示す方法によれば、p型半導体層1
4のCu/In原子濃度比率を1.8以上としても、K
CN処理工程でのp型半導体層14の剥離現象を防止で
き、p型半導体層14内の結晶性を向上でき、且つその
製造工程は図5に示す従来の製造工程と略同工程である
ため、安価で且つ高性能の太陽電池を得ることができ
る。更に、かかる図1に示す製造方法によって、最終的
に得られるp型半導体層14の厚さが2〜10μm(好
ましくは3〜6μm)となるように、インジウム層13
と銅層15とから成る金属膜の膜厚を調整することが好
ましい。ここで、p型半導体層14の厚さを2μm未満
の厚さとすると、p型半導体層14内の結晶性が低下す
る傾向にあり、他方、p型半導体層14の厚さを10μ
mを超えて厚くすると、p型半導体層14の内部抵抗が
高くなる傾向にある。
According to the method shown in FIG. 1, the p-type semiconductor layer 1
Even if the Cu / In atomic concentration ratio of No. 4 is 1.8 or more, K
Since the separation phenomenon of the p-type semiconductor layer 14 in the CN processing step can be prevented, the crystallinity in the p-type semiconductor layer 14 can be improved, and the manufacturing process is substantially the same as the conventional manufacturing process shown in FIG. Thus, an inexpensive and high-performance solar cell can be obtained. Further, the indium layer 13 is formed by the manufacturing method shown in FIG. 1 such that the finally obtained p-type semiconductor layer 14 has a thickness of 2 to 10 μm (preferably 3 to 6 μm).
It is preferable to adjust the thickness of the metal film including the metal layer and the copper layer 15. Here, if the thickness of the p-type semiconductor layer 14 is less than 2 μm, the crystallinity in the p-type semiconductor layer 14 tends to decrease, while the thickness of the p-type semiconductor layer 14 is 10 μm.
When the thickness exceeds m, the internal resistance of the p-type semiconductor layer 14 tends to increase.

【0013】図1に示す製造方法によって得られた太陽
電池を図2に示す。図2において、図2(a)は太陽電
池の正面図であり、図2(b)は太陽電池の斜視図であ
る。図2に示す太陽電池は、基板としてのガラス基板1
0上に電極膜としてモリブデン層12が形成されてい
る。このモリブデン層12上には、CuInS2のp型
半導体層14とZnSのn型半導体層16とが順次積層
されており、n型半導体層16上に透明電極18が形成
されている。更に、透明電極18上には櫛形電極20が
形成されている。この櫛形電極20は、図1(a)に示
す様に、電極が枝別れ状(櫛形状)に形成されているも
のである。図2に示す太陽電池には、櫛形電極20と対
となる電極端子22が、モリブデン層12の表面の一部
が露出して形成されている。この電極端子22は、モリ
ブデン層12上で電極端子を形成する部位に、予め保護
用のレジスト又はマスクにより被覆しておき、p型半導
体層14、n型半導体層16、透明電極18を形成した
後、保護用のレジスト又はマスクを除去することによっ
て形成できる。
FIG. 2 shows a solar cell obtained by the manufacturing method shown in FIG. 2A is a front view of the solar cell, and FIG. 2B is a perspective view of the solar cell. The solar cell shown in FIG. 2 has a glass substrate 1 as a substrate.
A molybdenum layer 12 is formed on electrode 0 as an electrode film. On the molybdenum layer 12, a p-type semiconductor layer 14 of CuInS 2 and an n-type semiconductor layer 16 of ZnS are sequentially laminated, and a transparent electrode 18 is formed on the n-type semiconductor layer 16. Further, a comb-shaped electrode 20 is formed on the transparent electrode 18. As shown in FIG. 1A, the comb-shaped electrode 20 has electrodes formed in a branched shape (comb shape). In the solar cell shown in FIG. 2, an electrode terminal 22 that is paired with the comb electrode 20 is formed with a part of the surface of the molybdenum layer 12 exposed. The electrode terminals 22 were previously coated on the molybdenum layer 12 where the electrode terminals were to be formed with a protective resist or mask to form the p-type semiconductor layer 14, the n-type semiconductor layer 16, and the transparent electrode 18. After that, it can be formed by removing the protective resist or mask.

【0014】図2に示す太陽電池のI−V特性を図3の
曲線Aとして示す。AM1.5(100mW/cm2)の
条件により測定した結果である。曲線AのI−V特性を
呈する太陽電池は、受光面積(有効面積)が0.25c
2の太陽電池あって、次のようにして形成した。先
ず、ガラス基板10の一面側に形成した厚さ約1μmの
モリブデン層12上に、蒸着によって加熱しつつ形成し
た厚さ2000nmのインジウム層13と厚さ2600
nmの銅層15とから成る金属膜を形成し、この金属膜
に硫化処理を施してCuInS2から成るp型半導体層
14を形成した。かかるp型半導体層14の厚さは約8
μmであって、Cu/In原子濃度比率は3.0であっ
た。次いで、p型半導体層14にKCN処理を施した
後、更に化学エッチングを施してp型半導体層14の厚
さを約4μmとした。その後、p型半導体層14上に、
厚さ80〜120nmのZnSから成るn型半導体層1
6を形成し、更にAlがドープされたZnOから成る厚
さ約1μmの透明電極18を形成した。尚、n型半導体
層16としてCdS、InSを使用した場合も同様であ
る。
The IV characteristic of the solar cell shown in FIG. 2 is shown as a curve A in FIG. It is a result measured under the condition of AM 1.5 (100 mW / cm 2 ). The solar cell exhibiting the IV characteristic of the curve A has a light receiving area (effective area) of 0.25c.
An m 2 solar cell was formed as follows. First, on a molybdenum layer 12 having a thickness of about 1 μm formed on one surface side of a glass substrate 10, an indium layer 13 having a thickness of 2000 nm
A metal film comprising a copper layer 15 nm in thickness was formed, and the metal film was subjected to sulfuration treatment to form a p-type semiconductor layer 14 made of CuInS 2 . The thickness of the p-type semiconductor layer 14 is about 8
μm, and the Cu / In atomic concentration ratio was 3.0. Next, after performing the KCN treatment on the p-type semiconductor layer 14, the p-type semiconductor layer 14 was further subjected to chemical etching to reduce the thickness of the p-type semiconductor layer 14 to about 4 μm. Then, on the p-type semiconductor layer 14,
N-type semiconductor layer 1 made of ZnS having a thickness of 80 to 120 nm
6 and a transparent electrode 18 made of ZnO doped with Al and having a thickness of about 1 μm. The same applies to the case where CdS or InS is used as the n-type semiconductor layer 16.

【0015】他方、図5に示す従来の製造方法によって
製造された図4に示す従来の太陽電池のI−V特性を、
図3に曲線Bとして併記する。この曲線Bは、曲線Aの
測定と同一の条件で測定した結果である。曲線BのI−
V特性を呈する太陽電池は、その受光面積(有効面積)
が0.25cm2であって、ガラス基板100上に形成
された厚さ約1μmのモリブデン層102、厚さ約2μ
mで且つKCN処理前のCu/In原子濃度比率が1.
6であったCuInS2から成るp型半導体層104、
厚さ80〜120nmのZnSによるn型半導体層10
6及びAlがドープされたZnOから成る厚さ約1μm
の透明電極18によって構成されている。図3から明ら
かな様に、図1に示す製造方法で製造した図2の太陽電
池のI−V特性は、図4に示す従来の太陽電池のI−V
特性よりも良好であり、図3に示すI−V特性から導か
れる発電効率は11.7%である。一方、図4に示す従
来の太陽電池の発電効率は9.7%であった。
On the other hand, the IV characteristics of the conventional solar cell shown in FIG. 4 manufactured by the conventional manufacturing method shown in FIG.
Also shown in FIG. The curve B is a result measured under the same conditions as the measurement of the curve A. Curve B I-
A solar cell exhibiting V characteristics has a light receiving area (effective area).
Is 0.25 cm 2 , a molybdenum layer 102 having a thickness of about 1 μm formed on a glass substrate 100 and a thickness of about 2 μm.
m and the Cu / In atomic concentration ratio before the KCN treatment is 1.
6, a p-type semiconductor layer 104 of CuInS 2 ,
80-120 nm thick n-type semiconductor layer 10 of ZnS
6 and Al doped ZnO about 1 μm thick
Of the transparent electrode 18. As apparent from FIG. 3, the IV characteristics of the solar cell of FIG. 2 manufactured by the manufacturing method shown in FIG. 1 are the same as those of the conventional solar cell shown in FIG.
It is better than the characteristics, and the power generation efficiency derived from the IV characteristics shown in FIG. 3 is 11.7%. On the other hand, the power generation efficiency of the conventional solar cell shown in FIG. 4 was 9.7%.

【0016】図1に示す製造方法では、インジウム層1
3と銅層15とを蒸着によって形成したが、いずれか一
方の層又は両層をめっきによって形成してもよい。但
し、めっきによってインジウム層13を形成する場合
は、蒸着やスパッタリングのように加熱しつつインジウ
ム層13を形成することは不可能である。このため、イ
ンジウム層13を形成した後に、インジウム層13の表
面を露出させた状態で、このインジウム層13を120
〜210℃(特に好ましくは140〜190℃)に加熱
する。また、めっきによってインジウム層13及び/又
は銅層15を形成する場合、蒸着やスパッタリングによ
ってインジウム層13と銅層15とを形成する場合に比
較して、層厚をコントロールすることは困難である。こ
のため、KCN処理前のp型半導体層14を、最終的に
形成するp型半導体層14の層厚よりも厚く形成し、K
CN処理後に化学エッチングを施して所定厚さのp型半
導体層14としてもよい。この化学エッチングには、過
酸化水素、硫酸、水酸化アンモニウム、過硫酸アンモニ
ウム、過硫酸ナトリウム、硫酸銅、アンモニア、硝酸、
燐酸、及び塩酸から成る化合物群から選ばれた単独又は
複数の化合物を用いることができる。特に、過酸化水素
が好適である。この様に、KCN処理前のp型半導体層
14を、最終的に形成するp型半導体層14の層厚より
も厚くなるように、めっきによってインジウム層13及
び/又は銅層15を形成することは、p型半導体層14
の層厚を容易にコントロールできるばかりか、p型半導
体層14を形成するCuInS2の結晶の成長を促進し
て結晶粒径を可及的に大きくすることができ、最終的に
得られる太陽電池の発電効率を向上できる。尚、蒸着や
スパッタリングのみによって、インジウム層13と銅層
15とから成る金属膜を形成する場合も、p型半導体層
14を形成するCuInS2の結晶の成長を促進して結
晶粒径を可及的に大きくすべく、最終的に形成するp型
半導体層14が2〜10μm(好ましくは3〜6μm)
となるように、金属膜の膜厚を調整することが好まし
い。
In the manufacturing method shown in FIG.
3 and the copper layer 15 are formed by vapor deposition, but either one or both layers may be formed by plating. However, when the indium layer 13 is formed by plating, it is impossible to form the indium layer 13 while heating such as vapor deposition or sputtering. For this reason, after the indium layer 13 is formed, the indium layer 13 is
To 210 ° C (particularly preferably 140 to 190 ° C). In addition, when the indium layer 13 and / or the copper layer 15 is formed by plating, it is more difficult to control the layer thickness than when the indium layer 13 and the copper layer 15 are formed by vapor deposition or sputtering. Therefore, the p-type semiconductor layer 14 before the KCN treatment is formed to be thicker than the p-type semiconductor layer 14 to be finally formed,
After the CN treatment, chemical etching may be performed to form the p-type semiconductor layer 14 having a predetermined thickness. This chemical etching includes hydrogen peroxide, sulfuric acid, ammonium hydroxide, ammonium persulfate, sodium persulfate, copper sulfate, ammonia, nitric acid,
One or a plurality of compounds selected from the group consisting of phosphoric acid and hydrochloric acid can be used. In particular, hydrogen peroxide is preferred. As described above, the indium layer 13 and / or the copper layer 15 are formed by plating so that the p-type semiconductor layer 14 before the KCN treatment is thicker than the finally formed p-type semiconductor layer 14. Is the p-type semiconductor layer 14
Not only can easily control the layer thickness of Cu, but also the crystal grain size can be increased as much as possible by promoting the growth of CuInS 2 crystal forming the p-type semiconductor layer 14, and the finally obtained solar cell Power generation efficiency can be improved. When a metal film composed of the indium layer 13 and the copper layer 15 is formed only by vapor deposition or sputtering, the growth of the crystal of CuInS 2 forming the p-type semiconductor layer 14 is promoted to increase the crystal grain size. In order to increase the size, the p-type semiconductor layer 14 to be finally formed is 2 to 10 μm (preferably 3 to 6 μm).
It is preferable to adjust the thickness of the metal film so that

【0017】以上の説明では、インジウム層13と銅層
15とから成る金属層に、硫化水素雰囲気中で加熱処理
する硫化処理を施すことによって、CuInS2のp形
半導体層14を形成したが、インジウム層13と銅層1
5とから成る金属層に、セレン化水素雰囲気中で加熱処
理するセレン化処理を施し、CuInSe2のp形半導
体層14を形成する場合も、本発明を適用することがで
きる。また、p形半導体層14を形成するCuInS2
又はCuInSe2中に、微量のガリウム(Ga)が含
有されていてもよい。この様に、微量のガリウム(G
a)が含有されているp形半導体層14を形成するに
は、例えば図1に示す方法において、ガラス基板10の
基板面に形成したモリブデン層12上にガリウム層をガ
リウム(Ga)又は硫化ガリウム(GaS)のスパッタ
リング又は蒸着によって形成した後、インジウム層13
と銅層15とを形成するが、或いはモリブデン層12上
にインジウム層13と銅層15とを形成した後、同様に
ガリウム層を形成し、次いで、硫化水素雰囲気中で加熱
処理する硫化処理を施すことによって、微量のガリウム
(Ga)を含有するCuInS2から成るp形半導体層
14を形成できる。同様のp形半導体層14は、ガラス
基板10の基板面に形成したモリブデン層12上にイン
ジウム層13を形成した後、銅(Cu)−ガリウム(G
a)合金層をスパッタリング又は蒸着によって形成し、
次いで、硫化水素雰囲気中で加熱処理する硫化処理を施
しても形成できる。
In the above description, the p-type semiconductor layer 14 of CuInS 2 is formed by subjecting a metal layer composed of the indium layer 13 and the copper layer 15 to a sulfurating treatment of heating in a hydrogen sulfide atmosphere. Indium layer 13 and copper layer 1
The present invention can also be applied to a case where the metal layer made of No. 5 is subjected to heat treatment in a hydrogen selenide atmosphere to form a p-type semiconductor layer 14 of CuInSe 2 . Also, CuInS 2 forming the p-type semiconductor layer 14
Alternatively, a trace amount of gallium (Ga) may be contained in CuInSe 2 . Thus, a trace amount of gallium (G
In order to form the p-type semiconductor layer 14 containing a), a gallium layer is formed on the molybdenum layer 12 formed on the substrate surface of the glass substrate 10 by gallium (Ga) or gallium sulfide, for example, in the method shown in FIG. After being formed by sputtering or vapor deposition of (GaS), the indium layer 13 is formed.
And a copper layer 15, or after forming an indium layer 13 and a copper layer 15 on the molybdenum layer 12, similarly forming a gallium layer and then performing a heat treatment in a hydrogen sulfide atmosphere. By performing this, the p-type semiconductor layer 14 made of CuInS 2 containing a trace amount of gallium (Ga) can be formed. A similar p-type semiconductor layer 14 is formed by forming an indium layer 13 on a molybdenum layer 12 formed on a substrate surface of a glass substrate 10 and then forming a copper (Cu) -gallium (G
a) forming an alloy layer by sputtering or vapor deposition;
Next, it can also be formed by performing a sulfurization treatment of performing a heat treatment in a hydrogen sulfide atmosphere.

【0018】[0018]

【発明の効果】本発明によれば、KCN処理前のp型半
導体層のCu/In原子濃度比率を、従来のpn接合の
化合物半導体太陽電池よりも高くでき、且つ最終的に得
られるp型半導体層も従来よりも厚くできるため、p型
半導体層内の結晶性を向上できる。このため、本発明に
係る製造方法によって得られたpn接合の化合物半導体
太陽電池の発電効率は、従来の製造方法によって得られ
たpn接合の化合物半導体太陽電池の発電効率よりも向
上できる。その結果、pn接合の化合物半導体太陽電池
の普及を図ることができる。また、KCN処理を施した
p型半導体層も従来よりも厚く形成でき、化学エッチン
グによって最終的に得られるp型半導体層の層厚を調整
できるため、インジウム層と銅層とから成る金属層を容
易に形成でき、発電効率が従来よりも向上されたpn接
合の化合物半導体太陽電池を容易に形成できる。
According to the present invention, the Cu / In atomic concentration ratio of the p-type semiconductor layer before the KCN treatment can be made higher than that of the conventional pn junction compound semiconductor solar cell, and the p-type semiconductor layer finally obtained can be obtained. Since the semiconductor layer can be made thicker than before, the crystallinity in the p-type semiconductor layer can be improved. For this reason, the power generation efficiency of the pn junction compound semiconductor solar cell obtained by the manufacturing method according to the present invention can be higher than that of the pn junction compound semiconductor solar cell obtained by the conventional manufacturing method. As a result, the spread of pn junction compound semiconductor solar cells can be achieved. Also, the p-type semiconductor layer subjected to the KCN treatment can be formed thicker than before, and the layer thickness of the p-type semiconductor layer finally obtained by chemical etching can be adjusted, so that the metal layer composed of the indium layer and the copper layer is formed. A pn-junction compound semiconductor solar cell that can be easily formed and whose power generation efficiency has been improved compared to the related art can be easily formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る化合物半導体太陽電池の製造方法
の一例を説明するための工程図である。
FIG. 1 is a process diagram illustrating an example of a method for manufacturing a compound semiconductor solar cell according to the present invention.

【図2】図1に示す製造方法で得られた化合物半導体太
陽電池の正面図及び斜視図である。
2 is a front view and a perspective view of a compound semiconductor solar cell obtained by the manufacturing method shown in FIG.

【図3】図1に示す製造方法で得られた太陽電池のI−
V特性を示すグラフである。
FIG. 3 is a graph showing I- of the solar cell obtained by the manufacturing method shown in FIG.
5 is a graph showing V characteristics.

【図4】従来の化合物半導体太陽電池の一例を説明する
ための正面図及び縦断面図である。
FIG. 4 is a front view and a longitudinal sectional view for explaining an example of a conventional compound semiconductor solar cell.

【図5】図5に示す従来の化合物半導体太陽電池の製造
方法の一例を説明するための工程図である。
FIG. 5 is a process chart illustrating an example of a method for manufacturing the conventional compound semiconductor solar cell shown in FIG.

【符号の説明】[Explanation of symbols]

10 ガラス基板 12 モリブデン層(電極膜) 13 インジウム層 14 p型半導体層 15 銅層 16 n型半導体層 18 透明電極層 20 櫛形電極 Reference Signs List 10 glass substrate 12 molybdenum layer (electrode film) 13 indium layer 14 p-type semiconductor layer 15 copper layer 16 n-type semiconductor layer 18 transparent electrode layer 20 comb-shaped electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 市川 純廣 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 Fターム(参考) 5F051 AA10 DA03 FA06 FA14 FA16 GA03  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor: Sumitomo Ichikawa, Nagano City, Nagano Pref.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板の一面側に形成された電極膜上にイ
ンジウム層と銅層とを積層して成る金属膜を形成した
後、前記金属膜に硫化処理又はセレン化処理を施してC
uInS2又はCuInSe2から成るp型半導体層を形
成し、 次いで、前記p型半導体層をKCN溶液による洗浄によ
って、硫化銅やセレン化銅等の不純物を除去するKCN
処理を施した後、前記p型半導体層上にn型半導体層を
形成して化合物半導体太陽電池を製造する際に、 該インジウム層を加熱しつつ形成すること、又は形成し
た前記インジウム層の表面を露出させた状態で、前記イ
ンジウム層に加熱処理を施すことを特徴とする化合物半
導体太陽電池の製造方法。
1. A metal film formed by laminating an indium layer and a copper layer on an electrode film formed on one surface side of a substrate, and then the metal film is subjected to sulfidation treatment or selenization treatment to form a C film.
forming a p-type semiconductor layer made of uInS 2 or CuInSe 2 , and then removing the impurities such as copper sulfide and copper selenide by washing the p-type semiconductor layer with a KCN solution.
After performing the treatment, when an n-type semiconductor layer is formed on the p-type semiconductor layer to manufacture a compound semiconductor solar cell, the indium layer is formed while being heated, or a surface of the formed indium layer And subjecting the indium layer to a heat treatment while exposing the compound.
【請求項2】 インジウム層の形成温度又はインジウム
層に施す加熱処理の温度を、基板が120〜210℃に
加熱される温度とする請求項1記載の化合物半導体太陽
電池の製造方法。
2. The method according to claim 1, wherein the temperature at which the indium layer is formed or the temperature of the heat treatment applied to the indium layer is set to a temperature at which the substrate is heated to 120 to 210 ° C.
【請求項3】 インジウム層と銅層とを積層して成る金
属膜を、KCN処理を施す前のp型半導体層の銅(Cu)
及びインジウム(In)のCu/In原子濃度比率が1.
8以上となるように形成する請求項1又は請求項2記載
の化合物半導体太陽電池の製造方法。
3. A metal film formed by laminating an indium layer and a copper layer is coated with copper (Cu) of a p-type semiconductor layer before performing a KCN treatment.
And the indium (In) Cu / In atomic concentration ratio is 1.
3. The method for manufacturing a compound semiconductor solar cell according to claim 1, wherein the number is 8 or more.
【請求項4】 KCN処理を施す前のp型半導体層を、
最終的に形成するp型半導体層の厚さよりも厚くなるよ
うに形成し、KCN処理後に化学エッチングによって所
定の厚さに形成する請求項1〜3のいずれか一項記載の
化合物半導体太陽電池の製造方法。
4. The p-type semiconductor layer before performing the KCN treatment,
The compound semiconductor solar cell according to any one of claims 1 to 3, wherein the compound semiconductor solar cell is formed so as to be thicker than a thickness of a p-type semiconductor layer to be finally formed, and is formed to a predetermined thickness by chemical etching after KCN treatment. Production method.
【請求項5】 インジウム層と銅層とを積層して成る金
属膜を、KCN処理後又は化学エッチング後のp型半導
体層の厚さが2〜10μmとなるように形成する請求項
1〜4のいずれか一項記載の化合物半導体太陽電池の製
造方法。
5. A metal film formed by laminating an indium layer and a copper layer such that the p-type semiconductor layer after KCN treatment or chemical etching has a thickness of 2 to 10 μm. The method for producing a compound semiconductor solar cell according to any one of the above.
JP36703999A 1999-03-29 1999-12-24 Method for producing compound semiconductor solar cell Expired - Lifetime JP3777280B2 (en)

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EP00302565A EP1041645A3 (en) 1999-03-29 2000-03-28 Compound semiconductor solar cell and production method

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JP11-252550 1999-09-07
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* Cited by examiner, † Cited by third party
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Publication number Priority date Publication date Assignee Title
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