JP2001147890A - Input and output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input and output device having not less than two interfaces capable of data communication based on an IEEE 1284 specifications for simultaneously realizing data communication. SOLUTION: When a request for the transmission and reception of data based on an IEEE 1284 specifications is issued from a PC, an interface part 11 detects it, and informs an access detecting part 12 of the issue of the access request. Then, the access detecting part 12 informs an access arbitrating part 13 of the inputted access information. When the access request is issued simultaneously at that time, the access arbitrating part 13 applies the permission of an operation to each access control part 14 according to a preliminarily decided sequence, and also controls a data switching part 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an input / output device that performs data transfer according to the EE1284 standard.

[0002]

2. Description of the Related Art Generally, in a device such as a printer,
Various interface methods are provided for transmitting and receiving data to and from a personal computer (hereinafter, referred to as a PC).
There are methods according to the four standards. FIG. 5 is a block diagram of a conventional input / output device, and shows a block diagram in the case of transmitting and receiving data according to the IEEE1284 standard. 1
0 is an input / output terminal for transmitting and receiving PC data, and 11 is an I / O terminal.
An interface unit for transmitting and receiving data to and from a PC according to the EEE1284 standard.
1 is an access detection unit that receives notification that there is an access request from a PC; 14 is an access control unit that controls the interface unit 11 when access is detected;
Reference numeral 6 denotes a memory control unit for controlling a memory for storing received data, and reference numeral 17 denotes a memory for storing received data.

An operation for receiving data from a PC will be briefly described. When there is a transmission request from the PC, negotiation is performed with the PC according to the IEEE1284 standard. The interface unit 11
The transmission request of the PC is detected from the operation of the interface signal of the EEE1284 standard and the access detection unit 12 is notified. The access detection unit 12 instructs the access control unit 14 that there is an access request, and the access control unit 14
It controls the interface unit 11 to acquire data according to the standard. Further, it also instructs the memory control unit 16 to store the received data in the memory 17. The access detection unit 12 and the access control unit 14 are specifically a CPU
May be realized by software operation.

FIG. 6 is a block diagram of a conventional input / output device, in which two input / output terminals for a PC are provided. Reference numeral 15 denotes a switching unit. in this case,
Which terminal is used to receive data from the PC is determined by mechanically switching the switching unit 15.

[0005]

Conventionally, an IEEE standard for transmitting / receiving data to / from a PC in a peripheral device such as a printer.
An interface conforming to the 1284 standard is generally equipped with one interface, and is not configured to have two or more interfaces. When two or more devices are provided, mechanical switching can be considered as shown in FIG.
There is a problem that data cannot be transmitted and received according to the EEE1284 standard.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an input / output device capable of simultaneously transmitting and receiving data with two or more interfaces conforming to the IEEE1284 standard.

[0007]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an interface means for performing data transfer of two or more IEEE 1284 standards, a detecting means for detecting an access request from each interface means, Arbitration means for managing an access right for each access request in accordance with a detection result; and access control means for determining an access method. When accesses occur simultaneously, the access control means and the control order are determined in accordance with the arbitration result. Was decided.

According to the present invention, two or more IEEE
An input / output device capable of transmitting and receiving data through an interface conforming to the E1284 standard is obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises: interface means for performing data transfer according to two or more IEEE1284 standards; detecting means for detecting an access request from each interface means; Arbitration means for managing an access right for each access request according to a result; and access control means for determining an access method. When accesses occur simultaneously, the access control means and the control order are changed according to the arbitration result. And two or more IEEE 1284
Even if there is a data access request according to the standard, arbitration is performed for each access request according to a predetermined control means and control order, so that data can be transmitted and received at the same time.

The invention according to claim 2 of the present invention comprises two or more DMA (direct memory access) transfer means, an arbitration means for managing an access right for each DMA request, and a priority setting means, The DMA transfer is performed in accordance with the control order determined by the order setting means. Even if there are two or more data access requests according to the IEEE1284 standard, the DM transfer is performed according to the priority setting means.
Since the A transfer is arbitrated, the DMA transfer of data can be performed at the same time.

(Embodiment 1) FIG. 1 is a block diagram showing an input / output device according to Embodiment 1 of the present invention. In FIG. 1, 10 is an input / output terminal for transmitting and receiving data from a PC, 11 is an interface unit for generating a signal conforming to the IEEE1284 standard, 12 is an access detection unit for detecting an access request from each interface unit 11, 13 Is an access arbitration unit that gives permission for operation to each interface unit 11 in accordance with information from the access detection unit 12, and 14 is an access arbitration unit.
, An access control unit for instructing an operation method, a switching unit for switching data stored in each memory,
Is a memory control unit for controlling a memory, and 17 is an IEEE 12
This is a memory for storing data received according to the E.84 standard.

The operation of the input / output device configured as described above will be described below. FIG. 2 is a flowchart of the operation of the input / output device according to Embodiment 1 of the present invention.
First, when there is a request for transmission and reception of data in accordance with the IEEE1284 standard from the PC, the interface unit 11 detects through a signal input from the input / output unit 10 and the access detection unit 1
2 is notified that there is an access request (step 1). Next, the access detection unit 12 notifies the access arbitration unit 13 of the obtained access information (Step 2). At this time, if there is one access request, the access arbitration unit 1
3 gives access information from the interface unit 11 and operation permission to the access control unit 14 to the interface to which the access request is made (step 3A1), and switches the switching unit 15 to the control unit to which the access request is made (step 3A2). The operation is also instructed to the memory control unit (step 3A3). The access control unit 14 instructs the operation contents to the interface unit 11 and stores the data received from the PC in the memory 17 (step 3A).
4). The memory 17 is controlled by the memory controller 16 in accordance with information from the access arbitration unit 13 (steps 3A and 3B).

Next, a case where an access request is made simultaneously from two interface units 11 will be described. If there is an access request at the same time, the access detection unit 12
Is input to the access arbitration unit 13. In the access arbitration unit 13, the operation permission is given to each access control unit according to a predetermined order (Step 4,
5). For example, when permitting the interface unit 1 first and then permitting the interface unit 2 later, first, the access control unit 14 of the interface unit 1 is permitted, and at the same time, the switching unit 15 is switched to the interface unit 1 side. Give instructions to the department. The access control unit 1 instructs the interface unit 11 on the operation contents according to the permission contents, and outputs the received data to the memory 17 (step 4, the contents are the same as step 3A). At this time, the access control unit 2 has to wait.

When the data reception from the interface unit 1 is completed, the access arbitration unit 13
Operation permission is given to the access control unit 2 for controlling the operation. The access control unit 2 that controls the interface unit 2 accumulates data received from the PC in the memory, similarly to the access control unit 1 (step 5, the contents are the same as step 3B). In the case where requests from the respective interfaces occur simultaneously, the access arbitration unit 13 determines in advance the order from which interface to receive the data in accordance with the content of each request.

As described above, in the present embodiment, even if access requests from the respective interface units are generated at the same time,
Since there is an arbitration function for controlling the operation permission to each interface unit according to the request contents, two or more IEEE1284
Data transfer according to the standard can be performed simultaneously.

(Embodiment 2) FIG. 3 is a block diagram of an input / output device according to Embodiment 2 of the present invention, and FIG. 4 is a flowchart of the operation of the input / output device. In FIG.
0 to 17 are the same as in the first embodiment. 20 is D
A priority order setting unit for giving priority to an MA (Direct Memory Access) function, a DMA arbitration unit 21 for arbitrating DMA operation, and a DMA unit 22 for transferring data from each interface unit 11 to the memory.

The operation of the input / output device configured as described above will be described below with reference to the flowchart of FIG. The difference from the first embodiment is that, with respect to data transfer from the PC, the operation contents are instructed by the access control unit, but the data transfer is controlled by the DMA unit.

First, necessary parameters such as a transfer address to a memory are set in the DMA unit 1 and the DMA unit 2, and DMA transfer is performed.
Start. When there is a request for transmission / reception of data in accordance with the IEEE1284 standard from the PC, the interface unit 11 detects through a signal input from the input / output terminal 10 and notifies the access detection unit 12 that there is an access request (step 11). Next, the access detection unit 12 notifies the access arbitration unit 13 of the obtained access information. The access arbitration unit 13 understands the contents of access from each interface and, when it is necessary to give an instruction to the access control unit 14, gives the operation contents and operation permission to the access control (step 12). The access arbitration unit 13 operates when an operation mode switching or the like occurs instead of arbitration of data transfer.

If the operation contents are changed simultaneously for each interface, an operation instruction is given to each access control unit 14 in accordance with a predetermined control order (steps 13, 14A, 14B, 15, 16). On the other hand, when data transfer occurs in response to an access request from each of the interface units 11,
Outputs a request signal to the DMA arbitration unit 21 (step 17). The DMA arbitration unit 21 gives the operation permission to the DMA unit 22 for the interface unit 11 to which the access request is made (step 18A1 or step 1).
8B1), the switching unit 15 is requested to access the DMA
(Step 18A2, Step 1)
8B2). Thereafter, the DMA unit 22 transfers the data from the interface unit 11 to the memory (Step 18A3).
Or step 18B3). Each interface unit 11
When the data transfer requests are simultaneously issued from the DMA, the DMA transfer is performed according to the order set in the priority order setting unit 20 in advance.
The arbitration unit 21 gives the operation permission to each interface unit 11 and controls the switching unit 15 at the same time. For example, if the priority setting unit 20 is set to transfer the interface unit 1 first, and then transfer the interface unit 2, the interface unit 2 waits until the transfer of the interface unit 1 is completed ( that's all,
Step 19, Step 20).

As described above, in the present embodiment, even if data transfer requests from the respective interface units occur at the same time, there is an arbitration function for controlling the operation permission to each of the DMA units according to the contents of the request. Data transfer according to the IEEE 1284 standard can be performed simultaneously using DMA.

[0021]

As described above, according to the present invention, data transfer at two or more interfaces according to the IEEE 1284 standard can be performed simultaneously.

[Brief description of the drawings]

FIG. 1 is a block diagram of an input / output device according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart of an operation of the input / output device according to the first embodiment of the present invention;

FIG. 3 is a block diagram of an input / output device according to Embodiment 2 of the present invention.

FIG. 4 is a flowchart of an operation of the input / output device according to the second embodiment of the present invention;

FIG. 5 is a block diagram of a conventional input / output device.

FIG. 6 is a block diagram of a conventional input / output device.

[Explanation of symbols]

 Reference Signs List 10 input / output terminal 11 interface unit 12 access detection unit 13 access arbitration unit 14 access control unit 15 switching unit 16 memory control unit 17 memory 20 priority setting unit 21 DMA arbitration unit 22 DMA unit

Claims (2)

[Claims] An interface means for performing data transfer according to two or more IEEE 1284 standards, a detecting means for detecting an access request from each interface means, and an arbitration for managing an access right for each access request according to a detection result. And an access control means for determining an access method, wherein when simultaneous access occurs, the access control means and the control order are determined according to the arbitration result. 2. An apparatus comprising two or more DMA transfer means, an arbitration means for managing an access right for each DMA request, and a priority setting means, wherein DMA transfer is performed according to a control order determined by the priority setting means. The input / output device according to claim 1, wherein: