JP2001147418A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit and to improve a yield with respect to a liquid crystal display device integrated with a driver. SOLUTION: A 4-bit shift register 26 and a plurality of gate pulse selection circuits 27 are formed on the outside of a display part 21 of a liquid crystal panel 20. The shift register 26 generates a selection signal based on a signal outputted from a control circuit. Gate pulse selection circuit 27 consist of plural switch circuits, and these switch circuits are turned on by the selection signal to electrically connect wiring where gate pulse signals GP1 to GP192 pass, and a gate bus line. Gate pulse signals GP1 to GP192 are made active in only one horizontal period in turn on a cycle of 192 horizontal synchronizing periods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driver-integrated liquid crystal display device in which a driver circuit is formed integrally with a liquid crystal panel.

[0002]

2. Description of the Related Art A liquid crystal display device is advantageous in that it is thin and lightweight, can be driven at a low voltage, and has low power consumption, and is widely used in various electronic devices. In particular, TF
An active matrix type liquid crystal display device in which active elements such as T (Thin Film Transistor) are provided for each pixel has a CRT (Cathode-Transistor) in view of display quality.
(Ray Tube), and has recently been used for displays of portable televisions, personal computers, and the like.

Generally, a liquid crystal display device has a structure in which liquid crystal is sealed between two transparent substrates. Of the two opposing surfaces (opposing surfaces) of the transparent substrate, an opposing electrode, a color filter, an alignment film and the like are formed on one surface side, and an active matrix circuit and a pixel are formed on the other surface side. An electrode, an alignment film, and the like are formed. Further, a polarizing plate is attached to a surface of each transparent substrate opposite to the facing surface. These two polarizing plates are arranged, for example, such that the polarization axes of the polarizing plates are orthogonal to each other. According to this, a mode in which light is transmitted when no electric field is applied and light is blocked when an electric field is applied, That is, a normally white mode is set. When the polarization axes of the two polarizing plates are parallel, a normally black mode is set.

In recent years, polysilicon TFTs have been used in place of amorphous silicon TFTs. Polysilicon is usually formed by forming an amorphous silicon film on a glass substrate using a plasma CVD method and irradiating the amorphous silicon film with a laser. In the case of an amorphous silicon TFT, the driving speed is low. Therefore, it is necessary to separately prepare a driver integrated circuit for driving pixels (hereinafter referred to as a driver IC) and connect it to a liquid crystal panel. However, the driving speed of a polysilicon TFT is high. The driver circuit can be formed integrally with the liquid crystal panel. Thus, there is an advantage that it is not necessary to prepare a driver IC and the cost of the liquid crystal display device can be reduced.

FIG. 18 is a block diagram showing an example of a conventional driver-integrated liquid crystal display device, and FIG. 19 is a schematic diagram showing the structure of the liquid crystal panel. In this example, X
A liquid crystal display device compatible with GA display (1024 × 768 pixels) will be described. The control circuit 50 includes a data processing circuit 51 and a timing generation circuit 52. The data processing circuit 51 receives image data RGB from a personal computer or the like, performs serial-parallel conversion, and outputs image data D1 to D96 at a predetermined timing. The timing generation circuit 52 outputs the horizontal synchronization signal H-s
ync and a vertical synchronization signal V-sync, and a gate start signal GSI indicating the beginning of one vertical synchronization period, a gate clock GCLK synchronized with the horizontal synchronization signal H-sync and its inverted signal / GCLK, and the beginning of one horizontal synchronization period , And a data clock DCLK indicating the transfer timing of the image data D1 to D96 and its inverted signal / DCLK are generated and output.

[0006] As shown in FIG.
Display unit 61, data driver 62, gate driver 63
It consists of. In this example, 3072 (1024 × 3 (RGB)) pixels 611 are arranged in the horizontal direction and 768 pixels 611 are arranged in the vertical direction. Each pixel 61
1 is provided with a TFT 612 and an auxiliary capacitor 613, respectively. Note that FIG. 19 schematically illustrates the pixel 611, and an actual pixel is configured by a pixel electrode, a counter electrode, and a liquid crystal therebetween.

The display unit 61 has a vertically extending 3.
There are formed 072 data bus lines 614 and 768 gate bus lines 615 extending in the horizontal direction. The TFT 612 has a source connected to the pixel electrode, a drain connected to the data bus line 614, and a gate connected to the gate bus line 615. The data driver 62 includes a 32-bit shift register circuit 64,
It is composed of two buffer circuits 65 and 3072 analog switches 66. Shift register circuit 6
4 is a data start signal DSI and a data clock DCL.
K and / DCLK are input, and selection signals are sequentially output to the 32 buffer circuits 65 based on these signals. In this example, the analog switch 66 is divided into 96 blocks, and the buffer circuit 65 is provided for each block.
And is turned on / off by the output of the buffer circuit 65. One end of the analog switch 66 of each block is connected to the signal lines of the image data D1 to D96, and the other end is connected to the data bus line 614.

The gate driver 63 comprises a 768-bit shift register 67 and 768 buffer circuits 68. The shift register 67 receives the gate start signal GSI and the gate clocks GCLK and / GCLK, and activates each output bit sequentially for one horizontal synchronization period within one vertical synchronization period. The output of the shift register 67 is supplied to each gate bus line 6 via a buffer circuit 65.
14 is supplied as a scanning signal.

FIG. 20 is a timing chart showing the operation of the data driver 62, and FIG. 21 is a timing chart showing the operation of the gate driver 63. As shown in FIG. 21, in the gate driver 63, the shift register circuit 67 is reset by the gate start signal GSI synchronized with the vertical synchronization signal V-sync, and the gate clocks GCLK, / GCLK
76 of the shift register circuit 67 at a timing synchronized with
The eight bit outputs sequentially become “H”, and “H” (scan signal) is sequentially output from the 768 buffer circuits 68. For example, when the output of the first bit of the shift register circuit 67 becomes “H”, the output of the first buffer circuit 68 becomes “H” and is connected to the gate bus line 615 in the first row. 3072 TFTs are turned on.

On the other hand, as shown in FIG. 20, in the data driver 62, the shift register circuit 64 is reset by the data start signal DSI synchronized with the horizontal synchronizing signal H-sync, and at a timing synchronized with the data clocks DCLK and / DCLK. The 32 bit outputs of the shift register 64 sequentially become "H". For example, the first buffer circuit 65
Is transmitted to the buffer circuit 65, the 96 analog switches 66 connected to the buffer circuit 65 are simultaneously turned on, and the image data D1 to D96 are transmitted to the data bus lines 614 in the first to 96th columns. Is transmitted. This gives 1
Image data D1 to D9 are assigned to pixels in the first to 96th columns of the row.
6 is written.

After that, the second bit output of the shift register circuit 64 becomes "H", and the 97th to 1st rows of the first row are output.
The next image data D1 to D96 are written to the pixels in the 92nd column. Thus, the display data is written to each pixel in the first row. In the next horizontal synchronization period, the output of the second bit of the shift register circuit 67 becomes “H”.
, And 3072 TFTs connected to the gate bus line 615 in the second row are turned on. On the other hand, the shift register circuit 64 is reset by the data start signal DSI, and sequentially sets the 32 bit outputs to "H" at the timing synchronized with the data clocks DCLK and / DCLK. As a result, image data is written to 3072 pixels in the second row, as in the case of the first row.

As described above, the image data is written to all the pixels in the display section 61 within one vertical synchronization period, and the image is displayed on the liquid crystal panel. FIG. 22 is a schematic diagram showing another example of a conventional liquid crystal panel. In this example, the shift register circuit 64 of the liquid crystal panel 60 shown in FIG.
In place of 67, decoder circuits 71 and 72 are provided. In FIG. 22, the same components as those in FIG. 19 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The decoder circuit 71 on the data driver side comprises:
The 32 bit outputs are sequentially set to “H” in accordance with the decoder signals DA0 to DA4. These decoder signals DA
0 to DA4 are generated in the control circuit 50 shown in FIG. 18 based on the horizontal synchronization signal H-sync, the vertical synchronization signal V-sync, and the data clocks DCLK and / DCLK. The decoder circuit 72 on the gate driver side supplies the decoder signals GA0 to G
According to A9, 768 bit outputs are sequentially set to “H”. These decoder signals GA0 to GA9 are also shown in FIG.
In the control circuit 50 shown in FIG.
Vertical synchronization signal V-sync and gate clocks GCLK, / GCLK
Is generated based on

FIG. 23 is a circuit diagram showing a configuration of the decoder. However, in FIG. 23, to simplify the description,
It is assumed that decoder signals (address signals) are A0 to A7. As shown in FIG. 23, a large number of logic gates 25 are required to configure a decoder. Normally, the logic gate 25 is constituted by a plurality of CMOSs, that is, a pair of MOS transistors (P-channel transistor and N-channel transistor).

[0015]

In recent years, a liquid crystal display device has been required to have a large screen and a high definition, and accordingly, driver circuits such as a data driver and a gate driver integrally formed on a liquid crystal panel. And the number of elements tends to increase. However, there is a problem that an increase in the degree of integration and an increase in the number of elements cause a decrease in yield.

An object of the present invention is to provide a liquid crystal display device capable of simplifying a circuit and improving a yield.

[0017]

The above object is achieved by forming a plurality of pixels, a data bus line and a gate bus line in a display section, and providing a plurality of gate pulse selection circuits and a plurality of gates outside the display section. A liquid crystal panel on which pulse wiring is formed; and a control circuit for driving the liquid crystal panel. Each of the gate selection circuits includes a gate bus line of a specific group among the plurality of gate bus lines. A plurality of switch circuits are provided between the plurality of gate pulse lines and electrically open and close each gate bus line of the specific group and the gate pulse line according to a selection signal. The problem is solved by a liquid crystal display device.

Hereinafter, the operation of the present invention will be described. In the liquid crystal display device of the present invention, a plurality of gate pulse selection circuits are formed outside the display section of the liquid crystal panel. Each of these gate pulse selection circuits is constituted by a plurality of switch circuits connected between a gate bus line and a gate pulse wiring. When a selection signal is supplied to the gate pulse selection circuit, these switch circuits are turned on, and the gate pulse wiring and the gate bus line are electrically connected.

A gate pulse signal generated by, for example, a control circuit is supplied to the gate pulse wiring, and the gate pulse signal is supplied to a predetermined gate bus line via a gate pulse selection circuit selected by the selection signal. Thereby, the TFT of the pixel connected to the predetermined gate bus line is turned on, and the image data sent via the data bus line is written to the pixel.

The selection signal may be generated by a control circuit, and a circuit for generating the selection signal based on a signal input from the control circuit may be provided outside the display unit of the liquid crystal panel. As such a circuit, for example, a shift register or a decoder can be used. If the gate bus lines are divided into, for example, four groups, the number of outputs of the shift register or the decoder is only 4 bits, so that the configuration of the shift register or the decoder is extremely simple as compared with the related art.

The gate pulse signal may be generated by a control circuit, or a gate driver integrated circuit (general-purpose gate driver IC) may be used. Thereby, the circuit configuration of the liquid crystal panel can be simplified. Further, a data driver integrated circuit (general-purpose data driver IC) may be mounted on the liquid crystal panel, and the data driver integrated circuit may generate image data.

Further, by configuring the gate pulse selection circuit and the analog switch only with transistors having the same polarity (N-type or P-type) as the polarity of the TFT in the display unit,
It is not necessary to manufacture either the P-type transistor or the N-type transistor, and the number of steps for manufacturing the liquid crystal display device can be greatly reduced.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing a liquid crystal panel of the liquid crystal display device. In this example, a liquid crystal display device compatible with XGA display (1024 × 768 pixels) will be described.

This liquid crystal display device comprises a control circuit 10 and a liquid crystal panel 20, and receives image data RGB, a horizontal synchronizing signal H-sync, and a vertical synchronizing signal V-sync from a computer or the like. The control circuit 10 includes a data processing circuit 11 and a timing generation circuit 12. The data processing circuit 11 performs serial / parallel conversion of the image data RGB, and outputs 192 pixels of data (D0 to D0).
192) are output as a group at a predetermined timing. The timing generation circuit 12 outputs the horizontal synchronizing signal H-syn
c and the vertical synchronization signal V-sync, and generates and outputs a data start signal DSI, data clocks DCLK and / DCLK, a gate start signal GSI, gate clocks GCLK and / GCLK, and gate pulse signals GP1 to GP192. The data start signal DSI is a signal indicating the start of one horizontal synchronization period, and the data clocks DCLK and / DCLK are the image data D0 to DCLK.
This signal is synchronized with the 192 output timing. The gate start signal GSI is a signal indicating the beginning of one vertical synchronization period, and the gate clocks GCLK and / GCLK are signals synchronized with the horizontal synchronization signal H-sync. Gate pulse signal GP
1 to GP192 are signals that go to the “H” level sequentially for one horizontal synchronization period in a cycle of 192 horizontal synchronization periods.

The liquid crystal panel 20 includes a display unit 21, a data driver 22, and a gate driver 23. In this example, the display unit 21 displays 3072 in the horizontal direction.
(1024 × 3 (RGB)) pixels and 768 pixels are arranged in the vertical direction. Further, the display section 21 is formed with 3072 data bus lines extending in the vertical direction and 768 gate bus lines extending in the horizontal direction.

As shown in FIG. 2, the data driver 22 includes a 16-bit shift register 24 and 3072 analog switches 25. The shift register 24 receives the data start signal DSI and the data clocks DCLK and / DCLK, and shifts the data (“H”) for each period obtained by dividing one horizontal synchronization period into 16 parts. That is,
Each output bit of the shift register 24 sequentially outputs “H” for each period obtained by dividing one horizontal synchronization period into sixteen.

There are 192 analog switches 25 each having 192 switches.
The common output is supplied from the shift register 24 to the 192 analog switches 25 in the group. For example, the first group (first
The first bit output of the shift register 24 is supplied to the analog switches 25 of the (column to the 192nd column), and when the first bit output is “H”, the analog switches of the first group 25 are all turned on. Similarly, the second group (column 193-
The second bit output of the shift register 24 is supplied to the analog switch 25 of the 384th column).
When the output of the second bit is “H”, all the analog switches 25 in the second group are turned on.
The same applies to other groups of analog switches.

The gate driver 23 includes a 4-bit shift register 26 and four gate pulse selection circuits 27. The shift register 26 receives the gate start signal GSI and the gate clocks GCLK and / GCLK, and shifts the data (“H”) for each period obtained by dividing one vertical synchronization period into four. That is, shift register 2
Each of the output bits 6 outputs “H” sequentially in each period obtained by dividing one vertical synchronization period into four.

The gate pulse selection circuit 27 is composed of 192 switch circuits. These switch circuits are connected between a line to which the gate pulse signals GP1 to GP192 are supplied (hereinafter, referred to as a gate pulse line) and a gate bus line. FIG. 3 is a circuit diagram showing an example of the gate pulse selection circuit 27. However, in FIG. 3, for simplicity of description, each gate pulse selection circuit 27 is assumed to be composed of four switch circuits 31a to 31d, respectively, and is denoted by reference numerals 27a and 27b in order from the upper gate pulse selection circuit 27.

The first gate pulse selecting circuit 27a
The second switch circuit 31a is connected between the gate pulse line GP1 and the first gate bus line GL1. Similarly, the second switch circuit 31b includes a gate pulse line GP2 and a second gate bus line GL2.
And the third switch circuit 31
c is connected between the gate pulse line GP3 and the third gate bus line GL3, and the fourth switch circuit 31d is connected between the gate pulse line GP4 and the fourth gate bus line GL4. Have been.

The second gate pulse selection circuit 27b
The first switch circuit 31a of FIG.
1 and the gate bus line GL5, the second switch circuit 31b is connected between the gate pulse line GP2 and the gate bus line GL6, and the third switch circuit 31c is connected to the gate bus line GL6. The fourth switch circuit 31d is connected between the gate line GP4 and the gate bus line GL8. The fourth switch circuit 31d is connected between the pulse line GP3 and the gate bus line GL7. Hereinafter, the switch circuits 31 of the other gate pulse selection circuits 27 will also be described.
According to this, it is connected between the corresponding gate pulse wiring and the gate bus line.

Each of the switch circuits 31a to 31d has 2
It is composed of two switches SW1 and SW2. The switch SW1 is connected to the gate pulse line GPn (where n is 1, 2, 2,
, 768) and the gate bus line GLn, and the switch SW2 is connected between the gate bus line GLn and the reference potential wiring. The first gate pulse selection circuit 27a is supplied with the first bit output BL1 of the shift register 26, and the second gate pulse selection circuit 27b
Is supplied with the output BL2 of the second bit of the shift register 26. Then, for example, in the first gate pulse selection circuit 27a, the output BL of the first bit of the shift register 26 is output.
When 1 is active (“H” in the figure), switch SW
1 is on, switch SW2 is off, and when output BL1 is inactive ("L" in the figure), switch SW1 is off and switch SW2 is on. Similarly, in the other gate pulse selection circuits 27, when the output of the corresponding bit of the shift register 26 is active, the switch SW
1 turns on and switch SW2 turns off.

FIG. 4 shows the gate pulse selection circuit 2 shown in FIG.
7 is a timing chart showing the operation of FIG. As shown in FIG. 4, the output BL of the first bit of the shift register 26
When 1 is active ("H"), each switch SW1 of the first gate pulse selection circuit 27a is turned on and the switch SW2 is turned on.
Are turned off, and gate pulse signals GP1 to GP4 which sequentially become "H" for each horizontal synchronization period are supplied to the gate bus lines GL1 to GL4 via these switches SW1.

When the output BL2 of the second bit of the shift register 26 becomes active, the switches of the switch circuits 31a to 31d of the second gate pulse selection circuit 27b are switched.
SW1 is turned on and switch SW2 is turned off, and gate pulse signals GP1 to GP4 are supplied to gate bus lines GL5 to GL8 via these switches SW1. FIG. 5 is a circuit diagram showing a specific example (part 1) of the gate pulse selection circuit 27. In the gate pulse selection circuit 27, each of the switch circuits 31a to 31d is composed of two N-channel transistors N1 and N2. The transistor N1 corresponds to the switch SW1 in FIG.
Corresponding to switch SW2.

The first bit output BL1 of the shift register 26 is supplied to the gate of the transistor N1 of the first gate pulse selection circuit 27a, and the inverted first bit / BL1 of the first bit is supplied to the gate of the transistor N2. . Similarly, each transistor N1 of the second gate pulse selection circuit 27b is connected to the output BL2 of the second bit of the shift register 26.
Is supplied to the gate of the transistor N2, and the inverted output / BL2 of the second bit is supplied to the gate of the transistor N2.

FIG. 6 shows the gate pulse selection circuit 27 of FIG.
6 is a timing chart showing the operation of FIG. As shown in FIG. 6, the output BL1 of the first bit of the shift register 26
, / BL1 are active (BL1 = "H", / BL1 = "L")
At this time, all of the transistors N1 of the first gate pulse selection circuit 27a are turned on and all of the transistors N2 are turned off, and the gate pulse signals GP1 to GP4 which become "H" sequentially in each horizontal synchronization period are the transistors. It is supplied to the gate bus lines GL1 to GL4 via N1.

When the outputs BL2 and / BL2 of the second bit of the shift register 26 become active, each transistor N1 of the second gate pulse selection circuit 27b is turned on, and the transistor N2 is turned off. Gate pulse signals GP1 to G are applied to the gate bus lines GL5 to GL8.
P4 is supplied. FIG. 7 shows the gate pulse selection circuit 27.
FIG. 9 is a circuit diagram showing a specific example (No. 2) of FIG. In the gate pulse selection circuit 27, each of the switch circuits 31a to 31d
Are each composed of a P-channel transistor P1 and an N-channel transistor N3. Transistor P1
Corresponds to the switch SW1 in FIG. 3, and the transistor N3 corresponds to the switch SW2 in FIG.

The first bit output BL1 of the shift register 26 is supplied to the transistors P1 and N3 of the first gate pulse selection circuit 27a, and the shift register is supplied to each of the transistors P1 and N3 of the second gate pulse selection circuit 27b. An output BL2 of 26 second bits is provided. FIG. 8 is a timing chart showing the operation of the gate pulse selection circuit 27 of FIG. As shown in FIG. 8, the output BL1 of the first bit of the shift register 26 is active ("L").
At this time, the transistors P1 of the first gate pulse selection circuit 27a are turned on, and the gate pulse signals GP1 to GP4 which sequentially turn to "H" for each one horizontal synchronization period generate gate bus lines GL1 through the transistors P1. ~ GL4.

When the output BL2 of the second bit of the shift register 26 becomes active ("L"), all the transistors N3 of the second gate pulse selection circuit 27b are turned on, and through these transistors N3. Gate pulse signals GP1 to GP4 are supplied to the gate bus lines GL5 to GL8. FIG. 9 is a circuit diagram showing a specific example (part 3) of the gate pulse selection circuit 27. In the gate pulse selection circuit 27, each of the switch circuits 31a to 31d is composed of a CMOS 32 and an N-channel transistor N4. The CMOS 32 corresponds to the switch SW1 in FIG. 3, and the transistor N4 corresponds to the switch SW2 in FIG.

Each C of the first gate pulse selection circuit 27a
One transistor of the MOS 32 has a shift register 2
6, the first bit output BL1 is supplied, and the other transistor of the CMOS 32 and the transistor N4 are supplied with the inverted output / BL1 of the first bit of the shift register 26.
Similarly, the output BL2 of the second bit of the shift register 26 is supplied to one transistor of each CMOS 32 of the second gate pulse selection circuit 27b.
The inverted output / BL2 of the second bit of the shift register 26 is supplied to the other transistor and the transistor N4.

FIG. 10 shows the gate pulse selection circuit 2 of FIG.
7 is a timing chart showing the operation of FIG. This FIG.
, The output of the first bit of the shift register 26
BL1 and / BL1 are active (BL1 = "H", / BL1 =
"L"), the first gate pulse selection circuit 27a
, And all the transistors N4 are turned off, and gate pulse signals GP1 to GP4 which sequentially become "H" for each horizontal synchronization period are supplied to the gate bus lines GL1 to GL4 via the CMOS32. .

When the outputs BL2 and / BL2 of the second bit of the shift register 26 become active, all of the CMOS 32 of the second gate pulse selection circuit 27b are turned on, and all of the transistors N4 are turned off. Gate pulse signal G to the gate bus lines GL5 to GL8.
P1 to GP4 are supplied. In the present embodiment, as shown in FIG. 1 and FIG. 2, the gate driver 23 is constituted by a 4-bit shift register 26.
The structure is extremely simple as compared with a gate driver composed of an 86-bit shift register. Therefore, the liquid crystal display device can be easily manufactured, and the yield can be improved.

(Second Embodiment) FIG. 11 is a block diagram showing a liquid crystal panel of a liquid crystal display device according to a second embodiment of the present invention. 11, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, in the present embodiment, although the signals output from the control circuit are slightly different, the basic configuration of the control circuit is the same as that of the first embodiment, so that the illustration of the control circuit is omitted.

The decoder signals DA0 to DA3 are supplied to the data clocks DCLK and / DCLK in the timing generation circuit of the control circuit.
(See FIG. 1). The decoder circuit 41 sequentially activates the bit output at intervals of dividing one horizontal synchronizing period into 16 by these decoder signals DA0 to DA3. As a result, the analog switches 25 are sequentially turned on for each group, and the image data D1 to D192 are supplied to the data bus lines.

The decoder signals GA0 and GA1 are also signals generated in the timing generation circuit of the control circuit. These signals GA0 and GA1 are signals generated based on the horizontal synchronization signal H-sync. The decoder circuit 42 activates the bit output sequentially in accordance with these signals GA0 and GA1 at intervals of dividing one vertical synchronization period into four equal parts. As a result, the same bit outputs as in the first embodiment are supplied to the four gate pulse selection circuits 27.

The operation of the liquid crystal display device of the present embodiment is the first operation.
This is basically the same as the embodiment. Also in the present embodiment, the number of elements constituting the gate driver is significantly reduced as compared with the related art, and the effect of improving the yield of the liquid crystal display device can be obtained. (Third Embodiment) FIG. 12 is a block diagram showing a liquid crystal panel of a liquid crystal display device according to a third embodiment of the present invention. 12, the same components as those in FIG. 2 are denoted by the same reference numerals, and the detailed description thereof will be omitted. Since the configuration of the control circuit is basically the same as that of the first embodiment, illustration of the control circuit is omitted.

In the present embodiment, the liquid crystal panel 20
A general-purpose driver IC generally used as a drive circuit for an amorphous Si liquid crystal panel
(TAB-IC) 28 is mounted. This driver I
C28 receives the gate start signal GSI and the gate clocks GCLK and / GCLK from the control circuit, and generates gate pulse signals GP1 to GP192 which sequentially become "H" level for one horizontal synchronization period in a cycle of 192 horizontal synchronization periods. Output.

Further, in the present embodiment, a gate pulse selection circuit 27 is provided in the liquid crystal panel 20 as in the first embodiment. The gate pulse selection circuit 27 outputs a bit output from the 4-bit shift register 26.
BL1 to BL4 are input. The configuration and operation of the gate pulse selection circuit 27 are the same as in the first embodiment, and a description thereof will not be repeated.

In this embodiment, the general-purpose driver IC 28
To generate the gate pulse signals GP1 to GP192, there is no need to generate these signals in the timing generation circuit in the control circuit. In addition to the effect obtained in the first embodiment, There is an advantage that the circuit configuration of the control circuit 20 is simplified. (Fourth Embodiment) FIG. 13 is a block diagram showing a liquid crystal panel of a liquid crystal display device according to a fourth embodiment of the present invention. 13, the same components as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof will be omitted. Also in this embodiment, although the signals output from the control circuit are slightly different, since the basic configuration of the control circuit is the same as that of the first embodiment, illustration of the control circuit is omitted.

In the present embodiment, the liquid crystal panel 20
And a selection signal BL1 to BL4 is generated by a timing generation circuit of a control circuit. These selection signals BL1 to BL4 are generated based on the gate start signal GSI and the gate clocks GCLK and / GCLK. The selection signals BL1 to BL4 generated by the timing generation circuit are supplied to the gate pulse selection circuit 27 of the liquid crystal panel 20 via wiring.

In the present embodiment, the shift register on the gate driver side is not required, so that the circuit configuration of the liquid crystal panel 20 is extremely simplified. (Fifth Embodiment) FIG. 14 is a block diagram showing a liquid crystal panel of a liquid crystal display device according to a fifth embodiment of the present invention. 14, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Also in this embodiment, although the signals output from the control circuit are slightly different, since the basic configuration of the control circuit is the same as that of the first embodiment, illustration of the control circuit is omitted.

In this embodiment, the timing generation circuit in the control circuit generates the data block selection signals BLD1 to BLD16 based on the gate start signal GSI and the data clocks DCLK and / DCLK, and generates the gate start signal.
The gate block selection signals BLG1 to BLG4 and the gate pulse signal GP1 are determined based on the GSI and the gate clocks GCLK and / GCLK.
Generate ~ GP192. Data block selection signals BLD1 to BL
D16 is a signal that becomes active in order every 1/16 of one horizontal synchronization period. Further, the gate block selection signals BLG1 to BLG4 are signals that become active sequentially in each quarter period of one vertical synchronization period. Further, the gate pulse signals GP1 to GP192 are signals which are sequentially activated for one horizontal period within one quarter of one vertical synchronization period.

FIG. 15 is a circuit diagram showing an example of the analog switch 25. In the example shown in FIG. 15, one analog switch is constituted by one CMOS 33. For example, the N of 192 CMOS33s in the first block
The block selection signal BL1 is supplied to the channel transistor, and the block selection signal / B is supplied to the P-channel transistor.
L1 is supplied. Hereinafter, similarly, the n-th block (where n =
The block selection signal BLn is supplied to the N-channel transistors of the CMOS 33 (2, 3,..., 16), and the block selection signal / BLn is supplied to the P-channel transistors.

FIG. 16 is a circuit diagram showing another example of the analog switch 25. In the example shown in FIG. 16, one analog switch is constituted by one transistor 34 (N-channel transistor or P-channel transistor). The block selection signal BL1 is supplied to the 192 transistors 34 of the first block, and the block selection signal BL1 is supplied to the transistor 34 of the second block.
2 is supplied. Similarly, a corresponding block selection signal is supplied to the transistor 34 of each block.

Generally, the TFT in the display section 21 is constituted by an N-channel transistor. Therefore, the analog switch 25 is constituted only by the N-channel transistor as shown in FIG. When the switch circuit of the selection circuit 27 is also configured with only N-channel transistors, there is no need to form P-channel transistors on the liquid crystal panel 20. This produces an effect that the manufacturing process is significantly reduced.

When the analog switch 25 is formed of a P-channel transistor, and the TFT in the display unit 21 and the switch circuit in the gate pulse selection circuit 27 are formed of a P-channel transistor, the process of forming the N-channel transistor is omitted. This is unnecessary, and the manufacturing process is greatly reduced as in the above-described example. (Sixth Embodiment) FIG. 17 is a block diagram showing a configuration of a liquid crystal panel of a liquid crystal display device according to a sixth embodiment of the present invention. 17, the same components as those in FIG. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted. Also in this embodiment, although the signals output from the control circuit are slightly different, since the basic configuration of the control circuit is the same as that of the first embodiment, illustration of the control circuit is omitted.

In the present embodiment, the data generation circuit of the control circuit generates the data block selection signals BLD1 to BLD16.
, And generates gate block selection signals BLG1 to BLG4. In the present embodiment, a general-purpose data driver IC 43 and a general-purpose gate driver IC 44 are mounted on the terminal of the liquid crystal panel 20. Driver IC 43
Receives RGB image data, a data start signal DSI and data clocks DCLK and / DCLK from a control circuit, performs serial / parallel conversion, and outputs 192 bits of data D1.
To D192 at a predetermined timing. Further, the driver IC 44 receives the gate start signal GSI and the gate clocks GCLK and / GCLK from the control circuit, and outputs gate pulse signals GP1 to GP192.

In the present embodiment, the liquid crystal panel 21
Becomes extremely simple. Further, by forming the TFT, the analog switch 25, and the gate pulse selection circuit 27 in the display unit 21 only with the N-channel transistor (or the P-channel transistor), the process of forming the P-channel transistor (or the N-channel transistor) is performed. Becomes unnecessary, and the manufacturing cost can be greatly reduced.

[0059]

As described above, according to the present invention,
A plurality of gate pulse selection circuits selected by a selection signal are formed outside the display section of the liquid crystal panel, and a switch circuit in these gate pulse selection circuits electrically connects a gate pulse line and a gate bus line. Since the driver is opened and closed, the circuit configuration of the driver integrally formed on the liquid crystal panel is simplified, and the yield can be improved. Further, by forming the gate pulse selection circuit and the analog switch only with transistors having the same polarity (N-type or P-type) as the polarity of the TFT in the display portion, one of the P-type transistor and the N-type transistor is manufactured. This eliminates the necessity and significantly reduces the number of manufacturing steps for the liquid crystal display device.

Further, by mounting the gate driver integrated circuit and the data driver integrated circuit on the liquid crystal panel, the circuit configuration of the liquid crystal panel can be further simplified, and the manufacturing cost can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a liquid crystal panel of the liquid crystal display device according to the first embodiment.

FIG. 3 is a circuit diagram illustrating an example of a gate pulse selection circuit.

FIG. 4 is a timing chart showing an operation of the gate pulse selection circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing a specific example (part 1) of the gate pulse selection circuit.

FIG. 6 is a timing chart showing an operation of the gate pulse selection circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a specific example (part 2) of the gate pulse selection circuit.

FIG. 8 is a timing chart showing an operation of the gate pulse selection circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a specific example (part 3) of the gate pulse selection circuit.

FIG. 10 is a timing chart illustrating an operation of the gate pulse selection circuit of FIG. 9;

FIG. 11 is a block diagram illustrating a liquid crystal panel of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a liquid crystal panel of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 13 is a block diagram illustrating a liquid crystal panel of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram illustrating a liquid crystal panel of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating an example of an analog switch.

FIG. 16 is a circuit diagram showing another example of the analog switch.

FIG. 17 is a block diagram illustrating a configuration of a liquid crystal panel of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 18 is a block diagram showing an example of a conventional driver-integrated liquid crystal display device.

FIG. 19 is a schematic view similarly showing the configuration of the liquid crystal panel.

FIG. 20 is a timing chart illustrating the operation of the data driver in FIG. 19;

FIG. 21 is a timing chart illustrating the operation of the gate driver of FIG. 19;

FIG. 22 is a schematic diagram showing another example of a conventional liquid crystal panel.

FIG. 23 is a circuit diagram showing a configuration of the decoder of FIG. 22;

[Explanation of symbols]

 10, 50 control circuit, 11, 51 data processing circuit, 12, 52 timing generation circuit, 20, 60 liquid crystal panel, 21, 61 display unit, 22, 62 data driver, 23, 63 gate driver, 24, 26, 64, 67 shift register, 25, 65 analog switch, 27 gate pulse selection circuit, 28, 43, 44 driver IC, 31a to 31d switch circuit, 41, 42, 71, 72 decoder circuit, 614 data bus line, 615 gate bus line.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA16 NC10 NC12 NC21 NC22 NC34 NC49 ND49 ND53 5C006 AF42 BB16 BC03 BC12 BC20 BF03 BF24 BF26 EB04 EB05 FA41 5C080 AA10 BB05 DD22 DD28 FF11 JJ02 JJ03 JJ03 JJ04

Claims (5)

[Claims] 1. A plurality of pixels, a data bus line and a gate bus line are formed in a display section, and a plurality of gate pulse selection circuits and a plurality of gate pulse wirings through which gate pulse signals pass are formed outside the display section. And a control circuit for driving the liquid crystal panel, wherein each of the gate selection circuits includes a gate bus line of a specific group among the plurality of gate bus lines and the plurality of gates. Provided between the pulse wiring
A liquid crystal display device comprising: a plurality of switch circuits that electrically open and close between each gate bus line of the specific group and the gate pulse wiring according to a selection signal. 2. The liquid crystal panel according to claim 1, further comprising:
2. The liquid crystal display device according to claim 1, wherein a circuit that generates the selection signal based on a signal input from the control circuit is formed. 3. The liquid crystal display device according to claim 1, wherein the selection signal is generated by the control circuit and supplied to the liquid crystal panel. 4. A gate driver integrated circuit mounted outside the display section of the liquid crystal panel to generate the gate pulse signal based on a signal input from the control circuit. 3. The liquid crystal display device according to 1. 5. The liquid crystal panel, outside the display section,
2. An image data line through which image data passes, and an analog switch connected between the image data line and the data bus line are formed.
3. The liquid crystal display device according to 1.