JP2000131708A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inspect the characteristic of thin film transistors(TFTs) being used without taking apart a liquid crystal display panel, that uses the TFTs, when an abnormality occurs by providing a control circuit section having inspection terminals to which signals outputted from a driver circuit are supplied. SOLUTION: A data shift out signal DSO is outputted from the last stage of a shift register of a data driver circuit 32 of a liquid crystal display panel 30. A gate shift out signal GSO is outputted from the last stage of the shift register of a gate driver circuit 33. These signals are transmitted to inspection terminals 44 and 45 of a timing generation circuit 41 of a control circuit section 40 through terminal electrodes 34 and 43 and a flexible table. After having completed a product assembly, the probe of an inspection device is connected to the terminals 44 and 45 in order to inspect the presence or the absence of the degradation of the TFTs that constitute the shift registers under an actually operating condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a peripheral circuit integrated type active matrix liquid crystal display device having a plurality of pixels and a driver circuit on the same substrate.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a switch which is turned off when not selected and cuts off a signal in each pixel to prevent crosstalk. It shows excellent display characteristics as compared with. In particular, T as a switch
A liquid crystal display device using an FT (Thin Film Transistor) has a high TFT driving capability.
It has excellent display characteristics comparable to a CRT (Cathode-Ray Tube).

Generally, a liquid crystal display device has a structure in which liquid crystal is sealed between two transparent substrates. Of the two surfaces (opposing surfaces) of the transparent substrate facing each other, a counter electrode, a color filter, an alignment film, and the like are formed on one surface side, and a TFT, a pixel electrode, and an alignment film are formed on the other surface side. A film or the like is formed. Further, a polarizing plate is attached to a surface of each transparent substrate opposite to the facing surface. These two polarizing plates are arranged, for example, such that the polarization axes of the polarizing plates are orthogonal to each other. According to this, a mode in which light is transmitted when no electric field is applied and light is blocked when an electric field is applied, That is, a normally white mode is set. On the contrary, when the polarization axes of the two polarizing plates are parallel, a normally black mode is set. Hereinafter, the transparent substrate on which the TFT and the pixel electrode are formed is referred to as a TFT substrate, and the transparent substrate on which the counter electrode and the like are formed is referred to as a counter substrate.

In recent years, TFTs using thin-film polysilicon formed by a low-temperature process have been developed and used in liquid crystal display devices. When a TFT is formed by a low-temperature process, there is an advantage that an inexpensive glass substrate can be used as a transparent substrate. Further, since the polysilicon TFT has a higher driving capability and can be miniaturized as compared with the amorphous silicon TFT, there is an advantage that the aperture ratio is improved and a bright image can be obtained. Further, in the case of the amorphous silicon TFT, since the driving speed is slow, it was necessary to separately prepare a driving IC and connect it to the liquid crystal display device.
Since the driving speed of the polysilicon TFT is high, a driving (driver) circuit can be formed on a glass substrate.

[0005]

In a liquid crystal display device using a TFT formed by a low-temperature process, data relating to reliability is not sufficiently accumulated, and as the time elapses, T
It has also been reported that the characteristics of FT deteriorate.
If the performance of the liquid crystal display device decreases with use,
It is important to investigate the cause, such as whether the cause is deterioration of the TFT characteristics or the manufacturing process, and take measures. However, conventionally, it is necessary to disassemble the liquid crystal display panel in order to find the cause, and there is a problem that it takes time and effort.

In order to examine the degree of TFT deterioration, it is conceivable to form several TFTs outside the display area of the TFT substrate independently of other circuits. At the time of inspection, a current is supplied to these TFTs, and the degree of deterioration of the TFTs can be known by checking the state of signals output from the TFTs. However, since no current flows through these TFTs in a normal use state, the T
It is not sufficient as a method for examining the degree of FT deterioration.

An object of the present invention is to provide a liquid crystal display panel which is actually used without disassembling when an abnormality occurs.
An object of the present invention is to provide a liquid crystal display device capable of examining the characteristics of the FT and quickly and easily determining the cause.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a plurality of pixels arranged in a matrix and a driver which is arranged outside a region where the plurality of pixels are arranged and supplies signals to the plurality of pixels. A control comprising: a liquid crystal display panel having a circuit formed on the same substrate; an electronic circuit for supplying a signal to the driver circuit; and an inspection terminal to which at least one of signals output from the driver circuit is supplied. The problem is solved by a liquid crystal display device having a circuit portion.

The operation will be described below. In the present invention, the control circuit section is provided with an electronic circuit that supplies a signal to a driver circuit of the liquid crystal display panel, and an inspection terminal to which at least one of the signals output from the driver circuit is supplied. By connecting a probe of an inspection device to the inspection terminal and examining a signal waveform or the like, the TFT of the liquid crystal display panel can be displayed without disassembling the liquid crystal display panel.
The degree of deterioration can be known.

Generally, a shift register is provided in a driver circuit of a liquid crystal display device. For example, the threshold value of the TFT may change due to deterioration. In this case, the signal output from the last stage of the shift register is superimposed on the degree of deterioration of the transistor in each stage, and the signal waveform or level greatly changes. . Therefore, if the signal output from the last stage of the shift register is supplied to the inspection terminal, the deterioration of the transistor can be known easily and with high accuracy.

The signal output from the driver circuit may be supplied to an inspection terminal via an inverter or a logic circuit.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a sectional view of a display area of a liquid crystal display panel of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a plan view thereof.

The liquid crystal display panel 30 includes a TFT substrate 10 and a counter substrate 20 which are disposed to face each other, and
It is composed of a liquid crystal 29 sealed between the substrate 10 and the counter substrate 20. The TFT substrate 10 includes a glass substrate 11, a gate bus line 12, a data bus line 13, a pixel electrode 14, and a TF formed on the glass substrate 11.
It is composed of T15 and the like. The gate bus line 12 and the data bus line 13 intersect at right angles, and are electrically insulated by an insulating film (not shown) formed therebetween. These gate bus lines 12 and data bus lines 13 are formed of a conductor such as aluminum. The TFT 15 includes a polysilicon film 16 selectively formed on the glass substrate 11 and a gate bus line 13 passing over the polysilicon film 16. Polysilicon film 16 and gate bus line 13
Between them, a gate insulating film (not shown) for insulating them from each other is formed. The TFT 15 is formed by a low-temperature process. That is, the polysilicon film 16 is formed on the glass substrate 11 by CVD (Chem).
An amorphous silicon film is formed by an ical vapor deposition (chemical vapor deposition) method, and the amorphous silicon film is formed by irradiating the amorphous silicon film with laser light to change the amorphous into polysilicon.

Each rectangular area defined by the gate bus line 12 and the data bus line 13 is a pixel. Each pixel has its own indium-tin oxid
e: hereinafter, referred to as ITO)
Are formed. The source of the TFT 15 is electrically connected to the pixel electrode 14 via a contact hole (not shown), and the drain is electrically connected to the data bus line 13 via another contact hole (not shown). ing.

On these pixel electrodes 14, an alignment film 17 made of, for example, polyimide is formed. The surface of the alignment film 17 is subjected to an alignment process in order to determine the alignment direction of the liquid crystal molecules when no voltage is applied. As a typical method of the alignment treatment, a rubbing method in which a surface of an alignment film is rubbed in one direction by a cloth roller is known.

On the other hand, the opposite substrate 20 is a glass substrate 21
And a color filter 22, a black matrix 23, a counter electrode 24, an alignment film 25, and the like formed on the lower surface side of the glass substrate 21. Color filter 22
Includes three types of red (R), green (G), and blue (B).
Are facing each other. A black matrix 23 is formed between these color filters 22. The black matrix 23 is made of a metal thin film that does not transmit light, such as chrome (Cr).

Below the color filter 22 and the black matrix 23, a transparent counter electrode 24 made of ITO is formed. Under the counter electrode 24, an alignment film 25 is provided.
Are formed. The surface of the alignment film 25 is also subjected to an alignment process. A spherical spacer (not shown) is arranged between the TFT substrate 10 and the opposing substrate 20, so that the distance between the TFT substrate 10 and the opposing substrate 20 is kept constant. Also, the TFT substrate 10 and the opposite substrate 20
A polarizing plate (not shown) is arranged on each of the. These polarizing plates are arranged so that the polarization axes are orthogonal to each other.

When a data signal is supplied to the data bus line 13 and a scanning signal is supplied to the gate bus line 12, T
The FT 15 is turned on, and a data signal is supplied to the pixel electrode 14. As a result, an electric field is generated between the pixel electrode 14 and the counter electrode 24. The liquid crystal molecules in the liquid crystal 29 are arranged along the electric field, and the light transmittance of the pixel changes. By controlling the voltage applied to the pixel electrode 14 for each pixel, a desired image can be displayed on the liquid crystal display panel 30.

FIG. 3 is a block diagram showing a circuit configuration of the liquid crystal display device of the present embodiment. This liquid crystal display device includes a liquid crystal display panel 30 and a control circuit unit 40. Then, the liquid crystal display panel 30 and the control circuit unit 40
Are electrically connected by a flexible cable (not shown). The liquid crystal display panel 30 has a display area 31 in which a plurality of pixels are arranged as shown in FIG. 2, a data driver circuit 32 and a gate driver circuit 33 arranged outside the display area 31, and a terminal electrode 34. . The data driver circuit 32, the gate driver circuit 33, and the terminal electrode 34 are all formed on the glass substrate 11, and the TFTs forming the data driver circuit 32 and the gate driver circuit 33 are different from the TFTs in the display area 31. It was formed at the same time. Further, between the terminal electrode 34 and the data driver circuit 32 and the gate driver circuit 33, the data driver circuit 32 and the display area 31
The data bus line 13 and the gate driver circuit 33 and the gate bus line 12 in the display area 31 are connected by the wiring formed simultaneously with the data bus line 13 or the gate bus line 12. Details of the data driver circuit 32 and the gate driver 33 will be described later.

The control circuit section 40 includes a timing generation circuit 4
1. It is composed of a data forming circuit 42 and a terminal electrode 43. The control circuit unit 40 receives R (red), G (green), and B from a video output device such as a personal computer.
(Blue) signal, the vertical synchronizing signal Vs and the horizontal synchronizing signal Hs.
Is input. From the vertical synchronizing signal Vs and the horizontal synchronizing signal Hs, the timing generation circuit 41 converts the data clock signal DCLK, the data clock inversion signal / DCLK, the data start signal DSI, the gate clock signal GCLK, the gate clock inversion signal / GCLK, and the gate start signal GSI. Is generated and output. The data start signal DSI is a signal indicating the start of one horizontal synchronization period, and the gate start signal GSI is 1
This signal indicates the start of the vertical synchronization period.

The timing generation circuit 41 is provided with terminals 44 and 45 for inspection. These terminals 4
The data shift-out signal DSO and the gate shift-out signal GSO are transmitted from the liquid crystal display panel 30 to 4, 45. When examining the degree of TFT deterioration, a probe of an inspection device is connected to these terminals 44 and 45.

The data forming circuit 42 receives the R, G, and B signals from the video display device, and outputs the horizontal synchronizing signal Hs and the data clock signal DCLK from the timing generating circuit 41.
And a data clock inversion signal / DCLK to generate data signals D _{1 to} D _N (N is the number of pixels in the horizontal direction) for one horizontal synchronization period, and output them in parallel at a timing synchronized with the horizontal synchronization signal Hs. .

A flexible cable connecting the liquid crystal display panel 30 and the control circuit unit 40 is joined to the terminal electrodes 34 and 43. FIG. 4 is a block diagram showing a configuration of the data driver circuit 32 and the gate driver circuit 33 of the liquid crystal display panel. The data driver circuit 32
The data signals D _{1 to} D _N are input from the data forming circuit 42 and the data start signal DSI, the data clock signal DCLK, and the data clock inverted signal / DCLK (hereinafter, these two signals are referred to as “data clock signal DCLK”). , / DCLK "hereinafter) is input, the data clock signal DCLK, at a timing synchronized with the / DCLK, and outputs the data signal D ₁ to D _N sequentially to each data bus line a ₁ to a _N of the display area 31.

The gate driver circuit 33 receives a gate start signal GSI, a gate clock signal GCLK, and a gate clock inversion signal / GCLK (hereinafter, referred to as "GCLK") from the timing generation circuit 41.
These two signals are referred to as “gate clock signals GCLK, / GCLK
), And the scanning signals are sequentially supplied to the gate bus lines G _{1 to} G _M of the display area 31 in synchronization with the gate clock GCLK.

As shown in FIG. 4, the data driver circuit 3
Reference numeral 2 denotes an N-stage (N is the number of pixels in the horizontal direction) shift register 51, a buffer circuit 52, a data signal line 53, and an analog switch circuit 54. Upon input of the data start signal DSI, the shift register 51 sets "1" as data in the first stage, and shifts the data at a timing synchronized with the data clock signals DCLK and / DCLK. As a result, the N signal lines Q _{1 to} Q _N of the shift register 51 sequentially become “1”. In this case, one of the N signal lines Q _{1 to} Q _N is “1”, and the other signal lines are “0”. Then, the data shift-out signal DSO is output from the shift register 51 by the (N + 1) th clock from the data start signal DSI.

From the shift register 51, the signal lines Q _{1 to} Q _N
Is output to the analog switch circuit 54 via the buffer circuit 52. The analog switch circuit 54 includes N sets of analog switch elements T
_{1 to} T _N. The gates of the analog switch elements T _{1 to} T _N are connected to the buffer circuit 52,
_{One of} the data signals D _{1 to} D _N output from the data forming circuit 42 is supplied to the source via the data line 53, and the drain is the data bus line A of the display area 31.
It is connected to ₁ to A _N. These analog switch elements T _{1 to} T _N are turned on when “1” is given to the gate, and turned off when “0”.

On the other hand, the gate driver circuit 33 includes an M-stage (M is the number of pixels in the vertical direction) shift register 55 and a buffer circuit 56. When the shift register 55 receives the gate start signal GSI, the shift register 55 sets “1” as data in the first stage, and sets the gate clock signal GC
Data is shifted at the timing synchronized with LK and / GCLK. In this case, only one of the M output lines of the shift register 55 is “1”, and the other is “0”. Then, the shift register 55 outputs the gate shift-out signal GSO with the (M + 1) th clock from the gate start signal GSI. The data (“1”) output from the shift register 55 is used as a scanning signal as a scanning signal in the buffer circuit 56.
To the gate bus lines G _{1 to} G _M ).

The liquid crystal display device of the present embodiment supplies the data shift-out signal SIO and the gate shift-out signal GSO output from the last stage of the shift registers 51 and 55 to the test terminals 44 and 45 of the control circuit unit 40. Except for forming the wiring to be formed, it can be manufactured basically in the same manner as in the conventional case. Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

The control circuit section 40 receives a horizontal synchronizing signal Hs and a vertical synchronizing signal Vs from a display device such as a personal computer.
And data signals D _{1 to} D _N , a data start signal DSI, data clock signals DCLK and / DCLK, a gate start signal GSI, and gate clock signals GCLK and / GCLK are generated from these signals. And output. The data signals D _{1 to} D _N , the data start signal DSI, and the gate clock signals GCLK and / GCLK are output at timing synchronized with the horizontal synchronization signal Hs, and the gate start signal GSI is output at timing synchronized with the vertical synchronization signal.

After inputting the gate start signal GSI, the shift register 55 of the gate driver circuit 33 sets the gate bus line G ₁ of the first row to “1” by the pulse of the first gate clock signal GCLK, / GCLK. The other gate bus lines G _{2 to} G _N are set to “0”. On the other hand, after inputting the data start signal DSI, the shift register 51 receives the first data clock signal DCLK and / DCLK pulse,
A signal line Q ₁ is set to "1", and other signal lines Q ₂ ~Q _N "0". Thereby, the analog switch element T ₁
There turned on, the data signal D ₁ to the data bus lines A ₁
Is supplied. Therefore, the data signal D ₁ is supplied to the pixel electrode of the pixel in the first row and the first column of the display area, and the light transmittance of the pixel becomes a value corresponding to the data signal D ₁ .

Next, the data clock signals DCLK and / DCLK are
The shift register 51 shifts by the second pulse.
Work, signal line Q_TwoIs “1” and other signal lines Q₁, Q_Three
~ Q _NBecomes “0”. This enables analog switches
Element T_TwoIs on, analog switch element T₁, T_Three~ T
_NIs turned off, and the data signal D is applied to the pixel in the first row and the second column._TwoBut
Supplied. Therefore, the image of the pixel in the first row and second column of the display area is
Data signal D to the element electrode _TwoIs supplied, and the light transmission of the pixel is
Rate is data signal D_TwoWill be a value corresponding to.

As described above, the data signals are sequentially supplied to the pixels in the first row, and the image in the first row is generated. Then, the data shift-out signal DSO is output from the shift register 51 by the (N + 1) th pulse of the data clock signals DCLK and / DCLK. This data shift out signal
DSO is transmitted to the inspection terminal 44 of the timing generation circuit 41 via the terminal electrode 34, the flexible cable, and the terminal electrode 43. This data shift-out signal DSO is a signal used only at the time of inspection, and does not affect the operation of a normal liquid crystal display device.

When one horizontal synchronization period ends, the data forming circuit 42 updates the data signals D _{1 to} D _N. Also, 1
When the horizontal synchronization period ends, the gate clock signals GCLK and / GCLK are supplied to the shift register 55 of the gate driver circuit 33.
Is supplied. Thus, shift register 55 is a shift operation, the gate bus line G ₂ is "1", the other gate bus lines G _1, G ₃ ~G _M becomes "0". Further, the data start signal DSI is supplied to the shift register 51 of the data driver circuit 32. As a result, the shift register 5
1 is a sequential "1" to signal line Q ₁ to Q _N at a timing synchronized with the data clock signal DCLK, / DCLK. In this manner, the data signals D _{1 to} D _N are sequentially applied to each pixel in the second row.
Is supplied, and an image on the second line is generated.

The above operation is performed for the M-th gate bus line G.
_{The process is} repeated up to _M to display an image for one screen. Thereafter, a gate shift-out signal GSO is output from the shift register 55 by the (M + 1) th pulse of the gate clock signals GCLK and / GCLK. The gate shift-out signal GSO is transmitted to the inspection terminal 45 of the timing generation circuit 41 via the terminal electrode 34, the flexible cable, and the terminal electrode 43. This gate shift out signal GSO
Is a signal used only at the time of inspection, and does not affect the operation of a normal liquid crystal display device.

When one vertical synchronization period is completed, the data forming circuit 42 updates the data signals D _{1 to} D _N , and synchronizes with the next data start signal DSI, gate start signal GSI, and data clock signals DCLK and / DCLK. in and outputs these data signals D ₁ to D _N. In this way, images are sequentially displayed in the display area. In the present embodiment, the shift register 5 of the data driver circuit 32
The data shift-out signal DSO is output from the final stage of the first stage, and the gate shift-out signal GSO is output from the final stage of the shift register 55 of the gate driver circuit 33. These signals are transmitted to the test terminals 44 and 45 of the timing generation circuit 41 via the terminal electrodes 34 and 43 and the flexible cable.

After assembling the product, a probe of an inspection device is connected to these terminals 44 and 45, and the shift registers 51 and 45 are connected.
Whether or not the TFT constituting the TFT 55 has deteriorated can be inspected in a state where the TFT is actually operating. FIG. 5 (a)
FIG. 5 is a diagram showing the waveform of the output pulse of the first stage of the shift register 51, and FIGS. 5B and 5C are diagrams showing the pulse waveform of the data shift-out signal DSO. Assuming that the time of one cycle of the data clock signals DCLK and / DCLK is T, T (N +
1) After a time, the data shift-out signal DSO becomes "1". In the example shown in FIG. 5B, the data shift-out signal
DSO level has not changed. This indicates that the characteristics of the TFT are good. On the other hand, in the example shown in FIG. 5C, the H level voltage (Vc) of the data shift signal DSO decreases and the L level voltage (0 V) increases. This is because the threshold value of the transistor shifts (negative side for N-channel transistor, positive side for P-channel transistor)
This is a phenomenon that often occurs when a through current of 0 V flows, and occurs because the power supply voltage decreases and the ground potential increases as the number of stages of the shift register increases.

As described above, in the present embodiment, the waveform of the waveform is observed by connecting the probe of the inspection apparatus to the inspection terminals 44 and 45 provided in the timing generation circuit 41.
The degree of deterioration of the TFT of the liquid crystal display panel 30 can be checked. In this case, there is no need to disassemble the liquid crystal display panel, and data can be collected quickly and easily. In addition, since the degree of deterioration of the transistor can be known in a state where the transistor is actually used, the reliability of the inspection is high. In particular, the characteristics of a TFT formed by a low-temperature process may be deteriorated when used for a long time, and it is difficult to determine whether the TFT is or is not the cause of the performance deterioration of the liquid crystal display device. According to the above embodiment, T
Since the degree of FT characteristic deterioration can be determined without disassembling the liquid crystal display panel, it contributes to improvement in reliability of the liquid crystal display device.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
FIG. 3 is a block diagram showing a liquid crystal display panel of the liquid crystal display device according to the embodiment. 6, the same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, since the configurations of the data driver circuit 32 and the gate driver circuit 33 are the same as those of the first embodiment, they will be described with reference to FIG.

In this embodiment, the data shift-out signal DSO and the gate shift-out signal GSO output from the shift registers 51 and 55 of the data drivers 32 and 33 are output from the inverters 61 and 6 formed on the TFT substrate.
2, and transmitted to the inspection terminals 44 and 45 of the control circuit unit 40. Also in this embodiment, as in the first embodiment, the degree of deterioration of the TFT formed on the TFT substrate can be checked without disassembling the liquid crystal display panel. In addition, the inverter 61,
A logic circuit may be provided instead of 62.

In the first and second embodiments, the case where both the data driver circuit 32 and the gate driver circuit 33 are provided in the liquid crystal display panel 30 has been described. The present invention can be applied to a case where one of the driver circuit and the gate driver circuit is provided in the control circuit portion.

[0041]

As described above, according to the present invention,
Since at least one of the signals output from the driver circuit provided in the liquid crystal display panel is supplied to the inspection terminal provided in the control circuit portion, the state of the deterioration of the transistor formed in the liquid crystal display panel is disassembled. You can easily find out without doing it. As a result, it is possible to quickly clarify the cause of the abnormality of the liquid crystal display device after manufacturing and to take a countermeasure, thereby greatly contributing to the improvement of the reliability and productivity of the liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a sectional view of a display area of a liquid crystal display panel of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the same.

FIG. 3 is a block diagram illustrating a circuit configuration of the liquid crystal display device according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of a data driver circuit and a gate driver circuit of the liquid crystal display device.

FIG. 5 is a diagram illustrating an example of output waveforms of a first stage and a last stage of a shift register.

FIG. 6 is a block diagram illustrating a liquid crystal display panel of a liquid crystal display device according to a second embodiment of the present invention.

[Explanation of symbols]

10 TFT substrate, 12, G ₁ ~G _M gate bus line, 13 A ₁ to A _N data bus lines, 14 pixel electrodes, 15 TFT, 16 polysilicon film, 20 counter substrate 29 liquid crystal 30 liquid crystal display panel, 31 Display area, 32 data driver circuit, 33 gate driver circuit, 40 control circuit section, 41 timing generation circuit, 42 data formation circuit, 51, 55 shift register, 52, 56 buffer circuit, 53 data signal line, 54 analog switch circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA50 JA25 JA29 JA38 JA42 JB77 KA04 KA07 KB14 MA07 MA30 MA56 NA13 NA25 NA30 PA08 5G435 AA14 AA17 BB12 CC09 EE30 EE33 KK05

Claims (4)

[Claims] 1. A plurality of pixels arranged in a matrix and a driver circuit arranged outside an area in which the plurality of pixels are arranged and supplying signals to the plurality of pixels are formed on the same substrate. A liquid crystal display panel, an electronic circuit for supplying a signal to the driver circuit, and a control circuit unit including a test terminal to which at least one of the signals output from the driver circuit is supplied. Liquid crystal display device. 2. The driver circuit of the liquid crystal display panel includes a shift register, and a signal output from a last stage of the shift register is supplied to the inspection terminal of the control circuit unit. The liquid crystal display device according to claim 1. 3. The liquid crystal display panel has an inverter or a logic circuit formed on the substrate, and at least one of signals output from the driver circuit is supplied to the control circuit unit via the inverter or the logic circuit. 2. The liquid crystal display device according to claim 1, wherein said liquid crystal display device is supplied to said inspection terminal. 4. The liquid crystal display panel has an inverter or a logic circuit formed on the substrate, and the driver circuit of the liquid crystal display panel has a shift register, and outputs from a last stage of the shift register. The signal obtained is supplied to the inspection terminal of the control circuit section via the inverter or a logic circuit.
3. The liquid crystal display device according to 1.