JP2001144726A - Multi-carrier reception system and synchronous circuit for receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect synchronous timing with high accuracy in a multi-carrier communication system having a guard interval. SOLUTION: A synchronizing signal detection circuit 100 outputs a synchronizing signal ST from a common-mode signal I and an orthogonal signal Q being outputs of an orthogonal detection circuit 200. The circuit 100 consists of a delay circuit 11, n pieces of phase rotation circuits 12-1, 12-2, ..., 12-n, (n+1) pieces of arithmetic circuits 13-0, 13-1, 13-2, ..., 13-n, an adder 14 and a peak detection circuit 15. When the phase rotation θi of an phase rotation circuit 12-i coincides with phase rotation by a frequency offset, the synchronous timing waveform of the circuit 12-i has a sharp peak.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multicarrier receiving system and a receiving apparatus. In particular, the present invention provides an orthogonal frequency division multiplexing (OF) signal using a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol.
This is particularly useful for a DM) receiving system and receiving apparatus.

[0002]

2. Description of the Related Art For example, in an OFDM receiver described in Japanese Patent Application Laid-Open No. 7-321762, in order to obtain synchronization timing from a signal consisting of an effective symbol and a guard interval obtained by copying a part of the effective symbol, a signal subjected to quadrature detection is used. , And a correlation signal with the signal delayed by the effective symbol length. This is because the guard interval part of the delayed signal is
The fact that it matches the copy source of the signal that has not been delayed is used. That is, since the correlation signal is an integration of the product of the delayed signal and the undelayed signal, the fact that the correlation signal has a peak at the start of the guard interval of the undelayed signal is used. Note that the detection of the same peak is not limited to the correlation signal (integration of the product), and another signal obtained by calculating a delayed signal and an undelayed signal can be used.

[0003]

At the time of reception in the multi-carrier communication system, when the receiving station is a mobile station, an offset occurs in the frequency of each carrier. In this case, for example, in the orthogonal frequency division multiplexing (OFDM) using a signal having a guard interval, the following problem occurs.

FIGS. 10 and 11 are conceptual diagrams for explaining how a problem occurs. FIG. 10 shows the relationship between the in-phase component I _g and the quadrature component Q _g of the guard interval (GI) when there is no frequency offset Δf, and the in-phase component I ₀ and the quadrature component Q ₀ of the copy source portion of the effective symbol. I have. In FIG. 10, in order to show the concept of the phase, the guard interval (GI) and the effective symbol are shown as cylinders. It is assumed that time flows from left to right in FIG. 10, and that the upward direction is positive for the quadrature component Q and the diagonally near side is positive for the in-phase component I.

[0005] As shown in FIG.
If not, the in-phase component I of the guard interval (GI)_g
Or quadrature component Q_gAnd the in-phase of the source part of the effective symbol
Component I ₀Or quadrature component Q₀Matches. However, the frequency
If there is a offset Δf, the phase changes as shown in FIG.
You. Then, if there is a frequency offset Δf, the guard
In-phase component I of interval (GI)_gAnd the effective symbol
In-phase component I of copy source part₀Or guard interval
Orthogonal component Q of (GI)_gAnd the valid symbol
Quadrature component Q₀Do not match. In this case, the correlation signal
No sharp peak in the signal.

Further, even when the frequency offset Δf is small or absent, the correlation signal does not always generate a sharp peak. This situation is shown in FIGS. As shown in FIG. 12A, the output of the correlation signal does not exceed the threshold even when the timing is originally synchronous, as shown in FIG. Synchronization timing may not be obtained. This is because the magnitude of the correlation signal depends on the signal waveform itself because the correlation signal is the integral of the product of the detection signal and its delay signal.

The present invention has been made to solve these problems, and an object of the present invention is to provide a frequency offset Δf.
It is to obtain a synchronization signal even in the case where there is, and further to improve the detection accuracy of the peak.

[0008]

According to the first aspect of the present invention, there is provided a multicarrier receiving system using a signal comprising an effective symbol and a guard interval obtained by copying a part of the effective symbol. A quadrature detection means for obtaining an in-phase signal I and a quadrature signal Q by quadrature detection, a delay means for delaying the in-phase signal I by an effective symbol length T to obtain a delayed in-phase signal I '; Quadrature signal Q
Each phase _{θ i (1 ≦ i ≦ n} , n is an integer of 2 or more) by rotating the real part _{R (θ i) = Icosθ i} -Qsinθ i (1 ≦ i preparative as a complex signal I + jQ (j is an imaginary unit) ≦ n) and n pieces of phase rotation means for taking out the in-phase signal I and the delayed phase signal I ', delayed in-phase signal I' and R (θ _1), ..., the delay phase signal I '
N + 1 arithmetic means for obtaining n + 1 outputs by an operation of successively integrating the absolute value of the difference between the two signals R and R (θ _n ) using the guard interval length T _g as an integration interval; and n +
An adder for summing the (n + 1) outputs of one arithmetic unit and a detector for detecting a peak of the output of the adder, wherein a start timing of a guard interval is obtained by an output of the detector. .

[0010] The means described in claim 2 is the same as the claim 1.
Calculation means, the in-phase signal I and the delayed in-phase signal I ',
The delayed in-phase signals I ′ and R (θ ₁ ),.
(θ _n ) is calculated by successively integrating the product of each of the two signals with the guard interval length T _g as an integration interval to obtain n +
In this case, n + 1 arithmetic means for obtaining one output are used.

According to a third aspect of the present invention, in a multicarrier receiving system using a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol, the in-phase signal I and the quadrature signal are orthogonally detected. A quadrature detection means for obtaining a signal Q; a delay means for delaying the in-phase signal I or the quadrature signal Q by an effective symbol length T to obtain a delayed in-phase signal I 'or a delayed quadrature signal Q'; Computing means for outputting a waveform indicating the start timing of the guard interval by computation from the in-phase signal I ', the in-phase signal Q, and the delayed quadrature signal Q', and detecting means for detecting the peak of the output of the computing means, The detection means compares the output of the arithmetic means with the delayed output of the at least two stages by using at least two stages of connected delay means, thereby obtaining a peak of the output of the arithmetic means. The method is characterized in that a peak is detected.

The means according to claims 4 to 6 are the ones in which the main part of the receiving system according to claims 1 to 3 is a synchronous circuit.

[0012]

When the phase rotation occurs during the operation for detecting the guard interval start timing due to the influence of the frequency offset, etc., one of the in-phase signal and the delayed in-phase signal is phase-rotated. By doing so, the influence of the frequency offset can be eliminated. Even if the magnitude of this phase rotation is not specified, if a plurality of phase-rotated signals at appropriate intervals, for example, about π / 4 intervals, are generated, the integration of the product of the two signals or the difference between the two signals can be obtained. When obtaining by integration of absolute values, it can be considered that a calculation output other than the calculation with two phase-rotated signals near the phase rotation due to the influence of the frequency offset or the like does not affect the peak formation of the guard interval start timing. After all, if a plurality of phase-rotated and non-phase-rotated signals are prepared, the peak of the guard interval start timing can be detected regardless of the phase rotation by adding the arithmetic outputs.

In addition, if the scanning is performed at three or more points of the waveform with respect to the arithmetic means for outputting the waveform indicating the start timing of the guard interval, the peak can be easily detected.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a block diagram showing a configuration of a synchronization signal detection circuit 100 according to the first invention. Synchronization signal detection circuit 100, and outputs a synchronizing signal S _T from the in-phase signal I and quadrature signal Q, which is the output of the quadrature detector 200. Synchronous signal detection circuit 10
0 is a delay circuit 11, n phase rotation circuits 12-1,
, 12-n, and n + 1 arithmetic circuits 13-
.., 13-n and an adder 14
And a peak detection circuit 15.

The n phase rotation circuits 12-1, 12-2,
.., 12-n represent the phase θ from the in-phase signal I and the quadrature signal Q
_The signal R (θ _i ) shifted by _i is output. This means that R (θ _i ) = Re ｛(I), where Rx = Re (I + Qj), where j is an imaginary unit and Re means a real part.
+ Qj) exp (jθ _i )}. This allows
When the phase rotation due to the frequency offset is any of θ _i , the phase rotation circuits 12-1, 12-2,.
Copy source of guard interval of output n and delay circuit 11
Of the output and the guard interval are high. When the phase rotation due to the frequency offset is between the adjacent θ _i and θ _k , the guard interval copy source of the outputs of the two phase rotation circuits 12-i and 12-k and the output of the delay circuit 11 are output. Is the closest to the guard interval.

As described above, the in-phase signal I and the output R of the n phase rotation circuits 12-1, 12-2,.
Among the (θ ₁ ), R (θ ₂ ),..., R (θ _n ), the degree of coincidence between the copy source of one or two guard intervals and the guard interval of the output I ′ of the delay circuit 11 is high. Has a low degree of coincidence. Therefore, the output of the arithmetic circuit 13-0 based on the output I 'of the delay circuit 11 and the in-phase signal I, and the arithmetic circuit 13-based on the output I' of the delay circuit 11 and the output R (θ ₁ ) of the phase rotation circuit 12-1. 1; the output I ′ of the delay circuit 11; and the output R (θ ₂ ) of the phase rotation circuit 12-2.
,..., The output I ′ of the delay circuit 11 and the output R (θ _n ) of the phase rotation circuit 12-n are added by the adder 14 to obtain the in-phase signal I. A signal having a peak only at the start timing of the guard interval can be easily obtained.

The (n + 1) arithmetic circuits 13-0, 13-1,.
, 13-n, a correlation signal, a subtraction signal, or another arithmetic circuit can be used. FIG. 2 is a conceptual diagram showing a mechanism of a subtraction circuit for calculating the integral ∫ | I−I ′ | dt from the output I ′ of the delay circuit 11 and the in-phase signal I. By setting the integration interval to the guard interval length T _g , a signal that becomes 0 at the synchronization timing t _G can be obtained. This is because at the synchronization timing t _G , from time t _G −T _g to time t _G , I _g of the output I ′ of the delay circuit 11 and I _{0 of the in-} phase signal I are the same, and the difference is within the integration interval. At 0. When the other part is included in the integration interval, the absolute value of the difference may be considered to take a positive value stochastically. As a result, the integral ∫ | I−I ′ | dt becomes as shown in FIG. 0 at synchronization timing t _G , time t _G −T
It is probabilistically expected that monotonous decrease and monotone increase from _g to t _G + T _g and positive values at other times.

The n phase rotation circuits 12-1, 12-2,
, 12-n are, for example, n = 7 and θ _i = iπ / 4
If it is set at equal intervals from 0 to 2π, all phase rotations can be handled. This is shown in FIG. Note that the phases θ _i are not limited to equal intervals and may be arbitrarily designed. Also, n = 4
As an alternative, only the phase rotation in the vicinity of -π / 2, -π / 4, π / 4, π / 2 with no phase rotation in between may be used. Also in this case, the phases θ _i are not limited to equal intervals and may be arbitrarily designed.

Further, the phase rotation is divided into an in-phase component I and a quadrature component Q.
May be performed on the delayed in-phase component I ′ and the delayed quadrature component Q ′ to calculate the in-phase component I. This is shown in FIG. Also, instead of the delay in-phase component I ′ and the in-phase component I and the phase rotation R (θ _i ) of FIGS. 1 and 3, the delay quadrature component Q ′ and the quadrature component Q and the phase rotation R (θ
Performing the calculation with _i ) is naturally included in the present invention.

Second Embodiment FIG. 5 shows a peak detection circuit 150 according to the second invention. Peak detection circuit 150
Is to detect a peak from an output of an arbitrary synchronization signal operation circuit. The peak detection circuit 150 receives the output signal D ₀ of the synchronization signal operation circuit from the delay circuit 51 connected in two stages.
And 52 generate signals D ₁ and D ₂ delayed by a time interval τ. Signal D ₂ is delayed by 2τ compared to D ₀ . The comparison circuit 53 compares the signal D ₀ with the signal D ₂ , and D ₀ <
0 1, when D ₀ ≧ D ₂ when D ₂ is output to the AND gate 54. Arithmetic circuit 55 outputs the average value D _AV signal D ₀ and the signal D ₂ = a _{(D 0 + D 2) /} 2 to the comparator circuit 56. The comparison circuit 56 sets 1 for D ₁ <mD _AV and 0 for D ₁ ≧ mD _AV for a predetermined value m (m <1).
Output to the D gate 54. Such a peak detection circuit 1
When a signal D ₀ as shown in FIG.
The signals D ₁ and D ₂ and the outputs of the comparison circuits 53 and 56 are shown in FIG.
(B), (c), (d) and (e) of FIG.
At the timing when the signal D ₀ shown in FIG.
1 is output from the D gate 54. The present invention is particularly effective for the subtraction method shown in FIG. 2, but is also effective for the arithmetic circuit of the product integration method if the inequality sign of the comparison circuit is reversed.

As a modification of the second embodiment, FIG.
The clock detection circuit 160 can also be used. Peak detection
The circuit 160 outputs the output D of the synchronization signal operation circuit.₀Whereas 2
Time intervals τ by delay circuits 61 and 62 connected in stages
Delayed signal D₁And D_TwoIs generated. Signal D_TwoIs D₀
Is delayed by 2τ. Signal D₀And signal D_TwoThe ratio
The comparison circuit 63 compares₀> D_TwoWhen 1, D₀≤D_TwoNoto
Is output to the AND gate 64. The arithmetic circuit 65
Signal D₀And signal D_TwoAverage value of D_AV= (D₀+ D_TwoCompare) / 2
Output to the circuit 66. The comparison circuit 66 is determined in advance.
For the given value m (m <1), D₁<MD_AVWhen 1,
D₁≧ mD_AVIn this case, 0 is output to the AND gate 64.
FIG. 8A shows an example of such a peak detection circuit 160.
Una signal D ₀Is input, the signal D₁, D_Two, Comparison circuit 6
The outputs of 3 and 66 are (b), (c),
(D) and (e), and the signal D in FIG.₁
At the timing of the peak at the AND gate 64
Is output. In this case, 1 is output from the AND gate 64.
The output is the output D of the synchronization signal operation circuit.₀Time for
Since it is delayed by an interval τ, the received wave is demodulated accordingly.
Or effective symbol length T and guard interval length
T_gThe output of the AND gate 64 is T + T_g−τ delay
It is necessary to use the signal which was obtained. FIG. 7 peak detection circuit
160 is particularly effective for the subtraction method shown in FIG.
By reversing the inequality sign of the circuit, it becomes an arithmetic circuit of the product integration method
Is also effective.

[Modification] As a second invention, four stages of delay circuits are used to obtain five scanning points, and signals D ₀ , D ₁ , D ₂ , D ₃ , D ₄ shifted by time τ are used. To obtain signals D ₀ and D
_1, it is also possible to output the calculated peak point from D ₃ and D _4. This is shown as a conceptual diagram in FIG. Signal D ₂ is more effective when added even smaller set than the average value of D ₁ and D _3. The peak detection circuit having the operation of FIG. 9 is particularly effective for the subtraction method shown in FIG. 2, but is also effective for the arithmetic circuit of the product integration method.

Although the integration interval of the first embodiment is the guard timing _Tg , it is optional depending on the design. The time delay τ of the second embodiment may be, for example, T _g / 2, but is arbitrary. In the case of five-point scanning in the modification, for example, the time delay τ may be, for example, T _g / 4, but is arbitrary.

Further, the combination of the peak detection circuit of the first embodiment with the second embodiment and the combination of the modifications are even more effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization circuit according to a first invention.

FIG. 2 is a conceptual diagram showing an example of a synchronization signal operation.

FIG. 3 is a block diagram showing a configuration of another synchronous circuit according to the first invention.

FIG. 4 is a block diagram showing a configuration of a synchronization circuit according to a modification of the first invention.

FIG. 5 is a block diagram showing a configuration of a peak detection circuit according to a second invention.

FIG. 6 is a graph showing the operation of the peak detection circuit according to the second invention.

FIG. 7 is a block diagram showing a configuration of another peak detection circuit of the second invention.

FIG. 8 is a graph showing the configuration of another peak detection circuit according to the second invention.

FIG. 9 is a conceptual diagram showing the operation of a peak detection circuit according to a modification of the second invention.

FIG. 10 is a conceptual diagram showing a phase space of a guard interval (GI) obtained by copying an effective symbol and a part of the effective symbol.

FIG. 11 is a conceptual diagram showing a state where a phase is rotated by a frequency offset.

FIG. 12 is a graph showing a case where a peak of a synchronization signal exceeding a threshold is clear (a) and a case where the peak is not clear (b).

[Explanation of symbols]

 100: Synchronous circuit for multi-carrier receiving apparatus 150, 160 ... Peak detecting circuit 11, 51, 52, 61, 62 ... Delay circuit 12-i (1≤i≤n) Phase rotation circuit 13-0, 13-i (1 ≦ i ≦ n) arithmetic circuit 14 addition circuit 15 peak detection circuit 53, 56, 63, 66 comparison circuit 54, 64 AND gate 55, 65 arithmetic circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshitoshi Fujimoto 41-Cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside Toyota Central Research Laboratory Co., Ltd. (72) Inventor Tokuyoshi Suzuki Nagakute-cho, Aichi-gun, Aichi Prefecture No. 41, Yokomichi, Yojimichi, F-term, Toyota Central Research Laboratory Co., Ltd. F-term (reference) 5K022 DD01 DD13 DD17 DD19 DD31 DD32 DD42 5K047 AA03 BB01 CC01 HH01 HH15 HH31 MM12 MM35 MM36 MM59

Claims (6)

[Claims] An effective symbol and a part of the effective symbol are duplicated.
Using a signal consisting of the copied guard interval
Quadrature detection to obtain in-phase signal I and quadrature signal Q by quadrature detection in a multicarrier receiving system
Means for delaying the in-phase signal I by an effective symbol length T
And a delay means for obtaining the signal I ′, and a complex signal I + jQ (j is
Phase unit)_i(1 ≦ i ≦ n, n is 2 or less
(The integer above) and rotate the real part R (θ_i) = Icosθ_i−Qsinθ
_iN phase rotation means for extracting (1 ≦ i ≦ n), in-phase signal I and delayed in-phase signal I ′, delayed in-phase signal I ′ and R
(θ₁),..., The delayed in-phase signals I ′ and R (θ_n) And two each
The absolute value of the difference between the signals _gMultiply
N + 1 outputs by the operation of successively integrating as a segment
And an adder that sums n + 1 outputs of the (n + 1) arithmetic means.
And a detecting means for detecting the peak of the output of the adding means.
The start time of the guard interval is determined by the output of the detection means.
A multi-carrier reception method characterized by obtaining the ringing. 2. A multicarrier receiving system using a signal comprising an effective symbol and a guard interval obtained by copying a part of the effective symbol, comprising: a quadrature detection means for obtaining an in-phase signal I and a quadrature signal Q by quadrature detection; A delay means for delaying the signal I by the effective symbol length T to obtain a delayed in-phase signal I '; and a phase θ _i (1) in which the in-phase signal I and the quadrature signal Q are complex signals I + jQ (j is an imaginary unit). ≦ i ≦ n, n is an integer of 2 or more) by rotating the real part _{R (θ i) = Icosθ i} -Qsinθ
_i (1 ≦ i ≦ n), n phase rotation means for extracting the in-phase signal I and the delayed in-phase signal I ′, and the delayed in-phase signal I ′ and R
(θ ₁ ),..., n + 1 outputs are calculated by successively integrating the product of the two signals of the delayed in-phase signal I ′ and R (θ _n ) with the guard interval length T _g as an integration interval. Get n
+1 arithmetic means, adding means for summing n + 1 outputs of the n + 1 arithmetic means, and detecting means for detecting a peak of the output of the adding means, and a guard interval start timing based on an output of the detecting means. A multi-carrier receiving method characterized by obtaining: 3. A quadrature detection means for obtaining an in-phase signal I and a quadrature signal Q by quadrature detection in a multi-carrier reception system using a signal comprising an effective symbol and a guard interval obtained by copying a part of the effective symbol. Delay means for delaying the signal I or the quadrature signal Q by an effective symbol length T to obtain a delayed in-phase signal I 'or Q'; an in-phase signal I, a delayed in-phase signal I ', an in-phase signal Q, and a delay quadrature An arithmetic means for outputting a waveform indicating a start timing of the guard interval by an arithmetic operation from the signal Q '; and a detecting means for detecting a peak of the output of the arithmetic means, wherein the detecting means has at least two connected delays. Means, the output of the arithmetic means and at least two delayed
A multi-carrier receiving method characterized by detecting the peak of the output of the arithmetic means by comparing the magnitude of the output of the stage. 4. An effective symbol and a part of the effective symbol are duplicated.
Using a signal consisting of the copied guard interval
In-phase signal obtained by quadrature detection of multicarrier receiver
From the signal I and the quadrature signal Q, the start time of the guard interval
In the synchronous circuit that outputs the timing, the in-phase signal I is delayed by the effective symbol length T,
And a delay circuit for obtaining the signal I ′, and the complex signal I + jQ (j is an imaginary
Phase unit)_i(1 ≦ i ≦ n, n is 2 or less
(The integer above) and rotate the real part R (θ_i) = Icosθ_i−Qsinθ
_iN phase rotation circuits for extracting (1 ≦ i ≦ n), in-phase signal I and delayed in-phase signal I ′, delayed in-phase signal I ′ and R
(θ₁),..., The delayed in-phase signals I ′ and R (θ_n) And two each
The absolute value of the difference between the signals _gMultiply
N + 1 outputs by the operation of successively integrating as a segment
And an addition circuit that takes the sum of n + 1 outputs of the (n + 1) arithmetic circuits
And a detection circuit for detecting the peak of the output of the adder circuit.
The start of the guard interval is determined by the output of the detection circuit.
For multicarrier receivers characterized by obtaining
Synchronous circuit. 5. A start of a guard interval from an in-phase signal I and a quadrature signal Q obtained by quadrature detection in a multicarrier receiving apparatus using a signal composed of a valid symbol and a guard interval obtained by copying a part of the valid symbol. In a synchronous circuit for outputting timing, a delay circuit for delaying an in-phase signal I by an effective symbol length T to obtain a delayed in-phase signal I ′, a complex signal I + jQ (j is an imaginary number) units), each phase _{θ i (1 ≦ i ≦ n} , n is an integer of 2 or more) by rotating the real part _{R (θ i) = Icosθ i} -Qsinθ
_i (1 ≦ i ≦ n), n phase rotation circuits for extracting the in-phase signal I and the delayed in-phase signal I ′, and the delayed in-phase signal I ′ and R
(θ ₁ ),..., n + 1 outputs are calculated by successively integrating the product of the two signals of the delayed in-phase signal I ′ and R (θ _n ) with the guard interval length T _g as an integration interval. Get n
+1 arithmetic circuits, an adder circuit for summing the (n + 1) outputs of the (n + 1) arithmetic circuits, and a detection circuit for detecting the peak of the output of the adder circuit. The start timing of the guard interval based on the output of the detection circuit. A synchronous circuit for a multicarrier receiving apparatus. 6. A synchronizing circuit for outputting a start timing of a guard interval of a multicarrier receiving apparatus using a signal composed of a valid symbol and a guard interval obtained by copying a part of the valid symbol. A quadrature detection circuit for obtaining a quadrature signal Q; a delay circuit for delaying the in-phase signal I or Q by an effective symbol length T to obtain a delayed in-phase signal I ′ or Q ′; An arithmetic circuit that outputs a waveform indicating the start timing of the guard interval by an arithmetic operation from the signal I ′, the in-phase signal Q, and the delayed quadrature signal Q ′, and a detection circuit that detects the peak of the output of the arithmetic circuit. The detection circuit has at least two stages of connected delay circuits, and operates by comparing the output of the arithmetic circuit with the magnitude of the delayed at least two stages of output. Multicarrier receiver apparatus for synchronizing circuit and detecting a peak of an output of the circuit.