JP3446684B2 - Multicarrier receiving system, receiving apparatus and frequency offset detecting circuit for receiving apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a multicarrier receiving system and a receiving apparatus. The present invention is particularly applicable to an orthogonal frequency division multiplexing (OF) method using a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol.
It is particularly useful for a DM) receiving system and a receiving device.

[0002]

2. Description of the Related Art When a multi-carrier communication system is received, it is necessary to accurately reproduce the frequency of each carrier. However, when the receiving station is a mobile station, an offset occurs in the frequency of each carrier. Therefore, particularly in the case of a receiving station which is a mobile station, it is necessary to detect the frequency offset of each carrier at the time of demodulation and remove the influence thereof.

For example, in the OFDM synchronous demodulation circuit described in Japanese Patent Laid-Open No. 7-143097, the frequency offset of the carrier is detected by a circuit as shown in FIG. That is, for multi-carrier signals that are complex data,
Complex multiplication is performed with a signal (output of the delay circuit 91) delayed by the effective symbol length (time). The obtained results (the output of the complex multiplication circuit 92) are added and averaged (addition and averaging circuit 9
3) Then, the arc tangent (tan ^-1 ) of the ratio of the real part and the imaginary part is obtained to obtain the phase difference (phase difference circuit 94), and the frequency offset is obtained from this.

[0004]

The frequency offset detection circuit as described above uses a large number of complex operations for the operations, which results in a large circuit scale. In other words, the larger the number of carriers, the higher the speed of the multi-carrier transmission method, the more logical elements that can be operated at high speed are required, and the circuit design becomes extremely complicated.

The present invention has been made to solve such a problem, and an object thereof is to accurately detect a carrier frequency offset in an arithmetic circuit having a small circuit scale. A demodulation device and a demodulation method using such a circuit are also provided.

[0006]

In order to solve the above-mentioned problems, according to the means described in claim 1, a multi-carrier for receiving a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol. In the receiving method,
An in-phase component delay means and a quadrature component delay means for delaying the in-phase component I and the quadrature component Q, which are quadrature-demodulated from the received signal, by the effective symbol amount T to form a delayed in-phase component I ′ and a delayed quadrature component Q ′, and In-phase component I and delayed in-phase component I '
And a timing information calculation means for detecting the synchronization timing t _G , and an integral ∫ (| Q−I ′ | − | from the in-phase component I, the quadrature component Q, the delayed in-phase component I ′ and the delayed quadrature component Q ′.
There is a cross component amount calculating means for calculating IQ ′ |) dt with a guard interval length T _g , and a gate means for outputting the output of the cross component amount calculating means at the synchronization timing t _G from the information of the timing information calculating means. Then, the frequency for quadrature demodulating the received signal is corrected from the output of the gate means.

Further, according to the means described in claim 2, the output of the timing information calculating means outputs the guard interval length T.
The integral of _g is ∫ | II ′ | dt.

The means described in claim 3 and claim 4 is a multicarrier receiving apparatus using the multicarrier receiving system according to claim 1 and claim 2, respectively. The means described in claim 5 and claim 6 are the frequency offset detection circuits for a multicarrier receiver, which are the main parts of the multicarrier receiver described in claim 3 and claim 4, respectively.

[0009]

[Operation and Effect of the Invention] At the synchronization timing t _G ,
Integral ∫ (| Q-I 'calculated with the guard interval length T _g
|-| I-Q '|) dt is proportional to the phase difference due to the frequency offset. However, it is assumed that the frequency offset is between -1 / 4T and 1 / 4T. This means that when the frequency offset is -1 / 4T, ∫ | IQ '| dt is 0.
This is because it is considered that the frequency offset increases as the frequency offset becomes 0, and when the frequency offset is positive, it takes a certain positive constant value stochastically. When the frequency offset is 1 / 4T, ∫ | Q-I '| dt is 0,
This is because it is considered that the frequency offset increases as it becomes 0, and when the frequency offset is negative, it has a certain positive constant value stochastically. So if you take these differences,
The integral ∫ (| Q−I ′ | − | I−Q ′ |) dt calculated by the guard interval length T _g at the synchronization timing t _G between the frequency offset of −1 / 4T and 1 / 4T.
Is proportional to the phase difference due to the frequency offset.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the examples below.

1 and 2 are block diagrams showing the configuration of a frequency offset detection circuit 100 for showing the overall concept of the present invention and a block diagram showing the configuration of a multicarrier receiver 1000 incorporating the same. Is. Figure 1
The frequency offset detection circuit 100 is composed of two delay circuits 11 and 12, a timing information calculation circuit 20, a crossing component calculation circuit 30, and a gate circuit 40.

As shown in FIG. 2, the multi-carrier signal is demodulated by the carrier of the voltage controlled oscillator (VCO) 1 and the multiplier 2 to generate the in-phase component I. Note that the multiplier 2 also performs low frequency leaky waves. The carrier wave of the voltage controlled oscillator (VCO) 1 is output to the multiplier 4 as a carrier wave whose phase is shifted by the 90-degree phase shifter 3, and the quadrature component Q is generated from the multicarrier signal. Note that the multiplier 4 also performs low frequency leaky waves. In this way, the multicarrier signal is quadrature demodulated into the in-phase component I and the quadrature component Q.

The in-phase component I and the quadrature component Q are demodulated by the multicarrier demodulator 5. The in-phase component I and the quadrature component Q are the frequency offset detection circuit 1 according to the present invention.
It is also output to 00. Frequency offset detection circuit 100
Will be described with reference to FIG. The in-phase component I and the quadrature component Q are input to the delay circuits 11 and 12, and the delayed in-phase component I ′ and the delayed quadrature component Q ′ are generated. The timing information calculation circuit 20 outputs an output indicating the synchronization timing t _G from the in-phase component I and the delayed in-phase component I ′. The cross component amount calculation circuit 30 calculates the integral ∫ (| Q−I ′ | − from the in-phase component I, the quadrature component Q, the delayed in-phase component I ′, and the delayed quadrature component Q ′.
The integral interval for calculating | I−Q ′ |) dt is the guard interval length T _g . This output is output to the gate circuit 40. The gate circuit 40 determines the synchronization timing t _G from the output of the timing information calculation circuit 20, and the integral ∫ (| Q−I ′ | − which is the output of the cross component amount calculation circuit 30 at that time.
| I-Q '|) dt is output. The integral ∫ (| Q−I ′ | which is the output of the cross component amount calculation circuit 30 at the synchronization timing t _G.
Since − | I−Q ′ |) dt is proportional to the frequency offset Δf, it is passed through the loop filter 6 as shown in FIG. 2 to correct the frequency of the carrier wave output from the voltage controlled oscillator (VCO) 1. Below, the integral ∫ (| Q-I '|-| I-Q' |) dt
The reason why is proportional to the frequency offset Δf will be described.

FIG. 3 shows the relationship between the in-phase component I _g and the quadrature component Q _g of the guard interval (GI) when there is no frequency offset Δf, and the in-phase component I ₀ and the quadrature component Q ₀ of the copy source part of the effective symbol. Indicates. In FIG. 3, in order to show the concept of phase, the guard interval (GI) and the effective symbol are shown by a cylinder. It is assumed that time flows from left to right in FIG. 3, the quadrature component Q is positive in the upward direction, and the in-phase component I is positive in the oblique front side.

As shown in FIG. 4, when there is no frequency offset Δf, there is no phase difference between the in-phase component I and the delayed in-phase component I ', and the copy source part I ₀ of the effective symbol of the in-phase component I and the delayed in-phase component I are shown. It is exactly the same as the guard interval (GI) part I _{g of} '. Therefore, the difference is 0 in this section (guard interval length T _g ). However, in other sections, it can be considered that a certain value in terms of probability is taken as the average and takes a positive value. Therefore, the integration interval length is set to the guard interval length T
_{If the} successive integration ∫ | II ′ | dt is taken as _g , the in-phase component I
It can be seen that at the end of the effective symbol (the end of the guard interval portion of the delayed in-phase component I ′) t _G , the value becomes 0.

It is now assumed that the frequency offset Δf is 1/4 of the reciprocal 1 / T of the effective symbol length T. At this time,
The copy source part I ₀ of the quadrature demodulated effective symbol is demodulated into the quadrature component Q with a phase shift of π / 2 (FIG. 5). This is because the time from the guard interval (GI) to the copy source is shifted by T. Then, if the integral ∫ | Q−I ′ | dt is taken, the guard interval (GI) part I _{g of} the delayed in-phase component I ′ and the copy source part I _{0 of the} effective symbol demodulated as the quadrature component Q are completely obtained. Will be the same. Therefore, if the integral interval length is set to the guard interval length T _g and the successive integration ∫ | Q−I ′ | dt is taken, it will be understood that it becomes 0 at the synchronization timing t _G. Considering this when the frequency offset Δf is −1 / 2T to 1 / 2T, the integral ∫ | Q−I ′ | dt of the integration section length T _g at the synchronization timing t _G.
Is a constant value when Δf is negative and Δf when it is positive, as shown in FIG.
It can be seen that f = 1 / 4T is symmetrical with 0 in between.

In exactly the same way, the frequency offset Δf is −
If it is 1 / 4T, the copy source portion Q ₀ of the effective symbol that has been orthogonally demodulated as shown in FIG. 7 will be demodulated into the in-phase component I with a phase shift of −π / 2. Therefore, as shown in FIG. 8, the integral ∫ | I of the integration interval length T _g at the synchronization timing t _G
−Q ′ | dt is a constant value when Δf is positive, and Δf = when it is negative.
It can be seen that -1 / 4T is symmetrical with 0 sandwiched. Therefore, the integral ∫ (| Q−I ′ | − | I−Q ′ |) dt is proportional to the frequency offset Δf. The simulation is shown in FIG. It can be seen that the integral ∫ (| Q−I ′ | − | I−Q ′ |) dt monotonically decreases when the frequency offset Δf is −1 / 4T or more and ¼T or less. Therefore, this can be used as a frequency offset detecting means.

A concrete implementation of the present invention is shown in FIGS.
Of the frequency offset detection circuits 101 and 102 according to the example
The circuit is shown in a block diagram. Frequency offset detection of FIG.
The output circuit 101 is the frequency offset detection circuit 10 of FIG.
The timing information calculation circuit 20 of 0
Do interval length T_gThe successive integration ∫ | II ′ | dt
Synchronization timing t_GGet information on Taimi
And a crossing component amount calculation circuit.
The path 30 is the integration interval length and the guard interval length T _gAs
Sequential integrals ∫ | Q-I '| dt and ∫ | I-Q' | dt were calculated
Then find the difference ∫ (| Q-I '|-| I-Q' |) dt
This is a crossing component calculation circuit 301. Also, FIG.
The frequency offset detection circuit 102 of FIG.
Timing information calculation circuit 2 of offset detection circuit 100
0, the integration interval length is the guard interval length T_gAs
Synchronous timing by taking the next integral ∫ | I-I '| dt
G t _GAnd a timing information calculation circuit 200 for obtaining information of
In addition, the crossing component amount calculation circuit 30 is set to | Q-I '|-|
After calculating IQ '|, the integration interval length is set to the guard interval.
Le length T_gAs successive integration ∫ (| Q-I '|-| I-Q' |) d
This is a cross component calculation circuit 302 for obtaining t.

In the timing information calculation circuit 200, the subtraction circuit 21, the absolute value circuit 22, and the integration circuit 23 are sequentially I-I ', | I-I' |, from the in-phase component I and the delayed in-phase component I '.
∫ | II ′ | dt (integration interval length T _g ) is sequentially obtained. The cross component calculation circuit 301 calculates a subtraction circuit 31I and an absolute value circuit 32 from the quadrature component Q and the delayed in-phase component I ′.
I, in the integrating circuit 33I, Q-I ', | Q-I' |, ∫ |
Q-I '| dt (integration interval length _Tg ) is sequentially obtained, and the in-phase component I
From the delay quadrature component Q ', the subtraction circuit 31Q, the absolute value circuit 32Q, and the integration circuit 33Q sequentially take IQ', | I-Q '.
|, ∫ | I−Q ′ | dt (integration interval length T _g ) is sequentially obtained, and the subtraction circuit 341 obtains the integral ∫ (| Q−I ′ | − | I−Q ′ |) dt. Further, the crossing component calculation circuit 302 calculates the subtraction circuit 31I from the quadrature component Q and the delayed in-phase component I ′,
The absolute value circuit 32I sequentially determines Q-I 'and | Q-I' |, and the subtraction circuit 3 calculates the in-phase component I and the delayed quadrature component Q '.
1Q, absolute value circuit 32Q sequentially obtains IQ ', | I-Q' |, and subtraction circuit 342 obtains | Q-I '|-| I-Q' |
And the integration circuit 332 integrates ∫ (| Q−I ′ | − | I−
Q '|) dt is obtained.

Naturally, the frequency offset can be detected even if the integral sign of the present invention is changed. Further, the calculation of the timing information includes the quadrature component Q and the delay quadrature component Q ′
Of course, it is also possible to ask from. These variations are naturally included in the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a frequency offset detection circuit according to the present invention.

FIG. 2 is a block diagram showing the outline of the configuration of a multicarrier receiver incorporating a frequency offset detection circuit according to the present invention.

FIG. 3 is an explanatory diagram showing the concept of the present invention.

FIG. 4 is a conceptual diagram showing the contents of integration calculation in the present invention.

FIG. 5 is an explanatory diagram showing the concept of the present invention in which the phase is shifted by π / 2.

FIG. 6 is a graph showing integration when the phase is shifted by π / 2.

FIG. 7 is an explanatory diagram showing the concept of the present invention in which the phase is shifted by −π / 2.

FIG. 8 is a graph showing integration when the phase is shifted by −π / 2.

FIG. 9 is a simulation diagram showing the relationship between integration and frequency offset Δf according to the present invention.

FIG. 10 is a block diagram showing a configuration of a frequency offset detection circuit of the present invention.

FIG. 11 is a block diagram showing the configuration of another frequency offset detection circuit of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional frequency offset detection circuit.

[Explanation of symbols]

I in-phase component Q quadrature component I'delayed in-phase component Q'delayed quadrature component I _g in-phase component of guard interval portion I ₀ valid in-phase component of copy source portion of guard interval portion of symbol Q _g orthogonal component Q ₀ of guard interval portion Orthogonal component of copy source part of guard interval part of symbol T effective symbol length T _g guard interval length t _G synchronization timing

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-9-321733 (JP, A) JP-A-7-99486 (JP, A) JP-A-9-200176 (JP, A) JP-A-6- 244818 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04J 11/00

Claims (6)

(57) [Claims] 1. In a multi-carrier reception system for receiving a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol, an in-phase component I and an orthogonal component Q, which are quadrature-demodulated from a received signal, are respectively effective. The synchronization timing t _G is calculated from the in-phase component delay means and the quadrature-component delay means for delaying only the symbol T to form the delayed in-phase component I ′ and the delayed quadrature component Q ′, and the in-phase component I and the delayed in-phase component I ′. From the timing information calculating means for detecting, the in-phase component I, the quadrature component Q, the delayed in-phase component I ′ and the delayed quadrature component Q ′, the integral ∫ (| Q−I ′ | − | I−Q ′ |) dt
The has a cross-component amount calculating means for calculating with the guard interval length T _g, and a gate means for outputting an output of the cross-component amount calculating means in the synchronization timing t _G from the information of the timing information calculating means, said gate means A frequency for correcting the received signal for quadrature demodulation is corrected from the output of the multi-carrier reception system. 2. The output of the timing information calculation means is
Interval length T _gThe integral of ∫ | II ′ | dt
The multi-carrier receiving method according to claim 1, wherein
formula. 3. A multicarrier receiving apparatus for receiving a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol, and an in-phase component I and an orthogonal component Q, which are quadrature-demodulated from a received signal, are respectively effective. The synchronization timing t _G is calculated from the in-phase component delay circuit and the quadrature-component delay circuit that delay the symbol component T to form the delayed in-phase component I ′ and the delayed quadrature component Q ′, and the in-phase component I and the delayed in-phase component I ′. From the timing information calculation circuit for detection, the in-phase component I, the quadrature component Q, the delayed in-phase component I'and the delayed quadrature component Q ', the integral ∫ (| Q-I' |-| I-Q '|) dt
The has a cross-component amount calculating circuit for calculating guard interval length T _g, and a gate circuit which outputs the output of the cross-component amount calculating circuit in the synchronization timing t _G from the information of the timing information calculating circuit, said gate circuit The multi-carrier receiving apparatus is characterized in that the frequency for quadrature demodulating the received signal is corrected from the output of. 4. The output of the timing information calculation circuit is
Interval length T _gThe integral of ∫ | II ′ | dt
4. The multi-carrier receiver according to claim 3, wherein
Place 5. In a frequency offset detection circuit of a multicarrier receiver for receiving a signal composed of an effective symbol and a guard interval obtained by copying a part of the effective symbol, an in-phase component I and an orthogonal component which are quadrature demodulated from a received signal. From the in-phase component delay circuit and the quadrature-component delay circuit that delay Q and each by the effective symbol T to form the delayed in-phase component I ′ and the delayed quadrature component Q ′, and the in-phase component I and the delayed in-phase component I ′, From the timing information calculation circuit for detecting the synchronization timing t _G , the in-phase component I, the quadrature component Q, the delayed in-phase component I ′ and the delayed quadrature component Q ′, the integral ∫ (| Q−I ′ | − | I− Q '|) dt
The has a cross-component amount calculating circuit for calculating guard interval length T _g, and a gate circuit which outputs the output of the cross-component amount calculating circuit in the synchronization timing t _G from the information of the timing information calculating circuit, said gate circuit Is used as a signal for correcting a frequency for quadrature demodulating the received signal, a frequency offset detection circuit for a multicarrier receiver. 6. The output of the timing information calculation circuit is
Interval length T _gThe integral of ∫ | II ′ | dt
The multi-carrier receiving device according to claim 5, characterized in that
Frequency offset detection circuit for storage.