JP2001144633A - Viterbi detector, signal processing circuit, recording and reproducing device and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption. SOLUTION: In the case that likelihood calculation is executed on the basis of the Viterbi algorithm, a decoded value series is estimated and they are stored in path memories (630-633), a convergence discriminator (660) discriminates whether an alive path is converged on the basis of the values stored in each stage of the path memories (630-633). When the discriminator (660) discriminates that the alive path has converged, the discriminator (660) stops the operation of the path memories (630-633) that store information prior to the point of time of convergence except one path memory (630) that is selected optionally (but fixedly). Then the discriminator (660) outputs the output of the path memory (630) whose operation has not been stopped as a decoding result. Since the operation of the path memories whose alive path has converged is stopped, the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi detector, a signal processing circuit, a recording / reproducing apparatus, and an information processing system. More specifically, the present invention relates to a Viterbi detector capable of reducing power consumption, a signal processing circuit, and a recording / reproducing apparatus. The present invention relates to an apparatus and an information processing system.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing device (for example, a magnetic disk device, a magnetic tape device) or an optical or magneto-optical recording / reproducing device (for example, an optical disk device, a magneto-optical disk device), a PR (Partial Response) is used. A PRML method has been put to practical use in which waveform equalization is performed by a method and data is detected by an ML (Maximum Likelihood) decoding method. The PRML method is a decoding method in which the most probable data sequence is used as decoded data by positively utilizing intersymbol interference (interference of a reproduced signal corresponding to adjacent recording bits). According to such a PRML system, by limiting the band of the signal channel, the detection accuracy can be improved even with respect to a reproduced waveform having a low S / N ratio, thereby improving the recording density. .

There are several types of PR systems depending on what kind of intersymbol interference is applied. For example, in a magnetic disk drive, a PR system having band-pass characteristics is often used. Recently, an EPR (Extended PR) method for further lowering the band frequency and an EEPR (Extended E)
(PR) system is attracting attention.

[0004] The transfer function of the EPR system is G (D) = (1-
D ² ) (1 + D). Here, D represents a delay operator. The length (constraint length) L of the code interference is “3”. The transfer function of the EEPR method is G (D) =
It is expressed as (1−D ² ) (1 + D) ² . The length (constraint length) L of the code interference is “4”.

In a magnetic recording / reproducing system in which recording data is binary,
There are 2 ^L different intersymbol interference modes or states. Therefore, the Viterbi detector of the system using the EPR method handles eight states. Further, the Viterbi detector of the system using the EEPR method handles 16 states. When the EPR method or the EEPR method is used, the configuration of the Viterbi detector becomes complicated as compared with the most basic PR method, but the data detection accuracy can be improved.

A signal waveform-equalized by the PR method has a correlation with signals before and after. For such a signal sequence, the Viterbi detector performs decoding by estimating the most likely value by utilizing the characteristics of the signal based on the correlation between the amplitudes.

FIG. 12 shows a signal system model of a magnetic disk drive provided with a conventional Viterbi detector. The magnetic disk device 120 includes a precoder 101, an R / W amplifier 110, a magnetic disk 411, a (1-D) computing unit 102 representing reproduction characteristics of a head, an analog filter 1
03, an A / D converter 104, a waveform equalizer 105,
And a Viterbi detector 106. (1-D)
Noise is superimposed on the output of the arithmetic unit 102.

The input data is pre-coded by the precoder 101 by “1 / (1-D ² ) modulo 2” operation, and is passed through the R / W amplifier 110 to the magnetic disk 41.
1 is recorded. The reproduced signal passes through an analog filter 103 that removes high-frequency noise superimposed on the signal and an A / D converter 104 that performs analog / digital conversion at predetermined time intervals, and is equalized by a waveform equalizer 105. The equalized data is decoded by the Viterbi detector 106 into an input signal sequence.

FIG. 13 shows a trellis diagram of the EPR transmission line. When performing EPRML, combinations of inter-symbol interference (state) is 8 state of S ₀ to S _7. The branch (branch) emerging from the point of each state S _i (t-1) at time (t-1) is
The upper branch indicates the direction of transition when the input value is “0”,
It indicates the direction of transition when the lower branch has the input value “1”.
X1 / z1, x on the right side of each state S _i at time t
The value of x1 written in the form of 2 / z2 is the output value (input value to the channel) of the Viterbi detector 106, which is given to the upper branch toward each state. The value of z1 is a target value to be compared at the time of executing the likelihood calculation, which is given to the upper branch toward each state. The value of x2 is the output value of the Viterbi detector 106, which is given to the lower branch toward each state. The value of z2 is a target value to be compared when the likelihood calculation is performed, which is given to the lower branch toward each state. For example, the state at time (t-1) is the case was S _0, branches toward the S ₀ or S _1. When the input value of the reproduction system at time t is “0”, the upper branch is transited,
The state at time t becomes S ₀ , and the output value (decoding result) of the Viterbi detector 106 becomes “0”.

If there is no noise in the reproduced signal, the Euclidean distance (y (t)) is obtained from the waveform-equalized reproduced signal y (t).
According to −z (t)) ² = 0, the target value z (t) (the input value originally represented by the reproduced signal) can be uniquely determined. However, since the reproduced signal y (t) actually includes noise n (t), y (t) = z (t) + n (t). For the noise-added signal y (t), the Viterbi detector 106 sets the target value z that minimizes the sum of the Euclidean distance (y (t) −z (t)) ^2.
Maximum likelihood decoding for estimating that the sequence of (t) is represented by the sequence of the reproduced signal y (t) is performed.

Next, the Viterbi detector 106 will be described. Here, EPRML will be described as an example. FIG.
FIG. 4 shows a schematic configuration diagram of the Viterbi detector 106. The Viterbi detector 106 includes an ACS unit 320 including a branch metric calculation circuit 301 and ACS (Add-Compare-Select) circuits 310 to 313, and a path memory unit 321 including path memories 330 to 333. You. The ACS circuits 310 to 313 are provided corresponding to each state S. The path memories 330 to 333 are provided corresponding to each state S. Each path memory 330 to 333
Is constituted by a shift register.

When the reproduction signal y (t) is input to the Viterbi detector 106 at time t, the branch metric calculation circuit 301 calculates a target value z (t) corresponding to each branch of the trellis diagram of FIG. The Euclidean distance from the reproduction signal value y (t) is calculated and sent to the corresponding ACS circuits 310 to 313. For example, branches toward the state S ₀ in FIG. 13, there are two from state S ₄ from state S _0, each of the target values z1, z2 is "0", - "1". In this case, the Euclidean distance between the reproduction signal y (t) and the target value z1 and the reproduction signal y (t)
The Euclidean distance between the target and the target value z2 is obtained, and the result is sent to the ACS ₀ circuit 310 corresponding to the state S ₀ .
The Euclidean distance between the target value z (t) corresponding to the branch going from the state S _j (t-1) to S _i (t) and the reproduction signal y (t) as described above is represented by the branch at time t of the branch. Called Metric, _Bji
(t).

The i-th ACS _i circuit 312 calculates and manages the “probability” of the most probable path among the paths leading to the state S _i , assuming that the current state is S _i . This “probability” is called a path metric, and M
_i (t).

That is, the branch metric calculation circuit 3
AC that receives branch metric B _ji (t) from 01
S _i circuit 312, the state of the time t assuming that a S _i, one of the two branches leading to S _i at time t, is better to pass through either branch to estimate the probable. For example, for S _i , there is a branch from S _j and a branch from S _k . At this time, the branch metric B is supplied from the branch metric calculation circuit 301 to the ACS _i circuit 312.
_ji (t) and B _ki (t) are sent. Branch metric B _ji
The ACS _i circuit 312 that has received (t) and B _ki (t) receives the path metric M _j (t−1) calculated at time (t−1) by the ACS _j circuit as a branch from S _j to S _i. And the branch metric B _ji (t) of the branch from S _j to S _i are added to calculate the path metric M1. Similarly, the S _k path ACS _k circuit as branches towards the S _i is calculated at time (t-1) from the metric M _k (t-1), the branch metric of the branch going from S _k to S _i B _ki ( t) is added to calculate the path metric M2. The smallest one of the path metrics M1 and M2 thus obtained is selected as the path metric M _i (t). Thereby, the path metric M _i (t) of the most probable path among the paths reaching the state S _i at the time t.
Ask for. At this time, the output value corresponding to the “surviving path” (branch) selected in each state is stored in the path memory 330.
To 333, respectively. At this time, the state of the time (t-1) in the surviving path is also notified to the path memories 330 to 333.

The i-th path memory 332 stores a sequence of output values corresponding to the most probable path among the paths leading to the state S _i , assuming that the current state is S _i . That is, when the notification of the state at the time (t-1) is sent from the ACS _i circuit 312, first, the contents of the shift register are stored in the shift register at the time (t-1) corresponding to the state at the notified time (t-1). Rewrite with the contents of -1). Then, the contents of the shift register are shifted by one bit to output the first bit of the first stage, and the output value sent from the ACS _i circuit 312 is stored in the last stage of the vacant shift register. The content of the shift register obtained as a result is the content of the shift register at time t. By executing this operation at each time, an output value sequence corresponding to the surviving path estimated by the ACS _i circuit 312 is stored in the shift register in chronological order.

Here, if the number of bits of the shift register constituting each of the path memories 330 to 333 is sufficiently large (usually 4 to 5 times the constraint length), the output value output from each path memory Have the same value. This is because the surviving path information in each state estimated by the ACS circuits 310 to 313 converges to the same contents as far as the past, by the surviving path estimation operation of each of the ACS circuits 310 to 313. It depends on what you can expect. In this case, the Viterbi detector 106 outputs the same value no matter which path memory is selected.

A method of extracting the output of the Viterbi detector from the front end of a specific path memory set in advance is disclosed in US Pat. No. 5,588,011 to CMRiggle. However, in this case, since the surviving paths held by all the states need to be uniquely converged, it is necessary to have a path memory having a sufficient length, which increases the hardware and power consumption. Increase.

Therefore, in order to avoid an increase in hardware and power consumption, a method of selecting and outputting the contents of the path memory corresponding to the state where the path metric is minimized at each time is disclosed in Japanese Patent Application Laid-Open No. H11-103258. No. 6,086,045.

[0019]

In the conventional Viterbi detector, the path memory operates at all times, and there is a problem that power is always consumed. Therefore, an object of the present invention is to provide a Viterbi detector, a signal processing circuit, a recording / reproducing device, and an information processing system that can reduce power consumed by a path memory.

[0020]

According to a first aspect of the present invention, a code value at a time t (where t is a natural number of 2 or more) and a state at a time (t-1) are represented in a discrete time system. (N is a natural number equal to or greater than 2), and each state is a system represented by one bit or a plurality of bits, and the time (t-1) Viterbi detection for a code having a characteristic that a decoded value at time t is determined by a state transition from a state at time t to a state at time t, and determining a decoded value sequence from an input value sequence in which an error is superimposed on the code value sequence A plurality of surviving path calculating means provided for each of the N states, and a plurality of path memories, wherein each surviving path calculating means has an n-th state. With the assumption that Of the most probable state transition path among a plurality of state transition paths leading to the state transition path is estimated as the surviving path to the n-th state based on the difference between the code value sequence and the input value sequence that lead to each state transition path. Then, the likelihood of the surviving path estimated at the same time is calculated as a path metric, and each path memory, when estimating the surviving path at the time t, the decoded value at the time t determined by the estimated surviving path; Stored in the relevant path memory or another path memory (t-
The decoded value sequence consisting of the decoded values from the 1) th to (tk) (where k is an integer of 2 or more) is combined, and from time t to time (tk) determined by the estimated surviving path.
When generating a decoded value sequence consisting of the decoded values of and storing a decoded value sequence consisting of the (t−k + 1) th decoded values from time t in the generated decoded value sequence, all the path memories It is determined whether or not the surviving path has converged based on the held value. If it is determined that the surviving path has converged, the path memory for storing information before the time when the surviving path has converged is determined. The operation is stopped except for one arbitrarily (but fixedly) selected path memory, and when it is determined that the surviving paths are not converged, all the path memories continue to be operated. And a convergence state is written therein at each time, and among the decoded values at each time (tk) output from each path memory, the output of the path memory whose operation has not been stopped is decoded. Output as result A Viterbi detector is provided. The Viterbi detector according to the first aspect performs likelihood calculation based on a Viterbi algorithm,
When estimating the decoded value series and storing them in the path memory, it is determined whether or not the surviving path has converged from the values held in each stage of the path memory. If it is determined that the surviving path is converged, the operation is performed except for one (but fixed) path memory that is arbitrarily (fixed) selected from among the path memories that store information before the convergence point. Stop. At that time, a register for storing the convergence state of the surviving path is separately provided, and the convergence state is written therein at each time. Then, of the decoded values at each time output by each path memory, the output of the path memory whose operation has not been stopped is output as the decoding result. This makes it possible to reduce the power consumed in the path memory operation while maintaining the same error occurrence rate as compared with the conventional Viterbi detector.

According to a second aspect, the present invention provides the Viterbi detector according to the first aspect, further comprising a selector having a function of selecting one path memory from a plurality of path memories in each state. If the register that stores the convergence state in tk) indicates that the surviving path is not converged, the path metric that represents the most probable of the path metrics calculated by each surviving path calculating means is The decoded value at the time (tk) in the decoded value sequence corresponding to the calculated surviving path is selected from the decoded values at the time (tk) output from each path memory,
A Viterbi detector is provided which outputs the result as a decoding result of the Viterbi detector. In the Viterbi detector according to the second aspect, since the contents of the path memory corresponding to the state where the path metric becomes the smallest are selected and output at each time, the Viterbi detector is always selected from a specific path memory and is output. The path memory length can be shortened, and hardware and power consumption can be reduced, as compared with the case where the output is taken out.

According to a third aspect, the present invention relates to a signal processing circuit provided with the Viterbi detector according to the first or second aspect, comprising: an analog filter for removing high-frequency noise superimposed on an input signal; An analog-to-digital converter for converting the output signal of the analog filter from analog to digital, and a waveform equalizer for equalizing the digitally converted signal by a predetermined equalization characteristic. A signal processing circuit is provided, wherein an output sequence is an input sequence of the Viterbi detector. The signal processing circuit according to the third aspect uses the Viterbi detector according to the first or second aspect, so that hardware and power consumption can be reduced.

According to a fourth aspect, the present invention is a recording / reproducing apparatus provided with the signal processing circuit according to the third aspect, wherein a recording medium for recording a signal and a signal recorded on the recording medium are read out. A recording / reproducing apparatus comprising: a head unit; and a recording signal read by the head unit as an input signal of the analog filter. In the recording / reproducing apparatus according to the fourth aspect, since the signal processing circuit according to the third aspect is used, hardware and power consumption can be reduced.

According to a fifth aspect, the present invention includes the recording / reproducing apparatus according to the fourth aspect, and an information processing apparatus connected to the recording / reproducing apparatus and using the recording / reproducing apparatus as an external storage device. An information processing system is provided. In the information processing system according to the fifth aspect, since the recording / reproducing apparatus according to the fourth aspect is used, hardware and power consumption can be reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited by this.

First Embodiment FIG. 1 is a configuration diagram of a main part of a magnetic disk drive according to a first embodiment. The magnetic disk device 400 includes a magnetic disk 411, an R / W amplifier 410, and a signal processing circuit 420. The signal processing circuit 42
0 indicates an encoder 401, a precoder 402, an analog filter 403, an A / D converter 404, a waveform equalizer 405, a Viterbi detector 406, and "1 + D modulo".
It is composed of a 2 ″ arithmetic unit 407 and a decoder 408.

The input data to the signal processing circuit section 420 is
The code is converted into a specific code by the encoder 401 and input to the precoder 402. In the precoder 402, data modulation processing is performed. The data recorded on the magnetic disk 411 is binary data, and is “0” or “1”.
Take the value of In the R / W amplifier 410, the precoder 40
The data is recorded on the magnetic disk 411 by generating a signal that is high when the output data of No. 2 is “1” and low when it is “0”.

The reproduced signal is read from the magnetic disk 411 and amplified by the R / W amplifier 410. The analog signal 403 removes high frequency noise and the A / D converter 404 performs analog / digital conversion every predetermined time. As described above, the waveform is equalized by the waveform equalizer 405 so as to have a predetermined response waveform. Note that the reproduced signal is (1-
D) The result of the calculation is obtained. D is a delay operator. The Viterbi detector 406 performs maximum likelihood estimation on the reproduced signal y (t) output from the waveform equalizer 405. The output of the Viterbi detector 406 is “1 + D modulo 2”
After performing the “1 + D modulo 2” operation at 07, the decoder 408 returns to the original input data.

Next, the Viterbi detector 406 corresponding to the PR (1, 0, -1) transmission line will be described. In addition, the present invention
The present invention can be applied to other than the PR (1, 0, -1) transmission path.

FIG. 2 shows a trellis diagram of the PR (1, 0, -1) transmission line. PR (1, 0, -1) when performing maximum likelihood decoding in a transmission path, the combination of inter-symbol interference (state), the four states S ₀ to S _3. Each branch in the trellis diagram, the time (t-1) states in S _i (t-1) state at time t from the input values at the time t S _i (t) is uniquely determined, the time from the state transition This indicates that the output value which is the original data to be decoded at t is also uniquely determined. For example, the branch from S ₀ to S ₀ from left to right is at time (t−
When the state in 1) is S ₀ and the input value at time t is “0”, it indicates that the state at time t is S ₀ and the output value (decoding result) is “0”.

If there is no noise in the reproduced signal, the Euclidean distance (y (t) -z) is obtained from the waveform-equalized signal y (t).
(t)) The target value z (t) (the input value originally represented by the reproduced signal) can be uniquely determined according to ² = 0. But,
Actually, since noise n (t) is included, y (t) = z (t) +
n (t). Therefore, the Viterbi detector 106 determines that the sequence of the signal y (t) represents the sequence of the target value z (t) that minimizes the sum of the Euclidean distance (y (t) −z (t)) ^2. Perform maximum likelihood decoding for estimation.

FIG. 3 is a block diagram of the Viterbi detector 406. The Viterbi detector 406 includes an ACS unit 620 including a branch metric calculation circuit 601 and ACS (Add-Compare-Select) circuits 610 to 613.
And path memories 630-633 and convergence determiner 660
And a path memory unit 621. Said A
CS circuits 610 to 613 and the path memories 630 to 63
3 is provided corresponding to each state S.

When the reproduction signal y (t) is input to the Viterbi detector 406 at time t, the branch metric calculation circuit 601 calculates the target value z (t) corresponding to each branch on the trellis diagram and the target value z (t). The Euclidean distance from the value of the reproduction signal y (t) is calculated. The obtained Euclidean distance is the state S _i
To the corresponding ACS circuits 610 to 613. For example,
In the trellis diagram of FIG. 2, branches toward the state S ₀ There are two, each of the target value z (t) is "0" and "1". In this case, the Euclidean distance between the reproduced signal y (t) and the target value z (t) = 0 and the Euclidean distance between the reproduced signal y (t) and the target value z (t) = 1 are obtained, and the state S ₀ is set. Send to the corresponding ACS circuit 610. From the state S _j (t-1) as described above, S
_The target value z (t) corresponding to the branch toward _i (t) and the reproduced signal y (t)
_Is called a branch metric at the time t of the branch, and is expressed as B _ji (t).

ACS circuits 610, 611, 612, 61
3 calculates the "probability" of the most likely path in a path leading to the state S _i (path) assuming that the current state is _{S 0, S 1, S 2} , S 3 Administration I do. This certainty is called a path metric, and is written as M _i (t). The path memory 630,631,632,633 the current state corresponds to the most likely path of _{S 0, S 1, S 2} , path to the state S _i assuming that the S ₃ Stores a sequence of output values.

The ACS circuit 610 determines that the state at time t is S₀
At time t, assuming that₀Of the two branches leading to
Estimate which branch is more likely. sand
Word, S₀S for (t)₀(t-1) and S₁heading from (t-1)
Since there are two branches, the branch metric calculation circuit
B at time t from 601₀₀(t) and B_Ten(t) is the ACS circuit 6
Sent to 10. Upon receiving this, the ACS circuit 610
S₀(t-1) to S₀calculated at time (t-1) as a branch heading to (t)
Path metric M₀(t-1) and branch metric B₀₀
(t) is added to calculate the path metric. Similarly,
S₁(t-1) to S₀calculated at time (t-1) as a branch heading to (t)
Path metric M₁(t-1) and branch metric B_Ten
(t) is added to calculate the path metric. And
The minimum value of the path metrics obtained in this way is
Make the path you have the most probable path (survival path)
You. And the path metric found for this path
The value at time t is S ₀Assuming that
At time t₀Path metric M leading to₀(t)
You. The ACS circuit 610 is selected in each state.
The output value corresponding to the branch of the surviving path is stored in the path memory 6.
30 and 631, respectively. This output value
May use the output sequence of the encoder 401 as a return value.
The output sequence of the precoder 402 may be used as a return value.
No. In some cases, return the output of waveform equalizer 405
It may be. In the present embodiment, the output of the precoder 402 is
Force is the return value, but is not limited to this. Other A
The same applies to the CS circuits 611 to 613.

The path memory 630 is constituted by a shift register, and receives a time (t-
When the notification of the state of 1) is sent, the time (t-) of the shift register corresponding to the state of the notified time (t-1) is received.
Replace with the contents of 1). Then, the contents of the shift register are shifted by one bit, the one bit at the foremost stage is output as an estimation result, and the output value sent from the ACS circuit 610 is stored in the last stage of the shift register that has become empty. The content of the resulting shift register is
The content of the shift register at time t is the content. By performing this operation at each time, the path memory 63
In 0, an output value sequence corresponding to the surviving path estimated by the ACS circuit 610 is stored in chronological order. Here, in the present invention, rewriting of the shift register is controlled by the convergence determiner 660. That is, the convergence determiner 660 determines whether or not the contents of the pass registers 630 to 633 have converged, sends signals 650 to 653 to the path memories 630 to 633, and controls whether or not to rewrite. The same applies to the other path memories 631 to 633.

FIG. 4 is a configuration diagram of a main part of the path memory unit 621. The path memories 630 to 633 each include a main register for storing a sequence of output values corresponding to the above-described surviving path, a sub-register for temporarily storing the contents of the main register in the above-described rewriting process, It comprises a (sub) selector and write controller for selecting and writing the contents to be written to the sub register, and a (main) selector and write controller for selecting and writing the contents to be written to the main register. FIG. 4 shows a main register (consisting of cell registers 700 to 706) and a sub register (cell registers 720 to 726) of the path memory 630.
), A main register of the path memory 631 (comprising cell registers 710 to 716), and a path memory 6
30 (sub) selector and write controller 740
And a (main) write controller 741 of the path memory 630.

A signal 761 is output to the convergence determiner 660 from all of the main registers 700 to 706 of the main register of the path memory 630. Also, all the cell registers 710 to 71 of the main register of the path memory 631
6 outputs a signal 762 to the convergence determiner 660. Similarly, the other path memories 632, 6
Signals are output to the convergence determiner 660 from all of the 33 main registers.

The convergence determiner 660 is used to indicate whether or not the value of each cell register of the main register has converged.
CF registers 750 to 753 for respectively storing bits
The shift register has the following.

Next, how to rewrite the register will be described by taking the state S ₀ as an example. When the state at time (t-1) is notified from the ACS circuit 610 to the path memory 630, the (sub) selector / write controller 740 of the path memory 630 transmits the notified information from the ACS circuit 610 and the convergence determiner 660. CF registers 750 to 753
Of the main registers of the path memories 630 to 633, and writes the contents to the corresponding cell registers of the sub-registers of the path memory 630. Next, the (main) write controller 741 shifts the contents of the cell registers 720 to 726 of the sub-registers of the path memory 630 by 1 bit, and based on the values of the CF registers 750 to 753 of the convergence determiner 660, the path memory 630 Is selected, and the contents are written to the corresponding cell register of the main register of the path memory 630. next,
The contents of all the main registers are sent to the convergence determiner 660. In each cell register of the main register, when the set of the value of a certain cell register and the value of the cell register one stage after it match in all the main registers, the convergence determiner 660 determines that the surviving path of the cell register is It is determined that the convergence has occurred, and the result of the determination is written to the corresponding CF register as 1-bit information. For example, “0” is written when the convergence is made, and “1” is written when the convergence is not made.

Next, the writing process will be described in more detail with reference to FIGS. FIG. 5 shows PR (1,
0, -1) when maximum likelihood decoding is performed on the transmission path,
It shows an example of a surviving path selection process at each time. The value assigned to each branch is actually stored in the path memory 63.
Decoded values stored in 0 to 633. The portion drawn with a bold line is the portion where the surviving path has already converged.

FIG. 6 shows a process of updating the registers in the path memories 630 to 633 when the decoding process shown in FIG. 5 occurs. The sub register corresponding to the state S ₀ is Sub ₀ , the main register is Main ₀ , and the convergence determiner 66
The register in 0 is denoted as CF. .., Sub0-0 from the left, and these cell registers in Sub0 are referred to as cell register numbers. All other sub-registers, main registers, and CFs are similarly described. The values enclosed by [] in the first column of each sub register are the ACS _i circuits 610 to 613.
Indicates the number of the state in the previous stage selected by.

Time (0): At time (0), the values held in all the sub registers and the main register are undefined.
Sub0-0, ..., Sub0-0 are # 06, ..., #
00, and Sub16,..., Sub1-0, # 16,
, # 10 and # 2 in Sub2-6, ..., Sub2-0
6, ..., # 20, and in Sub3-6, ..., Sub3-0
# 36, ..., # 30. The value held in the main register may be independent of the value held in the sub register.
Here, it is assumed that the same value (undefined value) is held. All the CFs are reset to “1”. This indicates that the values held by the registers have not converged at any stage.

Time (1): ACS is executed and S₀, S₁To
For S₀Is selected, and S_Two, S _ThreeAgainst
And S_ThreeA branch extending from is selected. CF is all "1"
(Survival paths are not converged at any stage)
In b0, the value held by Main0 is stored as it is, and Sub1 is
Stores the value of Main0 as is, and stores it in Sub2
Is the value stored in Main3 as it is, and Sub3 is M
The value held by ain3 is stored as it is. Subregis
When the value of the main register is stored in the
Since it is “1”, the value held in the sub register is 1 bit.
And store it in the main register. At this time, Su
The value held by b0-0 is the output of the Viterbi detector 406.
Output to the outside. Main0-6, Main1-6, Main2-
6, Main 3-6, ACS₀610, ACS₁
611, ACS_Two612, ACS_Three613 output is stored
It is. Then, the value of (Main0-1, Main0-0) becomes (Ma
in2-1, Main2-0), (Main3-1, Main3-0)
Since they match, the surviving path is Main * -0 (* is 0-3)
Are not converged. Where the bits for two times
The convergence state is determined by a set of values because PR (1,0,
-1) Because the state of the transmission path is defined by 2 bits
is there. It was determined that the surviving path did not converge
Then, "1" is written to the corresponding CF0. Likewise
Thus, "1" is also written to CF1 to CF6.

Time (2): ACS is executed and S₀, S₁To
For S₀Is selected, and S_Two, S _ThreeAgainst
And S_TwoA branch extending from is selected. CF is all "1"
So, Sub0 stores the value of Main0 as it is
The value held by Main0 is stored as is in Sub1.
Sub2 stores the value of Main1 as it is.
Sub3 stores the value of Main1 as it is.
You. The value of the main register is stored in the sub register
And CF are all "1", so that the sub-register holds
All values are shifted by 1 bit and stored in the main register
You. At this time, the value held by Sub0-0 is the Viterbi detector
The output 406 is output outside. Main0-6, Mai
n1-6, Main2-6 and Main3-6 have ACS respectively₀
610, ACS₁611, ACS_Two612, ACS_Three61
3 are stored. And (Main0-1, Main0-
0) is (Main1-1, Main1-0), (Main2-
1, Main2-0), (Main3-1, Main3-0)
Surviving pass with Main * -0 (* is 0-3)
Is determined to have converged to one. Survival passes
Since it is determined that they are bundled, the corresponding CF0
“0” is written. Similarly, (Main0-2, Main0-
1) is (Main1-2, Main1-1), (Main2-1)
2, Main2-1), (Main3-1, Main3-1)
Surviving pass in Main * -1 (* is 0-3)
Is determined to have converged to one, and the corresponding CF1
“0” is written. Similarly, CF2 and CF3
Is also written with "0". However, (Main0-5, Main
The values of (0-4) are (Main2-5, Main2-4), (Main3-
5, Main3-4), so Main * -4 (* is 0)
In 3), it is determined that the surviving paths do not converge to one.
Then, "1" is written to the corresponding CF4. Likewise
Thus, "1" is also written in CF5 and CF6.

Time (3): ACS is executed and S₀, S₁To
For S₀Is selected, and S_Two, S _ThreeAgainst
And S_ThreeA branch extending from is selected. Basically, Sub0
Stores the value held by Main0, and Sub1 stores the value of Main0.
Store the value to be stored, and in Sub2, the value to be stored in Main3
Is stored, and the value stored in Main3 is stored in Sub3,
Consider that there is a place where it is "0" in the CF register
You. That is, a cell whose CF register is "0"
Regarding the cell registers of register numbers 3 to 0, first,
Sub0 cell register number 3-0 Cell register Sub0-
3, Sub0-2, Sub0-1, Sub0-0 have Main0-3, M
ain0-2, Main0-1, Main0-0 are written
(As described later, the result of the ACS is
Even if it is not supposed to write 0
Same). On the other hand, the cell registers of Sub1 to Sub3
For the cell registers of numbers 3 to 0, the cell register of Sub0
Cell registers Sub0-3, Sub0-2, 2 of register numbers 3-0
Since Sub0-1 and Sub0-0 hold the convergence result,
Do not burn. In other words, those cell registers (black
Stop clock input to parts 931 and 921)
Confuse. On the other hand, the cell register whose CF register is "1"
Regarding the cell registers of the register numbers 6 to 4, the
Write as usual according to the result. That is, Su
Main0 for b0-6 to Sub0-4 and Sub1-6 to Sub1-4
-6 to Main0-4 are written, and Sub2-6 to Sub2-
Main3-6 to Main3-4 for 4 and Sub3-6 to Sub3-4
Is written.

Next, the value held in the sub-register is shifted by one bit and stored in the main register. Consideration is given to the point that writing is stopped for some cell registers of the sub-register. That is, only Main0 has Sub0 as usual.
Is written by shifting the contents by 1 bit.
3 is a cell register number 3-0 of Sub1 to Sub3.
Of the cell registers of the corresponding cell register numbers 2 to 0 are not written, and those cell registers (portions 93 surrounded by a black frame) are not written.
2, 922) is stopped. On the other hand, Sub
Since the writing to the cell registers Nos. 1 to 3 of the cell registers Nos. 6 to 4 is not stopped, the values held therein are shifted by one bit and written to the cell registers Nos. 5 to 3 of the corresponding main registers. Perform
At this time, the value held by Sub0-0 is the Viterbi detector 40
6 is output to the outside.

As for CF3 to CF1 which was "0" at the previous time, the CF3 to CF1 on the right side are replaced with CF3 to CF1 on the right side.
Shift (935) to F0. Next, the value of (Main0-4, Main0-3) corresponding to CF3 is (Main2-4, Mai
n2-3), (Main3-4, Main3-3)
In Main * -3 (* is 0 to 3), it is determined that the surviving paths do not converge to one, and "1" is written to CF3. Similarly, "1" is written in CF4 to CF6.

Time (4): ACS is executed and S₀, S₁To
For S_TwoIs selected, and S_Two, S _ThreeAgainst
And S_ThreeA branch extending from is selected. Basically, Sub0
Stores the value that Main2 holds, and Sub1 stores the value of Main2.
Store the value to be stored, and in Sub2, the value to be stored in Main3
Is stored, and the value stored in Main3 is stored in Sub3,
Consider that there is a place where it is "0" in the CF register
You. That is, a cell whose CF register is "0"
Regarding the cell registers of register numbers 2 to 0, first,
Sub0 cell register number 2-0 Cell register Sub0-
2, Sub0-1, Sub0-0 have Main0-2, Main0-1,
The contents of Main0-0 are written (the result of ACS is Main
Is the content of 0 written to Sub0?
Even if it does, the contents of Main0 are written to Sub0). This
On the other hand, the cell register numbers 2 to 0 of Sub1 to Sub3
For the sub-registers, Sub0 cell register numbers 2
0 cell registers Sub0-2, Sub0-1, Sub0-0 converge
Since the result is held, those cell registers (in black frame)
Hatched part 9 in enclosed part 943,931
41, 933), while CF
Cell register numbers 6 to 3 whose registers are "1"
For cell registers of
Write as you do. That is, Sub0-6 to Sub0-3
And Sub1-6 to Sub1-3 have Main2-6 to Main2-3
The contents are written, and Sub2-6 to Sub2-3 and Sub3-6
Main3-6 to Main3-3 are written in Sub3-3
It is.

Next, the value held in the sub-register is shifted by one bit and stored in the main register, and it is taken into consideration that writing has been stopped for some cell registers of the sub-register. That is, only Main0 has Sub0 as usual.
Is written by shifting the contents by 1 bit.
For cell No. 3, the cell register numbers 2 to 0 of Sub1 to Sub3
Of the cell registers of the corresponding cell register numbers 1 to 0 (the hatched parts 942, 9 in the parts 944, 932 surrounded by black frames).
Stop writing to 34). On the other hand, since writing to the cell registers Nos. 6 to 3 of Sub1 to Sub3 is not stopped, the values held therein are shifted by one bit, and the cell register numbers 5 to 5 of the corresponding main registers are shifted.
2 is written to the cell register. At this time, Sub
The value held by 0-0 is output to the outside as the output of the Viterbi detector 406.

As for CF2 to CF1 which was “0” at the previous time, the values are replaced with CF1 to C1 on the right side.
Shift to F0. Next, it corresponds to CF2 (Main0
-3, Main0-2) are (Main1-3, Main1-2),
(Main2-3, Main2-2), (Main3-3, Main3-2)
Therefore, in Main * -2 (* is 0 to 3), it is determined that the surviving path has converged to one path, and “0” is written to CF2. Similarly, "0" is also set for CF3.
Is written. Next, it corresponds to CF4 (Main0-
The value of (5, Main0-4) is (Main2-5, Main2-4),
(Main3-5, Main3-4)
In (* is 0 to 3), it is determined that the surviving paths do not converge to one, and “1” is written to CF4. Similarly, “1” is written to CF5 and CF6.

Time (5), Time (6): Basically, time
(3) The same operation as (4) is performed. The black frame portion (951, 961) is not updated by the value held by the CF.
As a result of the convergence determination, at time (5) and time (6), CF6
CF0 is “110000”.

By updating / non-updating the values held in the path memories 630 to 633 while following the above process, a correct result can be output. Then, since the operation of the cell register of the path memory in which the surviving path is converged is stopped, power consumption can be reduced.

FIG. 7 is a configuration diagram of a mechanical unit of the magnetic disk drive 400. The mechanical part of the magnetic disk drive 400
A magnetic disk 411 to which data is written, a spindle motor 1201 for rotating the magnetic disk 411,
A head 1203 for reading data from the magnetic disk 411 and an arm 120 supporting the head 1203
2, a voice coil motor 1204 for moving the head 1203, and an R / W amplifier 410 for amplifying a signal from the head 1203.

FIG. 8 is a configuration diagram of an electronic circuit unit of the magnetic disk drive 400. The electronic circuit unit of the magnetic disk device 400 includes an interface 1220 for connecting to an information processing device such as a host, and an interface 122
Interface control circuit 121 for controlling input / output of 0
0, a magnetic disk device controller 1211 for controlling data transfer and format, etc., a microprocessor 1212, a signal processing circuit 420 for processing signals to the R / W amplifier 1206, and for controlling the spindle motor 1201. Spindle control circuit 1214 and voice coil motor control circuit 1213
It comprises.

Second Embodiment FIG. 9 is a configuration diagram of an information processing system using the magnetic disk device 400. This information processing system 900
Is an information processing device 1300 and its information processing device 130
0 is connected to the magnetic disk drive 400. The information processing device 1300 includes a CPU 1301 and a memory 1302 connected to an internal bus 1305, and a peripheral interface 13 connected to an external bus 1306.
04, the internal bus 1305 and the external bus 1306
And a bridge 1303 for connecting Then, the information processing device 1300 transmits the data 1 of the magnetic disk 411 via the peripheral interface 1304 and the interface 1220 in the magnetic disk device 400.
315 can be read / written.

Third Embodiment In the Viterbi detector 406 of the first embodiment, the value (Sub0-) of the last stage of the path memory (630) corresponding to a specific state.
0) was output as the result of maximum likelihood decoding. in this case,
The path memory length must be long enough to allow the surviving paths to converge in any case. This means
This results in increased hardware and power consumption. On the other hand, there is a method of attaching a path memory selector called an ML selector to a path memory, thereby reducing a required path memory length, and reducing hardware and power consumption.
The third embodiment is an embodiment in which the present invention is applied to a Viterbi detector equipped with an ML selector.

FIG. 10 shows a Viterbi detector equipped with an ML selector. The Viterbi detector 1000 includes a branch metric calculation circuit 1001 and ACS circuits 1010 to 1
0103, an ACS unit 1020, and a path memory 103.
And a path memory unit 1021 including a convergence determiner 1060 and an ML selector 1070. The ACS circuits 1010 to 1013 and the path memories 1030 to 1033 are provided corresponding to respective states S.

The branch metric calculation circuit 100
1, ACS circuits 1010 to 1013, path memory 103
0-1033 and the convergence determiner 1060 are the branch metric calculation circuit 601, AC
The configuration is the same as that of the S circuits 610 to 613, the path memories 630 to 633, and the convergence determiner 660.

The ML selector 1070 has the last value 1073 of all the path memories 1030 to 1033 and the CF
Of the last stage of all the ACS circuits 1010 to 1010
13 is sent at each time.

FIG. 11 is a configuration diagram of a main part of the ML selector 1070. This ML selector 1070 is connected to the comparator 11
00 and a selector 1101. Only when the value of the CF transmitted at a certain time is “1” (that is, the state has not converged), each of the ACS circuits 1010 to 1010
13 is compared with the metric values M _{0 to} M ₃ sent from
The value stored in the path memory corresponding to the state having the minimum metric value is set as the decoding result when the signal passes through the maximum likelihood path. Then, the last value of the path memory corresponding to the state selected here is set as the output of the Viterbi detector. If the last CF is “1”, part of the path memories 1030 to 1033 cannot be stopped in the middle of the state, so that the output from the last path memory by the ML selector 1070 is not possible. Does not select the output from the stopped path memory.

In the third embodiment, the path memory output corresponding to the most probable path is selected and output. Therefore, the path memory length is shorter than in the first embodiment, and the hardware and power consumption are reduced. Can be further reduced.

[0063]

According to the present invention, a Viterbi detector, a signal processing circuit,
According to the recording / reproducing apparatus and the information processing system, power consumption can be reduced without deteriorating the bit error rate of the decoding result.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a signal system model of a magnetic disk drive according to a first embodiment.

FIG. 2 is an input / output relationship for a PR channel and its trellis diagram.

FIG. 3 is a block diagram illustrating a configuration of a Viterbi detector according to the first embodiment.

FIG. 4 is a main part block diagram of a path memory unit in the Viterbi detector of FIG. 3;

FIG. 5 is a trellis diagram illustrating an example of a surviving path in a PR channel.

FIG. 6 is an explanatory diagram showing changes in the contents of the path memory according to the first embodiment.

FIG. 7 is a configuration diagram of a mechanical unit of the magnetic disk drive according to the first embodiment.

FIG. 8 is a configuration diagram of an electronic circuit unit of the magnetic disk device according to the first embodiment.

FIG. 9 is a block diagram illustrating a configuration of an information processing system according to a second embodiment.

FIG. 10 is a block diagram illustrating a configuration of a Viterbi detector according to a third embodiment.

FIG. 11 is a block diagram of an ML selector.

FIG. 12 is a block diagram illustrating a signal system model of the magnetic disk drive.

FIG. 13 is an input / output relationship for an EPR channel and its trellis diagram.

FIG. 14 is a block diagram illustrating a configuration of an example of a conventional Viterbi detector.

[Explanation of symbols]

400: magnetic disk device 405: waveform equalizer 406, 1000: Viterbi detector 411: magnetic disk 420: signal processing circuit 601, 1001: branch metric calculation circuit 610-613, 1010-1013: ACS circuit 620, 1020: ACS Circuit units 621, 1021: Path memory units 630-633, 1030-1033: Path memories 660, 1060: Convergence determiner 700-736: Cell register of main register of path memory 630 740: (sub) selector of path memory 630 Write controller 741: (Main) write controller of path memory 630 750 to 753: CF register in convergence determiner 660 900: Information processing system 921, 922, 931, 932: Register that cannot be rewritten at time (3) Minutes 933, 934, 941, 942: Register portion not rewritten at time (4) 935: Arrow indicating shifting of values held in CF register 951, 952: Register portion not rewritten at time (5) 961 , 962: Register portion that cannot be rewritten at time (6) 1070: ML selector 1100: Comparator 1101: Selector 1300: Information processing device

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyuki Yamakawa 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. (72) Takashi Nara 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 In the Semiconductor Division of Hitachi, Ltd. (72) Inventor Hiroshi Ide 5-2-1, Kamimihoncho, Kodaira-shi, Tokyo F-term in the Semiconductor Division of Hitachi, Ltd. F-term (reference) 5B001 AA10 AB05 AC03 AD04 5D044 FG01 GL31 GL32 5J065 AA01 AB01 AC02 AD10 AE06 AF03 AG05 AH23

Claims (5)

[Claims] In a discrete time system, N states (N is 2) in which a state at a time t is determined by a code value at a time t (where t is a natural number of 2 or more) and a state at a time (t-1). Is a system in which each state is represented by one bit or a plurality of bits, and the state transition at time (t-1) to the state at time t causes time t A Viterbi detector for determining a decoded value sequence from an input value sequence in which an error is superimposed on a code value sequence, for a code having a characteristic in which a decoded value is determined. It has a plurality of surviving path calculating means provided respectively and a plurality of path memories, and each surviving path calculating means reaches the n-th state on the assumption that there is an n-th state. The most probable state transition path The estimated state transition path is estimated as a surviving path to the n-th state based on the difference between the code value sequence and the input value sequence that lead to each state transition path, and the likelihood of the estimated surviving path is determined. Each path memory is calculated as a path metric, and when each path memory estimates the surviving path at the time t, the decoded value at the time t determined by the estimated surviving path is stored in the path memory or another path memory. From (t-1) th to (tk)
(Where k is an integer of 2 or more) is combined with a decoded value sequence composed of the decoded values to generate a decoded value sequence composed of the decoded values from time t to time (tk) determined by the estimated surviving path, When storing a decoded value sequence consisting of the (t−k + 1) th decoded values from time t to time t in the generated decoded value sequence, surviving paths converge from values held in all path memories. It is determined whether or not the surviving path has converged, and if it is determined that the surviving path has converged, one (arbitrarily fixed) selected one of the path memories for storing information before the time of convergence. When the operation is stopped except for one path memory and it is determined that the surviving paths have not converged, all the path memories continue to operate, and at that time, a register for storing the convergence state of the surviving path is provided, and a register is provided there. Each time the convergence state Writing each, of the decoded value at each time (tk) of each path memory output, Viterbi detector and outputs the output of the path memory that did not stop the operation as a decoding result. 2. The Viterbi detector according to claim 1, further comprising a selector having a function of selecting one path memory from a plurality of path memories in each state, and storing a convergence state at time (tk). Register is
If the surviving path indicates that it has not converged,
Medium time (tk) of the decoded value sequence corresponding to the surviving path for which the path metric representing the most likely path metric among the path metrics calculated by each surviving path calculating means is calculated.
At the time (t-
A Viterbi detector which selects from among the decoded values of k) and outputs the result as a decoding result of the Viterbi detector. 3. A signal processing circuit comprising the Viterbi detector according to claim 1, wherein the analog filter removes high-frequency noise superimposed on an input signal, and an output signal of the analog filter. And a waveform equalizer for equalizing the digitally converted signal with a predetermined equalization characteristic, and outputting the output sequence of the waveform equalizer to the Viterbi detector. A signal processing circuit characterized in that the input series is an input series. 4. A recording / reproducing apparatus comprising the signal processing circuit according to claim 3, comprising: a recording medium for recording a signal; and a head unit for reading a signal recorded on the recording medium. A recording signal read out by the unit as an input signal of the analog filter. 5. An information processing system comprising: the recording / reproducing apparatus according to claim 4; and an information processing apparatus connected to the recording / reproducing apparatus and using the recording / reproducing apparatus as an external storage device. .