JP2001144299A - Thin-film transistor array substrate and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control etching amount at a channel part by measuring the film thickness of a source electrode from an etching-resistant reference surface, which is not etched at the etching of the channel part. SOLUTION: Related to a thin-film transistor substrate of 'In-Plane Switching' mode channel digging type, an etching-resistant reference surface 23, which is not etched at etching of a channel part 24, is formed on a gate insulating film 15, and a part of the etching-resistant reference surface 24 is formed under the layer of a source electrode 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor (TFT) array substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the size of liquid crystal display devices has increased, the resistance of wiring materials has been required to be lower, and at the same time, the need for a higher viewing angle has been increasing. Therefore, a low-resistance material such as aluminum, molybdenum, or an alloy thereof is used as a wiring material.
An In-Plane Switching (hereinafter referred to as IPS) mode in which a pixel electrode and a common electrode are formed in a comb-like shape in one pixel of the FT and a liquid crystal is operated by applying a voltage between them in a horizontal direction is widely used. It has become.

However, for example, when aluminum or an aluminum alloy is used for a drain wiring, a drain electrode, and a source electrode of a TFT array substrate, there has been a problem that good contact cannot be made with a transparent conductive film or a semiconductor layer.

To solve this problem, a technique of capping aluminum or aluminum alloy with chromium, titanium, or the like has been developed. However, in order to prevent the number of steps from increasing, the capping film and the drain electrode and the like are integrally etched. There is a problem that it is difficult to control the etching shape.

In addition, aluminum and aluminum alloy generally have poor resistance to an alkali cleaning solution or an amine-based resist stripping solution used for cleaning a TFT array glass substrate, and it is necessary to apply a new chemical.

On the other hand, similarly, when molybdenum or its alloy is used, problems such as aluminum and aluminum alloy cannot occur, but there is a problem that the channel etching amount cannot be measured using a contact type step difference measuring device.

Here, there is a common electrode on the counter substrate side,
TFT using ITO for the pixel electrode on the TFT array substrate side
A method of measuring a channel etching amount by a contact-type step measuring device on an array substrate will be described with reference to FIGS.

FIG. 15 shows a film lamination state after channel etching, and FIG. 16 shows an output waveform obtained by measuring a step portion around a channel portion using a contact type step meter.

In FIG. 15, reference numeral 12a denotes a gate electrode, 1
5 is a gate insulating film, 16 is a non-doped semiconductor layer, 17 is an n-type semiconductor layer, 18 is a drain electrode, 19 is a source electrode, 24 is a channel portion, and 38 is a pixel electrode portion.

The channel portion 24 is etched using the source electrode 19 and the drain electrode 18 as a mask.
6 is the sum of the channel etching amount and the film thickness of the source electrode 19 or the drain electrode 18. When subtracted, the channel etching amount can be measured, and this can be expressed by the following equation.

Channel etching amount of the channel portion 24 =
(Thickness of source electrode 19 + etching amount of channel portion 24)-(Thickness of source electrode 19) = Step size as shown in FIG. 16-Step size as shown in FIG. Is a formation region of the source electrode 19, a formation region of the n-type semiconductor layer 17 to be etched of the channel portion 24, a formation region of the source electrode 19 and the pixel electrode portion 38, and a formation region of the pixel electrode portion 38. The step size shown in FIG. 16 is obtained from the formula of the film thickness of the source electrode 19−the film thickness of the pixel electrode section 38.

However, in an IPS mode TFT array substrate in which the drain electrode 18, the source electrode 19, the drain wiring 20, and the pixel electrode 21 are formed of molybdenum or its alloy, for example, in Japanese Patent Application Laid-Open No. 10-48671,
When channel dry etching is performed using a mixed gas of SF ₆ , HCl, and He, the drain electrode 18, the source electrode 19, and the gate insulating film 15 exposed on the surface other than the n-type semiconductor layer 17 are also slightly etched. The thickness of the source electrode 19 cannot be measured accurately, and the channel etching amount cannot be measured.

This will be described with reference to FIGS. FIG. 11 shows a film lamination state after channel etching. FIG. 12 shows an output waveform obtained by measuring a step portion around the channel portion 24 using a contact type step difference measuring device. The broken line shows the step waveform around the channel portion 24 before channel etching, and the solid line shows the channel waveform. This shows a step waveform around the channel portion 24 after the etching.

In FIG. 11, the surface of the gate insulating film 15 serving as a reference surface for measuring the thickness of the source electrode 19 is etched by channel dry etching. (The thickness of the source electrode 19 + the etching amount of the gate insulating film 15), making it impossible to measure the thickness of the source electrode 19 accurately. As a result, the channel etching amount cannot be measured accurately, and the yield decreases. And the problem of quality deterioration has occurred.

Therefore, the drain electrode 18, the source electrode 1
9, an IPS mode TFT array substrate in which the drain wiring 20 and the pixel electrode 21 are formed of chromium.
In Japanese Patent No. 48671, the drain electrode 18, the source electrode 19, and the gate insulating film 15 that are exposed on the surface other than the n-type semiconductor layer 17 are exposed by channel dry etching using a mixed gas of SF 6, HCl, and He. Since the drain electrode 18 and the source electrode 19 are not etched, the thickness of the source electrode 19 is measured before the channel etching, and the sum of the thickness of the source electrode 19 and the channel etching amount is measured after the channel etching. The measurement of the etching amount becomes possible.

This will be described with reference to FIGS. FIG. 13 shows a film lamination state after channel etching. FIG. 14 shows an output waveform obtained by measuring a step portion around the channel portion 24 using a contact type step measuring device. A broken line shows a step waveform around the channel portion 24 before channel etching, and a solid line shows channel etching. This shows a step waveform around the channel section 24 later.

In FIG. 13, since the thickness of the source electrode 19 is not etched when the channel portion 24 is etched, there is no problem if the thickness is measured before the channel portion 24 is etched. That is, the first step measurement is performed in the state of the broken line in FIG. 14 before the etching of the channel portion 24, and the film thickness of the source electrode 19 (the step size shown in FIG. 14) is measured.

Next, a second step measurement is performed in the state of the solid line after the etching of the channel portion 24 shown in FIG. 14, and (the film thickness of the source electrode 19 + the etching amount of the channel portion 24)
By measuring (the step size shown in FIG. 14), the etching amount of the channel portion 24 can be measured, and this can be expressed by the following formula.

The etching amount of the channel portion 24 = (the thickness of the source electrode 19 + the etching amount of the channel portion 24)-
(Thickness of source electrode 19) = (Step size from FIG. 14) − (Step size from FIG. 14)

[0020]

However, the technique according to the prior art shown in FIGS. 13 and 14 can accurately measure the etching amount of the channel portion 24, but can measure the etching amount of the channel portion 24. This causes a problem that the number of steps is increased by one, and a problem that a defect due to dust attached to the substrate before etching of the channel portion 24 is caused.

To solve the above problem, the source electrode 1
It is necessary to have a structure capable of accurately measuring the film thickness of No. 9.

However, JP-A-3-192728, JP-A-5-323369, and Patent No. 284
No. 6,681 or the like was examined in detail, but none of them discloses or suggests a structure capable of accurately measuring the thickness of the source electrode 19.

An object of the present invention is to solve these drawbacks by measuring the film thickness of a source electrode from an etching resistance reference plane which is not etched at the time of etching a channel portion, and enabling the amount of etching of the channel portion to be controlled. An object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same.

[0024]

In order to achieve the above object, a thin film transistor array substrate according to the present invention comprises
In a Plane Switching mode channel dug-in type thin film transistor substrate, an etching resistant reference surface that is not etched when a channel portion is etched is formed on a gate insulating film, and a part of the etching resistant reference surface is a source electrode or a drain electrode. Alternatively, it is formed below or above the drain wiring.

The etching resistance reference surface is formed of a transparent conductive film such as indium tin oxide.

The source electrode, the drain electrode or the drain wiring is a single layer film or a laminated film of molybdenum, tungsten, or an alloy thereof.

Further, the method for manufacturing a thin film transistor array substrate according to the present invention comprises the steps of:
In the method for manufacturing an ng mode channel dug-in type thin film transistor substrate, an etching resistance reference surface is formed on a gate insulating film with a film which is not etched at the time of etching a channel portion, and a part of the etching resistance reference surface is
It is formed in a lower or upper layer of a source electrode, a drain electrode, or a drain wiring.

Further, the etching resistance reference surface is formed of a transparent conductive film such as indium tin oxide.

Further, the source electrode, the drain electrode or the drain wiring is formed of a single layer film or a laminated film of molybdenum, tungsten, or an alloy.

Further, the etching resistance reference surface is formed in the same step as the terminal forming step of the thin film transistor.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a conceptual diagram showing a general thin film transistor (TFT) array substrate, and FIG.
In Plane Switching (hereinafter referred to as IPS)
FIG. 3 is a cross-sectional view showing a thin film transistor (TFT) array substrate according to the first embodiment of the present invention. It is sectional drawing which follows the A line.

A thin film transistor (TFT) array substrate according to the first embodiment of the present invention will be described by taking the IPS mode inverted staggered channel dug-in type TFT array substrate shown in FIGS. 1 to 3 as an example.

The IPS mode inverted staggered channel digging type TFT shown in FIGS. 1 to 3 has a gate wiring 12 and a gate electrode 12 a selectively formed on a transparent glass substrate 11.
An island-shaped non-doped semiconductor layer 16 facing the gate electrode 12a via the gate insulating film 15, and an n-type semiconductor layer 1
The structure has a pair of a drain electrode 18 and a source electrode 19 that are connected to the non-doped semiconductor layer 16 via the gate electrode 7.

Further, the gate wiring 12 selectively formed on the transparent glass substrate 11 and connected to the gate electrode 12a
And a common wiring 13 connected to the common electrode 13 and the common electrode, and a gate wiring 12 via a gate insulating film 15.
Wiring 2 which intersects with and is connected to the drain electrode 18
1 and the pixel electrodes 21 connected to the source electrodes 19 are arranged in a matrix as shown in FIG. 1 to form an active matrix substrate.

Here, the TFT is configured as a horizontal TFT in which a gate electrode 12a is formed on the gate wiring 12. In addition, the gate wiring 12 and the drain wiring 2
A gate terminal 32 and a drain terminal 33 for connecting to an external drive circuit are formed at the start end of 0.

As shown in FIGS. 3 and 5, the thin film transistor (TFT) array substrate according to the first embodiment of the present invention comprises:
In the IPS mode channel dug-in type thin film transistor substrate, an etching resistant reference surface (hereinafter, referred to as a reference pattern) 23 which is not etched when the channel portion 24 is etched is formed on the gate insulating film 15, as shown in FIGS. 3 and 5B. As shown, a part of the etching resistance reference surface 23 is formed in a lower layer (or upper layer) below the source electrode 19 (or the drain electrode 18 or the drain wiring 20).

The reference pattern 23 is formed of a transparent conductive film such as indium tin oxide.
9. The drain electrode 18 or the drain wiring 20 is formed of a single layer film or a stacked film of molybdenum, tungsten, or an alloy thereof.

The effects of the thin film transistor (TFT) array substrate according to the first embodiment of the present invention as shown in FIGS. 3 and 5 will be described in detail in the course of explaining the manufacturing method.

Next, a method of manufacturing a TFT (thin film transistor) array substrate according to the first embodiment of the present invention will be described with reference to FIGS.

The TFT portion shown in FIGS. 4 to 6 is a cross-sectional view taken along the line AA of FIG. 2, similarly to FIG.

First, as shown in FIG. 4A, a low-resistance high-melting-point metal, for example, molybdenum is formed on a glass substrate to a thickness of about 300 nm by sputtering, and then a photolithography method, for example, 2 and a common electrode 14 shown in FIG. 2 and a gate lead line 31 shown in FIG.
And a gate electrode 12a. Although not shown in FIG. 4A, the common electrode 13 and the common lead line are also formed at the same time.

Next, as shown in FIG.
A gate insulating film 15 made of, for example, silicon nitride or silicon oxide is formed to a thickness of about 500 nm on the transistor portion, the drain terminal portion, and the gate terminal portion of the substrate by the method D.

Further, as shown in FIG.
The non-doped semiconductor layer 16 and the n-type semiconductor layer 17 are sequentially formed to a thickness of about 300 nm and a thickness of about 50 nm in the transistor portion of the substrate by using the VD method.

Subsequently, as shown in FIG. 4B, the n-type semiconductor layer 1 is formed by photolithography and a dry etching method using a mixed gas of SF ₆ , HCl and He, for example.
7 and the non-doped semiconductor layer 16 only are etched, and the island-shaped non-doped semiconductor layer 16 is formed in the transistor portion of the substrate.
And an n-type semiconductor layer 17 is formed.

Next, as shown in FIG. 4C, a transparent conductive film, for example, an ITO transparent conductive film having a thickness of about 50 nm is formed on the transistor portion, the drain terminal portion and the gate terminal portion of the substrate by sputtering. The transparent conductive film is used to form a reference pattern 23 in the transistor region of the substrate and a gate terminal 32 in the gate terminal region of the substrate by photolithography and wet etching with aqua regia, for example. Is formed in the drain terminal region of the substrate. Although not shown, the common terminal shown in FIG. 2 is also formed simultaneously using the transparent conductive film. The effect of the reference pattern (etching resistance reference plane) 23 which is a feature of the present invention will be described later in detail.

Next, as shown in FIG. 5A, using a photolithography method and a dry etching method using a mixed gas of CF ₄ , CHF ₃ and O ₂ , for example, the gate insulating film 15 in the gate terminal region of the substrate is used. A contact hole 35 is formed on the gate lead line 31. Although not shown, a contact hole is similarly formed in the common terminal portion of the substrate by using the photolithography method and the dry etching method.

Next, as shown in FIG.
The transistor part of the substrate and the drain terminal
Low-resistance high-melting point metal such as
Approximately 300 nm thick film of lybdenum
Lithography method and, for example, Cl _Two, O_Two, He mixed gas
Using a dry etching method
A drain electrode 18 and a source electrode 19 in
A drain lead wire 34 is
The gate terminal lead metal 36 is placed in the gate terminal area of the board.
Form each.

Although not shown, a common terminal lead metal is similarly formed in the common terminal portion region of the substrate using the low-resistance high-melting metal, and in addition, the drain wiring 20 shown in FIG. 2 is formed at the same time. Further, the low-resistance high-melting-point metal comprises a patterned non-doped semiconductor layer 16 and n
The drain electrode 18 and the source electrode 19 are formed along the side walls of the non-doped semiconductor layer 16 and the n-type semiconductor layer 17 and are also patterned to adhere to the side walls of the type semiconductor layer 17.
It is formed in a state of being superimposed on the peripheral portion of the mold semiconductor layer 17.

Next, as shown in FIG. 6A, using the drain electrode 18 and the source electrode 19 as a mask, for example,
Using a dry etching method with a mixed gas of F ₆ , HCl and He, the drain electrode 18 and the source electrode 1 of the mask are formed.
The channel portion 24 is formed by removing the n-type semiconductor layer 17 exposed from 9. Therefore, the channel part 24 is formed in a region of the non-doped semiconductor layer 16 between the drain electrode 18 and the source electrode 19 formed in a state of being superimposed on the periphery of the non-doped semiconductor layer 16 and the n-type semiconductor layer 17.

When the production has progressed to the state of the structure shown in FIG. 6A, the channel 2
The digging amount of No. 4 is measured.

Here, the necessity of measuring the depth of the channel portion 24 and the method thereof will be described with reference to FIGS. 7 and 8. FIG.

FIG. 7 shows a state of film lamination after channel etching. FIG. 8 shows an output waveform obtained by measuring a step portion around the channel portion 24 using a contact type step measuring device. A broken line shows an output waveform obtained by measuring a step portion before channel etching, and a solid line shows a channel etching. It shows an output waveform obtained by measuring a later step portion.

First, the necessity of measuring the digging amount (channel etching amount) of the channel portion 24 will be described.

In the channel etching of the channel portion 24, only the n-type semiconductor layer 17 may be removed. However, when the n-type semiconductor layer 17 is etched, selective etching with the non-doped semiconductor layer 16, which is the base, is performed. Is difficult to do.

Further, in consideration of the uniformity of the channel etching amount in the TFT array substrate and the inability to use an endpoint detector for detecting the point when the etching amount is reached, it is necessary to overetch the non-doped semiconductor layer 16. .

The amount of over-etching for over-etching the non-doped semiconductor layer 16 is a very important value. If the amount of over-etching is too small, the n-type semiconductor layer 17 remains in the channel portion 24 and the drain is turned off when the transistor is turned off. If a leak current flows between the electrode 18 and the source electrode 19, and if the amount of over-etching is too large, the thickness of the non-doped semiconductor layer 16 in the channel portion 24 becomes small, and the drain electrode is turned off when the transistor is turned on. A sufficient current does not flow between the source electrode 18 and the source electrode 19, and the TFT does not operate normally.

There is a possibility that the production of the TFT having the operation failure will proceed until the final shipment inspection of the liquid crystal module. In order to improve the yield, the amount of channel etching for over-etching the non-doped semiconductor layer 16 is controlled. That is a very important factor.

Therefore, it is necessary to measure the channel etching amount of the channel portion 24 during the manufacturing process.

Next, a method for measuring the channel etching amount of the channel section 24 will be described. Since the channel etching of the channel portion 24 is performed using the source electrode 19 and the drain electrode 18 as a mask, the step size between the region indicated by the dotted line in FIG. When the channel etching of the channel portion 24 progresses as shown by the solid line in FIG. 8, the dimension value of the step portion with respect to the region shown by the dotted line in FIG. 8 and the film thickness of the source electrode 19 or the drain electrode 18 are obtained. , The channel section 24
Can be measured, and this can be expressed by the following formula.

Channel etching amount of channel portion 24 =
(Thickness of source electrode 19 + amount of channel etching of channel portion 24)-(Thickness of source electrode 19) = (Step size with FIG. 8)-(Step size with FIG. 8) FIG. Reference numeral 8 denotes a region where the source electrode 19 is formed, and denotes a region where the n-type semiconductor layer 17 to be etched of the channel portion 24 is formed.

In the present invention, the reason why the film thickness of the source electrode 19 can be measured is that the reference pattern 23 made of ITO is applied to the transistor portion of the substrate in the manufacturing stage of measuring the channel etching amount of the channel portion 24. This is because it is formed so as to be exposed on the surface.

That is, in the above-described channel etching of the channel portion 24, the drain electrode 18, the source electrode 19, and the gate insulating film 15 exposed on the surface other than the n-type semiconductor layer 17 are slightly etched. Is made of a material having etching resistance and is not etched, so that it can be used as a reference surface for measuring the thickness of the source electrode 19.

It is conceivable to measure the film thickness of the source electrode 19 before channel etching of the channel portion 24 and use this as a reference. However, at the time of channel etching of the channel portion 24, molybdenum which is a constituent material of the source electrode 19 is used. Is etched, and the film thickness of the source electrode 19 is reduced. Therefore, even if the film thickness of the source electrode 19 is measured before the channel etching of the channel portion 24, the measured value cannot be used. It is meaningful that the reference pattern 23 having etching resistance is formed on the surface of the transistor portion of the substrate so as to be exposed on the surface in the manufacturing stage of measuring the channel etching amount of the channel portion 24.

As described above, the channel etching amount for over-etching the non-doped semiconductor layer 16 is inspected, and the channel etching amount for over-etching is controlled to an appropriate value to continue the manufacturing.

After the amount of channel etching for over-etching the non-doped semiconductor layer 16 is controlled to an appropriate value and the film thickness of the non-doped semiconductor layer 16 in the channel portion 24 becomes an appropriate state, the next manufacturing process is continued. Done.

That is, as shown in FIG. 6B, after the above-described step measurement is completed, a passivation film is formed as a final step. Specifically, for example, a silicon nitride film is formed as a passivation film 22 to a thickness of about 200 nm on the entire surface of the substrate using a plasma CVD method, and the gate terminal portion of the substrate is formed using a photolithography method and a wet etching method using BHF. Passivation film 22
An opening 37 is formed in the opening. Finally, perform the annealing process,
Complete the TFT array substrate.

As described above, according to the present invention, the thickness of the source electrode 19 is accurately measured by using the contact-type step difference measuring device, and the channel depth, particularly the non-doped semiconductor layer 16 is measured.
The amount of channel etching for over-etching can be accurately controlled to an appropriate value, and the yield and quality can be improved. Further, the above-described effects can be obtained without moving to another manufacturing line in the middle of the manufacturing process and without increasing the number of processes using a series of manufacturing lines.

(Embodiment 2)

In the first embodiment of the present invention, the drain electrode 1
8, the high melting point metal molybdenum which is etched in the etching process of the channel portion 24 is used as the source electrode 19 and the drain wiring 20, but a metal which is not etched, for example, chromium may be used.

FIG. 9 shows a film stacking state after channel etching when chromium is used, and FIG. 10 shows an output waveform obtained by measuring a stepped portion before and after channel etching. The dashed line in FIG. 10 shows the output waveform measured at the step before the channel etching, and the solid line shows the output waveform measured at the step after the channel etching.

In the second embodiment of the present invention, similarly to the first embodiment, it is possible to measure the etching amount of the channel portion 24 by the following calculation method. Although the step portion was measured, the channel etching amount for over-etching the non-doped semiconductor layer 16 was inspected only by measuring the step portion once after the channel portion 24 was etched, and the channel etching amount for over-etching the non-doped semiconductor layer 16 was measured. Can be controlled to an appropriate value, and the process can be shortened.

Etching amount of channel portion 24 = (film thickness of drain electrode 18 + etching amount of channel portion 24) −
(Film thickness of drain electrode 18) = (step size in FIG. 10) − (step size in FIG. 10) Here, FIG. 10 shows a region where source electrode 19 is formed, and FIG. Is a region where the n-type semiconductor layer 17 to be etched is formed.

(Embodiment 3)

In the second embodiment of the present invention, after forming a reference pattern 23 as an etching resistance reference plane, the drain electrode 18, the source electrode 19 and the drain wiring 20 are formed.
Are formed in this order, but even if the order is reversed, the step waveform does not change, and the same effect as in the second embodiment can be obtained.

[0076]

As described above, according to the present invention, the thickness of the source electrode is accurately measured by using the contact-type step measuring device,
The channel digging amount, particularly the channel etching amount for over-etching the non-doped semiconductor layer, can be accurately controlled to an appropriate value, and the yield and quality can be improved. Further, the above-described effects can be obtained without moving to another manufacturing line in the middle of the manufacturing process and without increasing the number of processes using a series of manufacturing lines.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a general thin film transistor (TFT) array substrate.

FIG. 2 is a plan view showing a channel dug-type thin film transistor (TFT) using an In Plane Switching (hereinafter referred to as IPS) mode.

FIG. 3 is a sectional view showing a thin film transistor (TFT) array substrate according to Embodiment 1 of the present invention,
It is sectional drawing which follows the -A line.

FIG. 4 shows a thin film transistor (T) according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a method of manufacturing an FT) array substrate in the order of steps.

FIG. 5 shows a thin film transistor (T) according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a method of manufacturing an FT) array substrate in the order of steps.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a thin film transistor (TFT) array substrate according to Embodiment 1 of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing a state after etching a channel portion in the method for manufacturing a thin film transistor (TFT) array substrate according to the first embodiment of the present invention.

8 is a diagram showing an output waveform obtained by measuring a step portion around a channel portion using a contact-type step difference measuring device in the manufacturing stage shown in FIG. 7;

FIG. 9 is a cross-sectional view showing a state after etching a channel portion in the method for manufacturing a thin film transistor (TFT) array substrate according to the second embodiment of the present invention.

FIG. 10 is a diagram showing an output waveform obtained by measuring a step portion around a channel portion using a contact-type step difference measuring device in the manufacturing stage shown in FIG. 9;

FIG. 11 is a cross-sectional view showing a state after etching a channel portion in a method for manufacturing a thin film transistor (TFT) array substrate according to a conventional example.

12 is a diagram showing an output waveform obtained by measuring a step portion around a channel portion using a contact-type step difference measuring device in the manufacturing stage shown in FIG. 11;

FIG. 13 is a cross-sectional view showing a state after etching a channel portion in a method of manufacturing a thin film transistor (TFT) array substrate according to a conventional example.

14 is a diagram showing an output waveform obtained by measuring a step portion around a channel portion using a contact-type step difference measuring device in the manufacturing stage shown in FIG.

FIG. 15 is a cross-sectional view showing a state after etching a channel portion in a method of manufacturing a thin film transistor (TFT) array substrate according to a conventional example.

16 is a diagram showing an output waveform obtained by measuring a step portion around a channel portion using a contact-type step difference measuring device in the manufacturing stage shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Transparent glass substrate 12 Gate wiring 12a Gate electrode 13 Common electrode 14 Common wiring 15 Gate insulating film 16 Non-doped semiconductor layer 17 N-type semiconductor layer 18 Drain electrode 19 Source electrode 20 Drain wiring 21 Pixel electrode 22 Passivation insulating film 23 Reference pattern (resistance resistance) (Etching reference surface) 24 channel portion 31 gate lead line 32 gate terminal 33 drain terminal 34 drain lead line 35 contact hole 36 gate terminal lead metal 37 passivation film opening

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA14 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA05 KA07 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA35 MA37 NA04 NA25 QA18 4M11 AA10A01A01 AB01 AA12 AA14 AA42 AA43 AA44 BA03 BA43 CA19 DA13 DB01 DB04 EA04 EA05 EB02 FA01 FA02 FB02 FB12 FB14 FB15 GB10 5F110 AA24 BB01 CC07 DD02 EE04 EE44 FF02 FF03 FF30 GG24 HJ01 HJ04 Q04 NN04 HK04 NN04

Claims (7)

[Claims] 1. In-Plane Switching
In the mode channel dug-in type thin film transistor substrate, an etching resistant reference surface that is not etched when etching the channel portion is formed on the gate insulating film, and a part of the etching resistant reference surface is a source electrode, a drain electrode, or A thin film transistor array substrate formed in a lower layer or an upper layer of a drain wiring. 2. The thin film transistor array substrate according to claim 1, wherein the etching resistance reference surface is formed of a transparent conductive film such as indium tin oxide. 3. The thin film transistor array substrate according to claim 1, wherein the source electrode, the drain electrode, or the drain wiring is a single-layer film or a stacked film of molybdenum, tungsten, or an alloy thereof. 4. In-plane switching
In the method for manufacturing a mode channel dug-in type thin film transistor substrate, an etching-resistant reference surface is formed on a gate insulating film with a film that is not etched at the time of etching a channel portion, and a part of the etching-resistant reference surface is formed as a source electrode, Alternatively, a method for manufacturing a thin film transistor array substrate, which is formed below or above a drain electrode or a drain wiring. 5. The method according to claim 4, wherein the etching resistance reference surface is formed of a transparent conductive film such as indium tin oxide. 6. The thin film transistor array substrate according to claim 4, wherein the source electrode, the drain electrode, or the drain wiring is formed of a single layer film or a stacked film of molybdenum, tungsten, or an alloy thereof. Method. 7. The method for manufacturing a thin film transistor array substrate according to claim 4, wherein the etching resistant reference surface is formed in the same step as a step of forming a terminal of the thin film transistor.