JP2001144295A - Communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide communication equipment for fast operation without impairing roductivtiy. SOLUTION: A first channel region 15c, formed in a polycrystalline semiconductor film 15 formed on an insulating substrate 10, and a second channel region 15c formed in the polycrystalline semiconductor film 15, are provided. Here, the first channel region 15c comprises at least one grain boundary, while the second channel region 15c comprises substantially no grain boundary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device, and more particularly, to a communication device provided with various active elements requiring different operation speeds.

[0002]

2. Description of the Related Art Various methods for forming a semiconductor film on an insulating substrate such as glass have been developed and put to practical use. For example, an amorphous silicon semiconductor film formed by a plasma CVD method using a deposition gas such as silane can be formed over a large area at a low temperature, and thus is used for a liquid crystal display device or the like. However, since the mobility of the amorphous silicon semiconductor film is low, it is difficult to configure a driver circuit which requires high-speed operation.

However, a polycrystalline silicon semiconductor film obtained by polycrystallizing an amorphous silicon semiconductor film by, for example, excimer laser annealing (ELA) or the like is attracting attention because it can secure a relatively sufficient mobility, and has been put to practical use. Is being transformed.

[0004]

The polycrystalline silicon semiconductor film described above has a crystal grain size of at most about several μm, depending on the manufacturing method. For this reason, it was still difficult to form a circuit element having a high operation speed, but various improvements have been reported in recent years.

For example, Matsumura et al. In Euro Display 99, 351 proposed a technique for laterally growing a crystal by arranging a phase shift mask and spatially modulating the intensity of a laser beam incident on an amorphous silicon semiconductor film. I have. According to this, it is reported that a particle size of 5 μm or more was obtained and a mobility of 450 cm ² / Vs or more was achieved.

Further, IEEE Electron Device Letters, vo
In l.19 No.8 (1998) 306, Crowder et al. provide a mask exposure function to an ELA optical system and irradiate an amorphous silicon semiconductor film with a laser using a mask having a chevron-type light-shielding portion. Thus, it is reported that a crystal grows with the shadow portion at the tip of the chevron as a nucleus, and that the substrate is moved at a pitch of 0.5 to 0.7 μm to promote lateral growth and obtain a grain size of 10 μm or more.

[0007] However, all of the above methods are inferior in productivity and cannot achieve a reduction in the cost of the apparatus.

Accordingly, an object of the present invention is to provide a communication device capable of high-speed operation without significantly impairing productivity.

[0009]

According to a first aspect of the present invention, there is provided an insulating substrate, a polycrystalline semiconductor film formed on the insulating substrate, and a polycrystalline semiconductor film formed in the polycrystalline semiconductor film. A communication device comprising: first and second channel regions; and a transmission / reception circuit disposed on the insulating substrate, wherein a plurality of signal lines and scanning lines are arranged on the insulating substrate in a matrix. A pixel transistor disposed near an intersection of the signal line and the scanning line; and a signal line driving circuit electrically connected to the signal line, wherein the pixel transistor has the first channel region. The signal line driving circuit has the second channel region, the first channel region includes at least one grain boundary, and the second channel region does not substantially include a grain boundary.

According to the present invention, since a region which does not include a grain boundary in the channel region is selectively formed, a polycrystalline semiconductor device which can attain a sufficient operation speed without significantly impairing productivity. Is provided.

Hereinafter, the present invention will be described in detail with reference to specific examples, but the present invention is not limited to the following examples.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a communication apparatus according to an embodiment of the present invention.

As shown in FIG. 1, this portable video receiver 1
Is mainly for receiving a signal in the 50 GHz band and displaying the signal on the display unit 101 based on the signal. The display unit 101 has an effective display area V with a diagonal size of 4 inches in the VGA specification.

The display section 101 includes an effective display area V, and signal lines and scanning line driving circuits 25 and 31 arranged around the effective display area V.

As shown in FIG. 2, the display unit 101 includes an array substrate 51, a counter substrate 71, an array substrate 51 and a counter substrate.
The liquid crystal display includes a liquid crystal layer 81 made of twisted nematic liquid crystal sandwiched between the liquid crystal layer 71 and polarizing plates 91 and 93 disposed on outer surfaces of the array substrate 51 and the counter substrate 71, respectively. In this embodiment, the display unit 101 is formed of a liquid crystal display element including a liquid crystal layer as a light modulation layer. However, a self light emitting layer such as an EL layer may be used as the light modulation layer, other than the liquid crystal layer. Further, here, the display unit 101 is of a light transmission type, but may be a reflection type.

The array substrate 51 includes a silicon oxide film 12 and a silicon nitride film 13 as undercoat layers on an insulating substrate 10 made of glass, and an island-shaped polycrystalline silicon film 15 is disposed thereon.

Each polycrystalline silicon film 15 has a channel region 15
c, including source and drain regions 15s and 15d arranged with the channel region 15c interposed therebetween. On the channel region 15c, a gate electrode 19 is arranged via a gate insulating film 17, and this gate electrode 19 extends from the scanning line 21 connected to the scanning line driving circuit 31 as shown in FIG. .

On the gate electrode 19, a silicon nitride film is disposed as an interlayer insulating film 23, and the drain region 15d is connected to a signal line driving circuit through a through hole formed in the interlayer insulating film 23 as shown in FIG. It is electrically connected to a signal line 27 connected to 25 via a drain electrode 29.

The source region 15s is connected to a source electrode 33 via a through hole formed in the interlayer insulating film 23.

A color filter layer 35 also serving as a flattening layer is disposed thereon, and a transparent conductive film such as ITO electrically connected to the source electrode 33 through a through hole formed in the color filter layer 35. Is disposed. Then, the alignment film 55 is disposed thereon to form the array substrate 51.

That is, as shown in FIG. 1, the array substrate 51 has a pixel electrode 41 via a pixel TFT 41 disposed near an intersection of the signal line 27 and the scanning line 21 arranged in a matrix in plan view. 37 are located. This pixel TFT 41 is
It has a W / L of 9 / 4.5 μm and includes about 50 crystal grain boundaries inside the channel region.

The opposing substrate 71 is an insulating substrate made of glass.
A counter electrode 61 made of a transparent conductive film such as ITO, and an alignment film 75 are arranged on 60.

The array substrate 51 and the opposing substrate
71 are arranged to face each other with an interval of about 5 μm by a sealing material 95, and a liquid crystal layer 81 is arranged between them.

Next, the scanning line driving circuit 31 and the signal line driving circuit 25 will be described. The scanning line drive circuit 31 is 31.5 KHz
The flip-flop circuit operates based on the vertical clock signal CKV of the control circuit 121. Although not shown, a plurality of flip-flops are connected in cascade, and a vertical start signal S
TV is sequentially transferred based on the vertical clock signal CKV, and a gate signal is output based on this.

As shown in FIG. 3, the signal line drive circuit 25 sends the horizontal start signal STH from the control circuit 121 to 32 MHz.
A shift register SR that sequentially transfers based on the horizontal clock signal CKH, and an analog video signal Vi that is transferred via a video bus VB based on the output of each stage of the shift register SR.
and sampling TFTAST for sequentially sampling deo. These drive circuits 25 and 31 are integrally formed on the insulating substrate 10 by a polycrystalline silicon film similarly to the pixel TFT 41.

The display section 101 is provided on the insulating substrate 1.
Control circuit 121 and power supply circuit 111 integrally formed on
Is controlled by

Although not shown, the control circuit 121 operates based on a 32 MHz clock signal CKREF, and includes a digital-to-analog conversion circuit (DAC) for performing digital-to-analog conversion of an input digital video signal Data. And various control signals such as the horizontal clock signal CKH based on the input synchronization signal Sync.
The control circuit 121 is integrally formed on the insulating substrate 10 by a polycrystalline silicon film, like the pixel TFT 41. TF constituting the control circuit 121 and the drive circuits 25 and 31
Each T is configured so as not to substantially include a crystal grain boundary in the channel region, and details will be described in the description of the manufacturing process.

The power supply circuit 111 is connected to the insulating substrate 1 described above.
In this embodiment, components such as coils are mounted on this embodiment.

As described above, the display unit 101 and the power supply circuit 1
The low-frequency circuit section of the portable video receiver 1 such as 11 and the control circuit 121 is configured.

In this specification, the high-frequency circuit section is 1 to 9
It processes signals in the 0 GHz frequency band. In this embodiment, it processes signals in the 50 GHz band as described above.

As shown in FIG. 1, the high-frequency circuit section includes an antenna 201 for receiving a signal, a transmission line 211 for transmitting a signal received by the antenna 201, an oscillator 221 for outputting a local oscillation signal Lo, and an antenna 201. A coupler 231 for combining the obtained radio signal and the local oscillation signal Lo, a mixer 241 for converting an output signal of the coupler 231 into an intermediate frequency signal, an intermediate frequency amplifier 251 for amplifying a signal from the mixer 241, and a signal processing circuit 261. Including. The mixer 241 has an R (not shown).
It is connected to the ground 271 via the F choke, and an unnecessary mode is removed by the LSM mode suppressor 281 to make the circuit asymmetric in the vertical direction. The signal from the oscillator 221 is terminated by a non-reflection termination 291.

This will be described in more detail. As the transmission path 211, a transmission path based on an NRD guide is used. As the transmission line 211, besides this, a microstrip line,
Coplanar lines, triplate lines and the like can also be used.

The NRD guide generally holds a dielectric line made of a high-dielectric material by two metal flat plates, and a portion other than the dielectric line between the metal flat plates is made of a low dielectric material such as air. In such a configuration, since the wavelength in the dielectric line is shorter than the wavelength in the air, the distance between the metal plates corresponds to less than half the wavelength in air and more than half the wavelength in the dielectric line. The wave propagates only in the dielectric line.

The reason for using the NRD guide is that there is almost no leakage of electromagnetic waves to the surroundings, and the use of a dielectric material having a small dielectric loss enables low-loss electric transmission and facilitates miniaturization. by.

In this embodiment, as shown in FIG. 1B, the width L1 and the thickness t of the dielectric line 213 constituting the transmission line
Was set to 1 mm. The dielectric line 213 is made of a silicon nitride film having a relative dielectric constant ε _r2 of 6,
The dielectric constant as a low dielectric material 215 disposed adjacent to the 3 epsilon _r1
Was composed of the silicon oxide film of No. 3.

The dielectric line 213 is configured based on the following equation.

T = C / (fc · ε _r2 ), t / 2 ≦ L1 ≦ t (C: light flux, fc: cut-off frequency)
In this embodiment, about 1 mm is formed on the insulating substrate 10 in order to form the
Is formed. And this dielectric line 21
3 is sandwiched between a first metal flat plate 217 formed on the insulating substrate 10 and a second metal flat plate 219 formed on the insulating substrate 60. The first and second metal flat plates 217 and 219 It is electrically connected on the circuit section side, thereby preventing the electromagnetic wave from affecting the low-frequency circuit section side. Note that components such as the oscillator are mounted at predetermined positions before being held by the second metal flat plate 219.

The intermediate frequency amplifier 251 and the signal processing circuit 2
61 is constituted by a triplate line. As shown in FIG. 4, the triplate line includes a conductor layer 311 formed on the insulating substrate 10, an insulation layer 313 on the conductor layer 311,
Further, a conductor layer 315 is provided on the insulating layer 313. On the conductor layer 315, an insulating layer (not shown) for adjusting a gap between the insulating layer 60 and the insulating substrate 60 is disposed. Here, as the insulating layer 313,
An oxide film having a relative dielectric constant ε _r3 of 4 and a film thickness of 20 μm was used, and the conductor layer 315 was configured with a 6 μm width. Thereby, the characteristic impedance was 50Ω.

As the intermediate frequency amplifier 251 and the TFT and the diode constituting the signal processing circuit 261, the one integrally formed on the insulating substrate 10 by the same process as the TFT constituting the control circuit 121 and the like. Each of them is configured so as not to substantially include a crystal grain boundary in the channel region. Note that, also in the intermediate frequency circuit, components such as inductance are mounted as components on the substrate in this embodiment.

As described above, in the portable video receiver 1 of this embodiment, the driving circuits 25 and 31, the control circuit 121, and a part of the high-frequency circuit are formed integrally on the insulating substrate 10. , Height 60mm, width 120mm, thickness 5mm
The size could be reduced to one.

In particular, since the transmission path 211 of the high-frequency circuit is also formed integrally on the insulating substrate 10 by providing a step on the insulating substrate 10, the miniaturization can be promoted.

Next, a method for manufacturing the portable video receiver 1 of this embodiment will be described with reference to the drawings.

First, as shown in FIG. 5A, a molybdenum (Mo) film is deposited on an insulating substrate 10 made of glass, and is patterned to form an alignment mark 14. Thereafter, each step is processed with reference to the alignment mark 14.

As shown in FIG. 1B, a silicon oxide film 11 and a silicon nitride film 12 are sequentially deposited as an undercoat layer on the glass substrate 10 by a plasma CVD method. A film 13 is deposited. still,
The amorphous silicon film 13 is deposited to a thickness of 50 nm in order to suppress an undesired leak current.

Thereafter, as shown in FIG. 3C, the amorphous silicon film 13 is subjected to a dehydrogenation treatment to prevent ablation, and is irradiated with an excimer laser to grow a crystal on the polycrystalline silicon film 15. Let it.

Here, in the region corresponding to the pixel TFT 41 of the display section 101, the amorphous silicon film 13 is crystallized into the polycrystalline silicon film 15 by performing stepwise scanning with a long excimer laser beam. As a result, the polycrystalline silicon film 15 in the region corresponding to the pixel TFT 41 of the display unit 101 has an average particle diameter of 0.
It is about 3 μm. On the other hand, the other regions, that is, the low-frequency circuit portion and the high-frequency circuit portion such as the signal line driving circuit 25, the scanning line driving circuit 31, and the control circuit 121 use a mask having a chevron-type light-blocking portion, and The crystalline silicon film 13 is irradiated with excimer laser light. At this time, since the crystal grows with the shadow portion at the tip of the chevron as a nucleus, the lateral growth was promoted by moving the substrate at a pitch of 0.5 μm. here,
By controlling the tip of the chevron based on the alignment mark 14, a particle size of about 10 μm was obtained at a desired position.

The polycrystalline silicon film 15 thus formed is patterned into a predetermined island shape as shown in FIG. 4D, and TEOS is formed thereon as a gate insulating film 17 by a plasma CVD method. Film.

Further, as shown in FIG. 3E, a molybdenum-tungsten (MoW) alloy film functioning as the gate electrode 19 is deposited thereon by sputtering and patterned into a predetermined shape. And this gate electrode 19
Is used as a mask, and as impurity ions, for example, phosphorus (P)
Is ion-doped and heat-treated to activate the impurities. As a result, the source region 15s and the drain region 1
5d, and a channel region 15c sandwiched between the source and drain regions 15s, 15d is formed. Here, the channel region is an intrinsic semiconductor for the sake of simplicity, but it is effective to dope impurities such as boron (B) at a low concentration before crystallization for threshold control.

Next, as shown in FIG.
A silicon nitride film is deposited as an interlayer insulating film 23 on 10, and through holes are formed at locations corresponding to the source and drain regions 15s and 15d. Then, an aluminum-neodymium (AlNd) alloy film is deposited and patterned to form source and drain electrodes 29 and 33. In this manner, the n-type pixel TFT 41 and the TFT of the drive circuit unit 121 are configured. Although not described in detail here, a p-type TFT constituting a drive circuit portion is simultaneously manufactured by selectively disposing a resist mask and performing ion doping.

Then, as shown in FIG. 3G, a photosensitive color resist is applied in a thickness of 3 μm, and exposure and development are repeated to include red, blue and green color layers, In addition, a color filter layer 35 also serving as interlayer insulation is selectively formed on the pixel TFT. During the development process, the source electrode
A through hole is formed in the color filter layer 35 in a region corresponding to 29. An ITO film is deposited thereon by sputtering and patterned into a desired shape to form a pixel electrode 37 electrically connected to the source electrode 29.

As described above, the pixel TFT 41 of this embodiment is formed by a normal ELA from a polycrystalline silicon semiconductor film having a crystal grain size with no problem in its operation. On the other hand, TFTs in other areas
Since a polycrystalline silicon film crystallized by ELA using a mask aligned with the alignment mark 14 so as not to form a grain boundary in the channel region of the TFT is used, various drive circuits are mounted on the same substrate. It can be formed integrally. Moreover, ELA using this mask is
Since the processing is performed only on the peripheral area excluding the effective display area V, the productivity is not significantly impaired.

Further, the peripheral area is patterned based on, for example, about 0.8-fold reduction exposure, so that the effective display area V
Is patterned on the basis of magnified exposure of 1 × or more, for example, about 1.2 times. Is also maintained. As described above, in order to make the exposure magnification different for each region, in this embodiment, dry etching is used for patterning, thereby reducing the dependence of pattern accuracy on the wiring rule.

In the above-described embodiment, the amorphous silicon semiconductor film is patterned after crystallization, but may be crystallized after being patterned in advance. In crystallization, besides ELA, crystallization by other energy irradiation such as lamp annealing may be used. In addition, a catalyst can be applied on the amorphous silicon semiconductor film to control the crystal nucleus formation position and further increase the particle diameter.

[0054]

According to the communication apparatus of the present invention, it is possible to achieve a sufficient operation speed without significantly reducing productivity.

[Brief description of the drawings]

FIGS. 1A and 1B relate to a portable video receiver according to an embodiment of the present invention, wherein FIG. 1A is a schematic configuration diagram, and FIG. 1B is a schematic cross-sectional view taken along line AA ′.

FIG. 2 is a schematic sectional view of a display unit of FIG.

FIG. 3 is a schematic configuration diagram of a signal line driving circuit.

FIG. 4 is a diagram illustrating a configuration of the triplate line of FIG. 1;

FIG. 5 is a diagram illustrating a manufacturing process of the portable video receiver according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Portable video receiver 12 Silicon oxide film 13 Silicon nitride film 15 Polycrystalline silicon film 17 Gate insulating film 19 Gate electrode 21 Scan line 23 Interlayer insulating film 25 Signal line drive circuit 29 Drain electrode 31 Scan line drive circuit 33 Source electrode 41 Pixel TFT 51 Array substrate 71, 81 Liquid crystal layer 91, 93 Polarizer 101 Display unit 121 Control circuit 251 Intermediate frequency amplifier 261 Signal processing circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 G02F 1/136 500 5F110 H04N 5/66 101 H01L 29/78 612B 627G F term (Reference) 2H088 EA03 HA08 2H092 GA59 HA28 KA04 KA10 KA12 KA19 KB25 MA05 MA08 MA27 MA30 PA01 PA08 PA13 QA07 5C058 AA06 AB01 AB06 BA01 BA35 5C094 AA13 AA15 AA21 AA43 BA03 BA43 CA19 DA09 DA13 DB01 DB04 DB10 EA04 FB10 FA10 FB04 CA04 DA02 DB03 FA02 JA01 5F110 BB02 CC02 DD02 DD13 DD14 DD17 DD30 EE06 EE44 FF02 FF30 GG02 GG13 GG16 GG25 GG28 GG29 GG32 GG45 HJ01 HJ12 HJ13 HJ23 HL06 NN02 NN24 NN33 NN78 PP02 Q03 Q05

Claims (5)

[Claims] An insulating substrate; a polycrystalline semiconductor film formed on the insulating substrate; first and second channel regions formed in the polycrystalline semiconductor film; A transmission / reception circuit arranged, wherein the plurality of signal lines and scanning lines are arranged in a matrix on the insulating substrate, and are arranged near intersections of the signal lines and scanning lines. A pixel transistor; and a signal line driving circuit electrically connected to the signal line. The pixel transistor includes the first channel region, and the signal line driving circuit includes a second channel region. The communication device according to claim 1, wherein the first channel region includes at least one grain boundary, and the second channel region does not substantially include a grain boundary. 2. The communication device according to claim 1, wherein the transmission line of the transmission / reception circuit is formed integrally on the insulating substrate. 3. The transmission line includes a first metal plate disposed on the insulating substrate, a second metal plate facing the first metal plate, and a transmission line disposed between the first and second metal plates. 3. The communication according to claim 2, further comprising: a dielectric line having a first relative dielectric constant, and a dielectric layer disposed adjacent to the dielectric line and smaller than the first relative dielectric constant. apparatus. 4. The communication device according to claim 2, wherein the insulating substrate has a concave portion, and the transmission path is disposed in the concave portion. 5. The communication apparatus according to claim 4, wherein said transmission path transmits a signal in a frequency band of 1 to 90 GHz.