JP2001144291A - Horizontal-type field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decreases resistance by enlarging as much as possible the width of a lower-layer wiring, connected to a source region. SOLUTION: A through-hole for connecting an upper-layer wiring to a lower- layer wiring is provided above the side of a contact hole for connecting the lower-layer wiring to the drain region of a low on-resistance horizontal-type FET, where a source region and drain region are alternately provided. Here, the connection hole for connecting the drain region and the through-hole are formed, in a line, in the longitudinal direction of the drain region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral field effect transistor used for, for example, a small motor driving LSI.

[0002]

2. Description of the Related Art A lateral field effect transistor (hereinafter referred to as FET) in which a source region and a drain region are arranged on lattice points and a gate electrode is provided so as to surround the source region and the drain region,
For example, IEEE 1922 CUSTOM IC CONFERENCE, 25.7.1-25.
It is known as a low on-resistance power MOSFET as announced by SAKAMOTO et al. In 7.4. FIG.
(a) and (b) show an nMOSFET, and BB of FIG.
As shown in FIG. 2B, which is a sectional view taken along the line, a P base region 21 and an N ⁻ drain region 22 formed in the surface layer of the N-type substrate 1 are formed.
N ⁺ source region 23 and N ⁺ drain region 24
Are formed. The gate electrode 3 is connected to each N ⁺ source region.
On a surface between 23 and the N ⁻ drain region 24, a net-like planar shape is formed via a gate oxide film 41. The lower layer Al is formed by a contact hole 61 formed in the insulating film 42 covering the gate electrode 3.
The wiring 51 contacts the N ⁺ source region 23, and the lower
Al wiring 52 is in contact with N ⁺ drain region 24. The source side wiring 51 extends over the insulating film 42 and is a perspective plan view of FIG.
As shown in (a), the wiring extends over the entire surface except for the drain-side wiring 52 and the gap 7. An interlayer insulating film covering the lower Al wiring 51
The upper layer Al wiring is formed in the through hole 63 formed just above the contact hole 62 in 43.
53 is in contact with the lower layer Al wiring 52. As shown in FIG. 2A, the source and the drain are alternately formed on the lattice points. FIG. 3 is an enlarged view of the portion X in FIG. 2, and the surface is covered with a passivation film 44.

In the pMOSFET structure shown in FIGS. 4A and 4B, an N ⁺ source region 25 is directly
⁺ Drain region 26 is formed via P ^- drain region 27. In this case, the through hole 63 for the drain-side upper layer Al wiring 53 is formed in a laterally upper direction of the contact hole 62.

[0004]

In the structure shown in FIGS. 2 and 3, since the upper wiring 53 is in contact with the lower wiring 52 in the through hole 63 immediately above the contact hole 62, the width of the lower metal wiring 51 is reduced. There is an advantage that the area can be taken without waste and the resistance of the lower metal wiring 51 can be reduced. However, when the contact hole 62 is formed, the shape of the lower metal wiring 52 entering the contact hole 62 is distorted as shown in FIG. The insulating film formed thereafter remains without being etched when the through-hole 63 is formed, and there is a risk that the through-hole resistance is greatly increased. Also, even if etched, the depth of the through-hole 63 becomes deeper than usual, making it difficult for the upper-layer metal wiring 53 to penetrate, greatly increasing the through-hole resistance, and in the worst case, the upper-layer metal wiring 53 on the drain side. And the lower metal wiring 52 do not contact at all, and there is a possibility that a device is not formed.

In the structure shown in FIG. 4, the through hole 63 is formed on the side of the contact hole 62, but is formed in the source / drain direction. In this case, the width d of the lower wiring 51 becomes smaller. Thereby, the lower layer wiring resistance increases. Further, when a large current is applied, the current density is increased when compared with the same device size, and migration is easily caused. As a countermeasure, the device width in the current direction must be increased, and the degree of freedom in device layout is reduced.
Also, even if the device cycle in the semiconductor substrate, that is, the miniaturization of the distance between the source and the drain is advanced, the through hole
Since 63 is in the source / drain direction, the lower metal wiring,
The device cycle is determined by the design rule of the contact hole and the through hole. Further, among the patterns of the lower layer wiring 51, the width d is most affected with respect to the width, but it goes without saying that the width d is reduced in other directions.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to secure the width and area of a lower-layer wiring connected to a source region of a source region and a drain region alternately formed on a surface layer of a semiconductor substrate. Accordingly, it is an object of the present invention to provide a low-on-resistance lateral FET capable of reducing the lower-layer wiring resistance, improving the degree of freedom in device layout, and making the device cycle finer.

[0007]

In order to achieve the above object, the present invention is directed to a lateral field effect transistor formed on a semiconductor substrate, wherein a plurality of source regions are formed alternately in a strip shape in which the longitudinal direction is parallel to each other. And the plurality of drain regions,
The lower wirings are connected to each other by lower wirings connected through connection holes formed in an insulating film covering the source region and the drain region, and the lower wirings are formed through through holes formed in an interlayer insulating film on the lower wirings. In the lateral field-effect transistor connecting any one of the above and the upper layer wiring, the source region and the drain region are alternately arranged in parallel with each other so that the through hole and the connection hole of the lower layer wiring to which the through hole is connected are parallel to each other. It is effective to form an angle with respect to the direction in which the source region or the drain region is arranged on a straight line in the longitudinal direction of the source region or the drain region.

It is also effective that the lower wiring not connected to the through hole is formed so as to cover the lower wiring to which the through hole is connected and a portion excluding a region surrounding the lower wiring at a predetermined interval. .

[0009]

The lower wiring connected to the source region by not making the direction connecting the through hole of the interlayer insulating film for connection to the drain region and the connection hole coincide with the direction connecting the contact holes to both the source and drain regions. In the drain region side is reduced, and the device period can be miniaturized without increasing the resistance of the lower wiring. As a result, the device area can be reduced, and the on-resistance can be made lower than the increase in the number of integrated devices or the decrease in the lower layer wiring resistance. Further, the degree of freedom in device layout is improved by reducing the risk of electromigration.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings in which parts common to those in FIGS. 1A and 1B show a lateral DMOS structure according to an embodiment of the present invention. As shown in FIG. 1B, which is a cross-sectional view taken along line AA of FIG. 3 N through the N buried layer 12
An N-type epitaxial layer 1 having a thickness of about 4 cm and a thickness of about 4 cm is formed. By ion implantation from the surface of the N layer 1, a P base region 21 having a surface concentration of about 10 ¹⁷ / cm ³ , an N ⁺ source region 23 therein, an N drain region 22 having a surface concentration of about 10 ¹⁷ / cm ³ , An N ⁺ drain region 24 is formed in that region. The surface between the source region 23 and the N drain region 22 is covered with a gate oxide film 41 having a thickness of several hundreds of 、, and a polycrystalline silicon layer having a thickness of several thousand か け て over the field oxide film 45. Is provided and a gate electrode 3 is formed by patterning. Insulating film covering gate electrode 3
A source-side lower Al wiring 51 that short-circuits the N ⁺ source region 23 and the P base region 21 in a contact hole 61 opened in 42, and a drain-side lower Al contacting the N ⁺ drain region 24 in a similar contact hole 62. The wiring 52 is formed.

The source region 23 and the drain region 24 are formed in a parallel band shape, and a contact hole 61 is provided with a P for short-circuiting the N source region 23 to the P base region as known in Japanese Patent Application Laid-Open No. 2-154469. ⁺ Contact region 25 is exposed. Above the drain region 24, the contact hole 62 and the interlayer insulating film through hole 63
Are formed linearly, but the contact hole to the source region 23 is formed.
It is at 90 ° to 61.

The device cycle of this LSI is 7.9 μm.
m, source and drain contact holes 61, 62, through hole 63, lower layer
As shown in FIG. 1A which is a perspective plan view of only the Al wirings 51 and 52, the source and the drain are alternately formed.
The area of the drain contact hole 62 is 1.
2 μm × 1.2 μm, and the source contact
Similarly, at the interval of 1.2μm at an angle of 90 ° from the direction in which the drains are lined up, the minimum design rule value of 1.2μm × 1.2μm
The through hole 63 of the interlayer insulating film 43 having the area of?

As a result, the width of the lower Al wiring 51 can be doubled. As a result, the resistance of the lower wiring 51 becomes 50
%, And a reduction in on-resistance was promoted. Also, since the device width required for migration measures is reduced by 50%, the degree of freedom in device layout is increased. It is apparent that the effects of the present invention can be similarly obtained even if the drain region and the source region in the above description and drawings are exchanged.

[0014]

According to the present invention, a through hole formed between an interlayer insulating film formed by removing a contact hole just above a contact hole for connection with a drain region of a lower wiring, and a contact hole contacting a source region with respect to the contact hole. Are formed in a direction different from the direction connecting the source and drain, the restriction of the spread between the source and the drain of the lower wiring connected to the source region is reduced, and the width or area of the lower wiring can be increased. As a result, the device area can be reduced or the width of the lower wiring connected to the source region can be increased, so that the on-resistance can be further reduced. Further, the degree of freedom in device layout is improved, which is advantageous for miniaturization.

[Brief description of the drawings]

FIGS. 1A and 1B show a lateral FET according to an embodiment of the present invention, wherein FIG. 1A is a plan view excluding an upper structure, and FIG. 1B is a cross-sectional view taken along line AA of FIG.

2A and 2B show an example of a conventional lateral FET, wherein FIG. 2A is a plan view excluding an upper structure, and FIG. 2B is a sectional view taken along line BB of FIG.

FIG. 3 is an enlarged view of a part X in FIG. 2;

4A and 4B show another example of a conventional lateral FET, wherein FIG. 4A is a plan view excluding an upper structure, and FIG. 4B is a cross-sectional view taken along line CC of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N layer 21 P base region 22 N drain region 23 N ⁺ source region 24 N ⁺ drain region 3 Gate electrode 41 Gate oxide film 42 Insulating film 43 Interlayer insulating film 51 Source side lower layer wiring 52 Drain side lower layer wiring 53 Upper layer wiring 61, 62 Contact hole 63 Through hole 7 Gap

Claims (2)

[Claims] 1. A lateral field effect transistor formed on a semiconductor substrate covers a plurality of source regions and a plurality of drain regions alternately formed in a band shape in which the longitudinal direction is parallel to each other, and covers the source region and the drain region. Each of the lower wirings is connected to each other by a lower wiring connected through a connection hole formed in the insulating film, and one of the lower wirings and the upper wiring are connected through a through hole formed in the interlayer insulating film on each lower wiring. Wherein the through-hole and the connection hole of the lower wiring to which the through-hole is connected are formed at an angle with respect to a direction in which the source region and the drain region are arranged in parallel and alternately with each other. A lateral field-effect transistor formed so as to be aligned on a straight line in a longitudinal direction of the source region or the drain region. 2. The lateral field-effect transistor according to claim 1, wherein the lower wiring on the side not connected to the through-hole is:
A lateral field effect transistor formed so as to cover a lower layer wiring to which the through hole is connected and a portion excluding a region surrounding the lower layer wiring at a predetermined interval.