JP2001144216A - Semiconductor device and method of manufacture, circuit board and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having wiring not to be broken easily and a method of manufacture, a circuit board and an electronic apparatus. SOLUTION: The semiconductor device comprises a semiconductor chip 10 having an electrode 12, an insulation layer 20 provided with a through hole 22, a conductive layer 30 formed on the electrode 12 in the through hole 22, and a wiring layer 40 formed on the insulation layer 20 while passing above the conductive layer 30 wherein the level difference between the upper surface of the conductive layer 30 and the upper surface of the insulation layer 20 is equal to or less than the thickness of the wiring laver 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.

[0002]

BACKGROUND OF THE INVENTION A resin layer is formed on the surface of a semiconductor chip,
A semiconductor device having a structure in which a wiring is formed thereon and a solder ball is provided at a position shifted from the Al pad has been developed. Such a semiconductor device is a CSP (Chip Scale / Siz
e Package).

[0003] In this structure, the wiring is formed so as to extend from above the Al pad to above the resin layer through a through hole formed in the resin layer. Therefore, the wiring is easily broken at the corner of the opening end of the through hole, and improvement is required.

An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device whose wiring is hard to be disconnected, a method of manufacturing the same, a circuit board, and an electronic device.

[0005]

(1) In a semiconductor device according to the present invention, a semiconductor element having an electrode is electrically connected to the electrode provided on a surface of the semiconductor element on which the electrode is formed. A conductive layer formed thereon, an insulating layer formed around the conductive layer, and a wiring layer electrically connected to the conductive layer and formed on the insulating layer,
The upper surface of the conductive layer is formed between the upper surface of the insulating layer and a position higher than the upper surface of the insulating layer by the thickness of the wiring layer.

According to the present invention, the step between the upper surface of the conductive layer and the upper surface of the insulating layer is smaller than the thickness of the wiring layer. Therefore, disconnection of the wiring layer due to the corner of the opening end of the through hole is less likely to occur.

In the present invention, the semiconductor element is
This includes not only semiconductor chips but also individual elements of a semiconductor wafer before dicing.

(2) A semiconductor device according to the present invention includes a semiconductor element having an electrode and a conductive layer provided on a surface of the semiconductor element on which the electrode is formed and electrically connected to the electrode. , An insulating layer formed around the conductive layer, and a wiring layer electrically connected to the conductive layer and formed on the insulating layer, the upper surface of the conductive layer , Between the upper surface of the insulating layer and a position lower than the upper surface of the insulating layer by the thickness of the wiring layer.

According to the present invention, the step between the upper surface of the conductive layer and the upper surface of the insulating layer is smaller than the thickness of the wiring layer. Therefore, disconnection of the wiring layer due to the corner of the opening end of the through hole is less likely to occur.

In the present invention, the semiconductor element is
This includes not only semiconductor chips but also individual elements of a semiconductor wafer before dicing.

(3) In this semiconductor device, the wiring layer is formed with a thickness of about 5 μm, and a difference in height between the upper surface of the conductive layer and the upper surface of the insulating layer is within about 5 μm. Is also good.

(4) In this semiconductor device, a plurality of external terminals may be provided on the wiring layer at positions avoiding the conductive layer.

By providing the external terminal at such a position, the stress applied to the external terminal is less likely to be transmitted to the joint between the conductive layer and the electrode. As a result, the bonding portion is not easily broken, and the reliability of the electrical connection is improved.

(5) In this semiconductor device, a protective layer may be provided on the insulating layer and around the external terminal.

(6) In this semiconductor device, the insulating layer may have a stress relaxation function.

By doing so, the insulating layer absorbs the stress, and the stress transmitted to the joint between the conductive layer and the electrode can be reduced, and the reliability of the electrical connection is improved.

(7) A circuit board according to the present invention has the above-described semiconductor device mounted thereon.

(8) An electronic apparatus according to the present invention includes the above-described semiconductor device.

(9) In the method of manufacturing a semiconductor device according to the present invention, a conductive layer electrically connected to the electrode and a conductive layer formed around the conductive layer may be formed on the surface of the semiconductor element on which the electrode is formed. And a second step of electrically connecting to the conductive layer to form a wiring layer formed on the insulating layer, the upper surface of the conductive layer being provided. Is formed between the upper surface of the insulating layer and a position higher than the upper surface of the insulating layer by the thickness of the wiring layer.

According to the present invention, the step between the upper surface of the conductive layer and the upper surface of the insulating layer is set to be equal to or less than the thickness of the wiring layer. Therefore, disconnection of the wiring layer due to the corner of the opening end of the through hole is less likely to occur.

In the present invention, the semiconductor element is
This includes not only semiconductor chips but also individual elements of a semiconductor wafer before dicing.

(10) In the method of manufacturing a semiconductor device according to the present invention, a conductive layer electrically connected to the electrode and a conductive layer formed around the conductive layer are formed on the surface of the semiconductor element on which the electrode is formed. And a second step of electrically connecting to the conductive layer to form a wiring layer formed on the insulating layer, the upper surface of the conductive layer being provided. Is formed between the upper surface of the insulating layer and a position lower than the upper surface of the insulating layer by the thickness of the wiring layer.

According to the present invention, the step between the upper surface of the conductive layer and the upper surface of the insulating layer is set to be equal to or less than the thickness of the wiring layer. Therefore, disconnection of the wiring layer due to the corner of the opening end of the through hole is less likely to occur.

In the present invention, the semiconductor element is
This includes not only semiconductor chips but also individual elements of a semiconductor wafer before dicing.

(11) In this method of manufacturing a semiconductor device, in the first step, after forming the insulating layer over the electrode, the through hole is formed in the electrode, and then the conductive layer is formed. May be provided.

(12) In this method of manufacturing a semiconductor device, in the first step, after forming the conductive layer on the electrode and forming the insulating layer so as to cover the conductive layer, a part of the insulating layer is formed. May be removed to expose a part of the conductive layer.

According to this, since there is no step of forming a through hole, the process can be shortened. (13) In this method of manufacturing a semiconductor device, a part of the insulating layer may be removed by ashing. .

(14) In this method of manufacturing a semiconductor device, the wiring layer is formed with a thickness of about 5 μm, and a difference in height between the upper surface of the conductive layer and the upper surface of the insulating layer is reduced by about 5 μm.
m.

(15) The method for manufacturing a semiconductor device may further include a step of providing a plurality of external terminals on the wiring layer at positions avoiding the conductive layer.

By providing the external terminal at such a position, the stress applied to the external terminal is less likely to be transmitted to the joint between the conductive layer and the electrode. As a result, the bonding portion is not easily broken, and the reliability of the electrical connection is improved.

(16) The method of manufacturing a semiconductor device may further include a step of providing a protective layer on the insulating layer and around the external terminals.

(17) In this method of manufacturing a semiconductor device, the insulating layer may be formed of a material having a stress relaxation function.

[0033] This allows the insulating layer to absorb the stress, reduce the stress transmitted to the joint between the conductive layer and the electrode, and improve the reliability of the electrical connection.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to the following embodiments. The present invention relates to a CSP (Chip Size / Scale Pac) which is one mode of a semiconductor device.
kage).

(First Embodiment) FIGS. 1A to 3
(C) is a diagram illustrating the method for manufacturing the semiconductor device according to the present embodiment. In the present embodiment, a first step of forming the insulating layer 20 and the conductive layer 30 on the semiconductor chip 10 and a second step of forming the wiring layer 40 are performed.

(First Step) As shown in FIG. 1A, the semiconductor chip 10 has a plurality of electrodes (or pads) 12. The electrodes 12 may be arranged at the end of the semiconductor chip 10 or at the center of the semiconductor chip 10.
Further, the electrodes 12 may be arranged along two parallel edges when the semiconductor chip 10 forms a rectangle, or may be arranged along four edges. Each electrode 12 is connected to the semiconductor chip 1
Although it is often formed to be thin and flat at 0, the shape of the side surface or vertical cross section is not limited, and may be flush with the surface of the semiconductor chip 10. The electrode 12 is formed of, for example, aluminum. Also, the planar shape of the electrode 12 is not particularly limited, and may be circular or rectangular. Electrode 1
The passivation film 14 is often formed on the semiconductor chip 10 avoiding a part of the passivation film 2. The passivation film 14 is an insulating layer. Passivation film 14
Can be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like.

An insulating layer 20 is provided on the surface of the semiconductor chip 10 having the electrodes 12. The insulating layer 20
It has an insulating property with respect to the wiring layer 40. The insulating layer 20
It is preferable to protect the semiconductor chip 10 and also have heat resistance when melting the solder at the time of mounting. Insulating layer 20
Preferably, when the semiconductor device is mounted on a circuit board, the Young's modulus is low enough to reduce stress caused by a difference in thermal expansion coefficient between the semiconductor chip and the mounted circuit board. For that purpose, the insulating layer 20 may be formed of, for example, a polyimide resin. In addition, the thickness of the insulating layer 20 can be freely determined as needed.

The insulating layer 20 has a through hole 22 for exposing at least a part of each electrode 12 of the semiconductor chip 10.
Having. Therefore, the through holes 22 are formed on the electrodes 12 and may be formed according to the total number of the electrodes 12. FIG.
As shown in (A), the through hole 22 may be tapered, and the through hole 22 may be formed on an inner wall surface perpendicular to the semiconductor chip 10.

The through hole 22 covers the electrode 12 and covers the insulating layer 2.
0 may be formed and photolithography may be applied. That is, the photosensitive insulating layer 2 is exposed through a mask.
The through-hole 22 may be formed by irradiating energy to zero and developing. At this time, the insulating layer 20 may be a positive type or a negative type resist. Alternatively, the non-photosensitive insulating layer 20 may be etched to form the through hole 22.

Alternatively, after forming the conductive layer 30 on the electrode 12, the through hole 22 may be formed by forming the insulating layer 20 on the semiconductor chip 10 and around the conductive layer 30.

In the first step, as shown in FIG.
The conductive layer 30 is provided in the through hole 22. The conductive layer 30 may be a single layer or a plurality of layers. FIG.
In the example shown in (B), the conductive layer 30 is formed by a first layer (lower layer) formed on the electrode 12 and a second layer (upper layer or surface layer) laminated thereon. The first layer is made of, for example, nickel, and the second layer is made of, for example, gold.
Alternatively, the conductive layer 30 may be composed of a single layer made of only nickel.

In the present embodiment, the upper surface of the conductive layer 30 is
From the upper surface of the insulating layer 20, the wiring layer 40 (see FIG. 3C)
Is formed at a height equal to or higher than the position lowered by the thickness of. Further, the upper surface of the conductive layer 30 is moved from the upper surface of the insulating layer 20 to the wiring layer 40.
(See FIG. 3 (C)). That is, the difference in height between the upper surface of the insulating layer 20 and the upper surface of the conductive layer 30 is set within the range of the thickness of the wiring layer 40. For example, in the example shown in FIG. 1B, the upper surface of the conductive layer 30 is formed between the upper surface of the insulating layer 20 and a position higher than the upper surface of the insulating layer 20 by the thickness of the wiring layer 40. . By doing so, the step formed between the insulating layer 20 and the conductive layer 30 is within the range of the thickness of the wiring layer 40, so that the wiring layer 40 is less likely to be disconnected.

More specifically, the upper surface of the conductive layer 30 is
When the wiring layer 40 is lower than the upper surface, a recess is formed in the insulating layer 20, but since the corner of the opening end is small, disconnection of the wiring layer 40 is less likely to occur. When the upper surface of the conductive layer 30 is higher than the upper surface of the insulating layer 20, the conductive layer 30 is formed to protrude. However, since the angle formed by the insulating layer 20 and the conductive layer 30 is small, the wiring layer is formed. For example, when the thickness of the wiring layer 40 is about 5 μm at which the disconnection of the wiring layer 40 hardly occurs, the upper surface of the conductive layer 30 is formed at a height equal to or higher than a position lower by about 5 μm from the upper surface of the insulating layer 20. In this case, the conductive layer 3
The upper surface of the insulating layer 20 is formed at a height equal to or lower than the position approximately 5 μm higher than the upper surface of the insulating layer 20. That is, the height difference between the upper surface of the insulating layer 20 and the upper surface of the conductive layer 30 is set to about ± 5 μm.

The conductive layer 30 serves to protect the electrode 12 during the process. For example, when the electrode 12 is made of aluminum, aluminum has a property of being easily dissolved in a strongly alkaline solution. Therefore, the wiring layer 4 shown later
In the step of forming 0 (second step), for example, when the semiconductor chip 10 is immersed in a copper plating solution that is a strongly alkaline solution, the conductive layer 30 protects the electrode 12.

As a method of forming a nickel layer constituting at least a part of the conductive layer 30, a zincate treatment is performed on the electrode 12 to replace the surface on aluminum with zinc, and then immersed in an electroless nickel plating solution. Nickel may be deposited through a substitution reaction between zinc and nickel. Alternatively, aluminum may be immersed in a palladium solution that selectively adsorbs only on aluminum, and then immersed in an electroless nickel plating solution to precipitate nickel using palladium as a nucleus.

To form an additional gold layer on the nickel layer,
Further, it is immersed in an electroless gold plating solution to further form gold on the surface of nickel. By forming gold, electrical connection with the wiring layer 40 can be further ensured. In general, nickel can be deposited in a shorter time than gold, so that the first conductive layer 30 can be deposited in the first layer rather than in gold.
Preferably, the layer (lower layer) is formed of nickel, and the second layer (upper or surface layer) is formed of gold.

When the semiconductor chip 10 is immersed in a solution,
The surface excluding the surface on which the conductive layer 30, the catalyst 60 described later, or the wiring layer 40 is to be provided may be covered with a protective film in advance. Further, it is preferable to block light while the semiconductor chip 10 is immersed in the solution. This is a common matter in all the embodiments. Thus, it is possible to prevent a potential change between the electrodes in the solution caused by immersing the semiconductor chip 10 in the solution. Further, the protection film can prevent the catalyst 60 and the like from being provided in an unnecessary region.

(Second Step) Next, a wiring layer 40 is formed on the insulating layer 20 by passing over the conductive layer 30. For example, FIGS. 1C to 3B are diagrams illustrating a process of forming the wiring layer 40 by applying electroless plating. FIG.
It is preferable to roughen the surface of the insulating layer 20 before the step (C). By making the surface of the insulating layer 20 rough, the electroless plating can be easily performed even if the insulating layer 20 is made of an organic material. Surface roughening may be performed physically using, for example, plasma, or may be performed using an alkaline solution.

As shown in FIG. 1C, a resist 50 is formed.
Is formed on the entire surface of the conductive layer 30 and the insulating layer 20. Then, for example, a mask 52 that blocks the energy 54 such as light on a region where the wiring layer 40 is formed and transmits the energy 54 in the other region is disposed above the insulating layer 20, irradiated with the energy 54, and then developed. By doing so, the resist 50 is patterned (see FIG. 2A).

The above description is based on the assumption that the solubility is reduced when irradiated with energy (negative resist).
Although this example is used as 0, the resist 50 may be a resist whose solubility is increased by energy irradiation (positive resist). In the latter case, a mask for passing the energy 54 over the region where the wiring layer 40 is to be formed and blocking the energy 54 at other regions is provided. In any case, as shown in FIG. 2A, the resist 50 is patterned so as to avoid a region where the wiring layer 40 is to be formed.

Next, as shown in FIG. 2B, a catalyst 60 is provided on the entire surface. Specifically, a catalyst 60 is provided on the resist 50, the conductive layer 30, and the insulating layer 20. In the present embodiment, the catalyst 60 is palladium. As a method for forming the catalyst 60, for example, the semiconductor chip 10 is immersed in a mixed solution containing palladium and tin, and then treated with an acid such as hydrochloric acid to remove only palladium from the resist 50 and the conductive layer 3.
0 and the insulating layer 20.

By stripping the resist 50, as shown in FIG. 3A, the catalyst 60 can be provided only in the region where the wiring layer 40 is to be formed. When the resist 50 is stripped, the resist 50 may be irradiated with ultraviolet rays or may be immersed in a weakly alkaline solution to strip the resist 50. As a result, the resist 50 can be easily and reliably removed.

In the above-described example, the catalyst 60 is provided after patterning the resist 50, and then the resist 50 is peeled off, thereby exposing the catalyst 60 to the wiring pattern formation region. Unlike this example, after the catalyst 60 is provided on the entire surface, the resist 50 may be patterned and provided except for the wiring pattern formation region, so that the catalyst 60 may be exposed in the wiring pattern formation region. . In this case, the resist 50 is removed after the formation of the wiring layer 40 is completed.

When the catalyst 60 is provided, as shown in FIG. 3B, the wiring layer 40 is formed in the exposed region of the catalyst 60. The catalyst 60 is formed only in a region where the wiring layer 40 is to be formed. For example, when the wiring layer 40 is formed of copper,
By immersing the semiconductor chip 10 in a copper plating solution, the catalyst 6
Copper ions in the solution are reduced with palladium being 0 as a nucleus to deposit copper (wiring layer 40). Note that a plurality of different metals (for example, Ni + Cu, Ni + Au + Cu) may be used as a conductive material for forming the wiring layer 40.
Thus, the wiring layer 40 may be formed of a plurality of layers.

As shown in FIG. 3B, the wiring layer 40
It is electrically connected to the electrode 12 via the conductive layer 30. The wiring layer 40 is formed on the upper surface of the insulating layer 20 through the upper surface of the conductive layer 30. In the present embodiment,
Since the step between the conductive layer 30 and the insulating layer 20 is small, disconnection of the wiring layer 40 is less likely to occur.

(Details of Second Step) FIGS. 4A to 4
(D) is a diagram illustrating the details of the second step. In the present embodiment, the resist 50 is a negative resist, and the energy 50 is irradiated to decrease the solubility in the developing solution.

As shown in FIG. 4A, when a mask 52 is disposed above the resist 50 and energy 54 is irradiated from above the mask 52 toward the resist 50, the energy 54 is perpendicular to the resist 50. Not only that, it also enters obliquely. The vertically incident energy 54 irradiates the resist 50 corresponding to the pattern shape of the mask 52. On the other hand, the obliquely incident energy 54 is
The resist 50 is irradiated so as to wrap around from the boundary between the shielded part and the light-transmitting part.

Therefore, immediately below the boundary between the shielded portion and the transmitted portion of the mask 54, the energy 5 with respect to the resist 50 gradually increases as the mask 52 advances from the transmitted portion to the center of the shielded portion.
4, the irradiation depth of the energy 54 gradually decreases.

Immediately below the boundary between the shielded portion and the transmitting portion of the mask 54, the resist 50 is gradually irradiated with the energy 54 toward the center of the transmitting portion from the shielded portion of the mask 52. And the depth at which the energy 54 is irradiated gradually increases.

As described above, the obliquely incident energy 5
4, the irradiation depth of the energy 54 gradually changes, so that the interface between the portion of the resist 50 that is dissolved by the developing solution and the portion that is not dissolved by the developer becomes oblique. In addition, in the present embodiment, since the resist 50 is a negative resist, the portion irradiated with the energy 54 has reduced solubility in the developing solution and remains without being dissolved even when the development is performed. That is, in the region of the resist 50 where the energy 54 is irradiated shallowly, the lower portion (the portion on the back surface side)
Is dissolved, and the upper part (the part on the surface side) remains without being dissolved.

Therefore, as shown in FIG. 4B, the end of the resist 50 partially dissolved by the development protrudes outward from the lower part, and the end face inclined outward at the upper end. An inverse taper 51 is formed.

In order to form the reverse taper 51, it is preferable to use a negative resist having a property of hardly transmitting light. Specifically, it is preferable to use a black negative resist. For this purpose, a pigment may be included in the resist 50, or a carbon resist 50 may be used. In general, a negative resist is often baked after development. However, in the present embodiment, the resist 50 is peeled in a later step, and thus it is preferable that the resist is not baked.

As shown in FIGS. 4C and 4D, the catalyst 6 is formed on the resist 50 and in the region where the wiring layer 40 is to be formed.
Then, the resist 50 is peeled off. This is as described above. Here, since the resist 50 has the reverse taper 51 and the end of the catalyst 60 in contact with the resist 50 has the forward taper 61, the catalyst 6
The resist 50 can be easily removed while leaving 0 on the insulating layer 20. That is, the forward taper 61 of the catalyst 60 formed by the reverse taper 51 of the resist 50 is
Since the lower end protrudes outward from the upper end, stress in the direction in which the catalyst 60 is separated is less likely to be applied. As a result, when the resist 50 is stripped, a part of the catalyst 60
Since it can be prevented from being peeled off from the substrate, the electroless plating in the subsequent step can be performed accurately.

(Other Steps) Next, as shown in FIG. 3C, a step of providing a plurality of external terminals 70 on the wiring layer 40 may be included. Specifically, the external terminal 70 is provided on a portion of the wiring layer 40 other than the conductive layer 30. By doing so, the external terminal 70 is provided so as not to be on the joint between the electrode 12 and the conductive layer 30, and the stress applied to the external terminal 70 is not directly transmitted to the joint. Since the joint is not damaged, the reliability of the electrical connection is improved.

The external terminals 70 may be solder balls. For example, a solder resist is applied on the wiring layer 40, and a specific portion on the wiring layer 40 is exposed by photolithography or laser. The external terminals 70 may be formed by printing solder or the like on the exposed portions and performing a reflow process. The external terminals 70 may be formed of copper or the like in addition to solder. Alternatively, instead of actively forming the external terminals 70, a solder cream applied to the motherboard at the time of mounting the motherboard may be used, and the external terminals may be eventually formed by the surface tension at the time of melting. This semiconductor device
This is a so-called land grid array type semiconductor device.

The protective layer 80 may be provided on the insulating layer 20. The protective layer 80 preferably covers the wiring layer 40, in which case the wiring layer 40 can be protected. Further, the protective layer 80 may be provided around the external terminal 70. For example, the protective layer 8
0 may be provided to support or protect the external terminal 70.
When the protective layer 80 has a stress relaxation function, the stress applied to the external terminals 70 can be absorbed by the protective layer 80.

(Semiconductor Device) By the above steps, FIG.
The semiconductor device 1 shown in FIG. Semiconductor device 1
Is formed on the insulating layer 20 through the semiconductor chip 10 having the plurality of electrodes 12, the insulating layer 20 having the through hole 22 formed thereon, the conductive layer 30 provided on the electrode 12, and the conductive layer 30. Wiring layer 40. The upper surface of the conductive layer 30 is formed at a height equal to or higher than a position lower than the upper surface of the insulating layer 20 by the thickness of the wiring layer 40. Other details are as described above.

According to the present embodiment, the step between the upper surface of conductive layer 30 and the upper surface of insulating layer 20 is less than the thickness of wiring layer 40. Therefore, disconnection of the wiring layer 40 is less likely to occur.

(Modification 1) FIG. 5 is a diagram showing a modification of the method of forming a through hole in an insulating layer. In this modification, an insulating layer 20 is provided to cover the electrode 12, and as shown in FIG.
An energy 90 such as a laser beam is applied from above the electrode 12. Through hole 2 formed by irradiating energy 90
4 is formed perpendicular to the plane of the semiconductor chip 10. The through hole 24 may be formed by the method shown in FIG. As in this modification, the through hole 2
Even if 4 is formed vertically, the wiring layer 40 is hardly disconnected by applying the present invention.

(Modification 2) FIGS. 6A and 6B
FIG. 9 is a view showing a modification of the method of providing a catalyst. In this example, as shown in FIG.
It is provided in a region where 0 is to be formed.

In this example, the catalyst 62 is tin. The semiconductor chip 10 is immersed in a tin chloride solution to form a catalyst 62 on the resist 50, the conductive layer 30, and the insulating layer 20.
Is provided, and the resist 50 is peeled off as shown in FIG. Thus, the catalyst 62 can be provided in a region where the wiring layer 40 is to be formed.

Then, the catalyst 62 (tin) is replaced with the catalyst 60 (palladium). For example, palladium can be provided only in a region where the wiring layer 40 is to be formed by immersing the semiconductor chip 10 in a palladium chloride solution. As a result, a structure similar to that of FIG. 3A is obtained, and the wiring layer 40 can be formed by performing the above-described steps.

Also in this example, the catalyst 60 (for example, palladium) can be formed only in the region where the wiring pattern is to be formed, and the wiring pattern can be formed without performing the entire thin film forming step (sputtering) and the etching step. .

In the above description, electroless plating is employed as a method for forming the conductive layer 30, but other methods such as electroplating may be employed. This is the same in the following embodiments.

In this embodiment, the semiconductor chip 1
Although the respective steps are performed for the semiconductor wafer 0, the steps may be performed for each semiconductor element of the semiconductor wafer (an element that becomes a semiconductor chip when diced). In that case, in the above description, the semiconductor chip may be replaced with a semiconductor element of a semiconductor wafer. Further, the step of providing external terminals may be performed on the semiconductor wafer. Thereafter, the semiconductor wafer can be diced to obtain individual semiconductor devices. This can also be applied to the following embodiments.

According to the present embodiment, the wiring layer 4
Since 0 is not formed, the etching step of the wiring layer 40 can be omitted. Further, the stress generated by providing the wiring layer 40 on the entire surface can be prevented, and the treatment of waste liquid generated in the etching step is not required. Therefore, the wiring layer 40 can be formed by a simpler process without lowering the reliability.

In the above example, the wiring layer 40 is formed on the insulating layer 20. However, in the method of manufacturing a semiconductor device to which the present invention is applied, the wiring layer may be formed on the insulating layer. For example, the passivation film 14 may be used. Therefore, the wiring layer 40 is formed, for example, of the passivation film 1.
4 and the insulating layer 20.

(Second Embodiment) In the first embodiment, a method for manufacturing a semiconductor device in which the catalyst 60 formed on the entire surface is selectively removed by the resist 50 has been described. Alternatively, as shown in FIG. 7B, the catalyst 60 may be directly provided in a region where the wiring layer 40 is to be formed.
In the present embodiment, the catalyst 6 is formed by an inkjet method.
0 is directly provided in a region where the wiring layer 40 is formed. According to the ink jet system, it is possible to economically provide ink at high speed and without waste by applying technology practically used for ink jet printers. FIG. 7 (A)
The ink-jet head 92 shown in is used for, for example, an ink-jet printer, and a piezo-jet type using a piezoelectric element or a bubble-jet type using an electrothermal converter as an energy generating element can be used. The ejection area and ejection pattern can be set arbitrarily.

As a result, it is possible to form the wiring layer 40 only in the wiring pattern forming region without performing the etching step. Further, for example, since a step by photolithography using the resist 50 can be eliminated, the number of steps can be reduced. Therefore, a wiring pattern can be formed by a simpler process.

(Third Embodiment) FIGS. 8A to 9
FIG. 9B is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment to which the present invention is applied. Also in this embodiment, the semiconductor chip 10 used in the first embodiment is used.

(First Step) As shown in FIG. 8A, a conductive layer 100 is formed on the electrode 12. The conductive layer 100
The electrode 1 may be electrically connected to the electrode 12.
It may be provided in contact with at least a part of the surface of 2,
It may be formed so as to reach over the passivation film 14. The conductive layer 100 may be formed from a single layer or a plurality of layers. In the example shown in FIG. 8A, the conductive layer 100 includes a first layer (lower layer) made of nickel and a second layer (upper layer or surface layer) made of gold. The conductive layer 100 can be formed by electroless plating, and the details described in the first embodiment can be applied.

As shown in FIG. 8B, an insulating layer 110 is formed. The description of the insulating layer 20 according to the first embodiment applies to the insulating layer 110. Insulating layer 11
Numeral 0 is provided on the surface of the semiconductor chip 10 on which the electrodes 12 are formed (the surface on which the passivation film 14 is often formed), and is provided so as to cover the conductive layer 100. However, since the conductive layer 100 has a protruding shape, the thickness of the constituent material of the insulating layer 110 formed on the surface of the conductive layer 100 is smaller than the thickness of other parts. When the insulating layer 110 is formed, a through hole 114 is formed by a contact surface of the insulating layer 110 with the conductive layer 110.

As shown in FIG. 9A, a part of the insulating layer 110 is removed to expose a part of the conductive layer 100. For example, ashing such as the plasma 112 is applied. Specifically, when the entire surface portion of the insulating layer 110 is removed by ashing, the thickness of the constituent material of the insulating layer 110 formed on the upper surface of the conductive layer 100 is small, so that the conductive layer 100 is exposed in this portion. I do. Ashing is preferably light ashing. Further, by ashing the entire surface of the insulating layer 110, the surface of the insulating layer 110 for forming the wiring layer 120 can be roughened at the same time. At this time, since the purpose is to expose a part of the conductive layer 100, a region other than the region on the conductive layer 100 may be covered with a resist or the like.

(Second Step and Other Steps) FIG. 9B
As shown in FIG. 7, a wiring layer 120 passing through the conductive layer 100 is formed. Further, if necessary, a plurality of external terminals 130 are provided on the wiring layer 120, and a protective layer 140 covering the wiring layer 120 is provided.
To form For these details, the contents described in the first embodiment may be applied.

According to the present embodiment, first, conductive layer 100
Is provided and then the insulating layer 110 is formed.
The step of forming the through-hole 114 at 0 is unnecessary, and the process can be simplified.

FIG. 10 is a diagram showing a modification of the above-described first embodiment. 10, the upper surface of the conductive layer 230 is formed between the upper surface of the insulating layer 20 and a position lower than the upper surface of the insulating layer 20 by the thickness of the wiring layer 40. The contents described in the first embodiment can be applied to other configurations and manufacturing methods. Even in this embodiment, the same effects as in the first embodiment can be achieved.

FIG. 11 shows a circuit board 1000 on which the semiconductor device 1 according to the present embodiment is mounted. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board 1000. Wiring patterns made of, for example, copper or the like are formed on the circuit board 1000 so as to form a desired circuit, and these wiring patterns and the external terminals 70 of the semiconductor device 1 are electrically connected to each other by mechanically connecting them. Conduct continuity.

As an electronic apparatus having the semiconductor device 1 to which the present invention is applied, FIG. 12 shows a notebook personal computer 2000, and FIG. 13 shows a mobile phone 3000.

[Brief description of the drawings]

FIGS. 1A to 1C are views showing a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied;

FIGS. 2A and 2B are views showing a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied;

FIGS. 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied; FIGS.

FIGS. 4A to 4D are diagrams illustrating details of a second step in the first embodiment.

FIG. 5 is a diagram illustrating a modification of the first embodiment;

FIGS. 6A and 6B are diagrams showing a modification of the first embodiment. FIGS.

FIGS. 7A and 7B are diagrams showing a method for manufacturing a semiconductor device according to a second embodiment to which the present invention is applied.

FIGS. 8A and 8B are diagrams showing a method for manufacturing a semiconductor device according to a third embodiment to which the present invention is applied.

FIGS. 9A and 9B are diagrams showing a method for manufacturing a semiconductor device according to a third embodiment to which the present invention is applied.

FIG. 10 is a diagram showing a modification of the present embodiment.

FIG. 11 is a diagram illustrating a circuit board on which the semiconductor device according to the present embodiment is mounted;

FIG. 12 is a diagram illustrating an electronic device including the semiconductor device according to the present embodiment;

FIG. 13 is a diagram illustrating an electronic device including the semiconductor device according to the embodiment;

DESCRIPTION OF SYMBOLS 10 semiconductor chip 12 electrode 20 insulating layer 22 through hole 24 through hole 30 conductive layer 40 wiring layer 42 conductive layer 70 external terminal 80 protective layer 100 conductive layer 110 insulating layer 114 through hole 120 wiring layer 130 external terminal 140 Protective layer

Claims (17)

[Claims] A semiconductor element having an electrode; a conductive layer provided on a surface of the semiconductor element on which the electrode is formed, the conductive layer being electrically connected to the electrode; and a semiconductor layer formed around the conductive layer. And an interconnect layer electrically connected to the conductive layer and formed on the insulating layer, wherein an upper surface of the conductive layer has an upper surface of the insulating layer; and A semiconductor device formed between an upper surface of an insulating layer and a position raised by the thickness of the wiring layer. 2. A semiconductor element having an electrode; a conductive layer provided on a surface of the semiconductor element on which the electrode is formed, the conductive layer being electrically connected to the electrode; and a semiconductor layer formed around the conductive layer. And an interconnect layer electrically connected to the conductive layer and formed on the insulating layer, wherein an upper surface of the conductive layer has an upper surface of the insulating layer; and A semiconductor device formed between a position lower than an upper surface of an insulating layer by a thickness of the wiring layer. 3. The semiconductor device according to claim 1, wherein said wiring layer is formed with a thickness of about 5 μm, and a height difference between an upper surface of said conductive layer and an upper surface of said insulating layer is , A semiconductor device within about 5 μm. 4. The semiconductor device according to claim 1, wherein a plurality of external terminals are provided on the wiring layer at a position avoiding the conductive layer. 5. The semiconductor device according to claim 4, wherein a protective layer is provided on the insulating layer and around the external terminal. 6. The semiconductor device according to claim 1, wherein said insulating layer has a stress relaxation function. 7. A circuit board on which the semiconductor device according to claim 1 is mounted. 8. An electronic apparatus comprising the semiconductor device according to claim 1. 9. A first step of providing a conductive layer electrically connected to the electrode and an insulating layer formed around the conductive layer on a surface of the semiconductor element on which the electrode is formed; A second step of electrically connecting to the conductive layer to form a wiring layer formed on the insulating layer, comprising: forming an upper surface of the conductive layer on the upper surface of the insulating layer; A method of manufacturing a semiconductor device, wherein the semiconductor device is formed so as to be located between the upper surface of the substrate and a position raised by the thickness of the wiring layer. 10. A first step of providing a conductive layer electrically connected to the electrode and an insulating layer formed around the conductive layer on a surface of the semiconductor element on which the electrode is formed; A second step of electrically connecting to the conductive layer to form a wiring layer formed on the insulating layer, comprising: forming an upper surface of the conductive layer on the upper surface of the insulating layer; A method of manufacturing a semiconductor device, wherein the semiconductor device is formed so as to be located between the upper surface of the substrate and a position lowered by the thickness of the wiring layer. 11. The method for manufacturing a semiconductor device according to claim 9, wherein, in the first step, after forming the insulating layer over the electrode, the through hole is formed on the electrode. Then, a method of manufacturing a semiconductor device provided with the conductive layer. 12. The method for manufacturing a semiconductor device according to claim 9, wherein, in the first step, after the conductive layer is provided on the electrode and the insulating layer is formed to cover the conductive layer. A method of manufacturing a semiconductor device in which a part of the insulating layer is removed to expose a part of the conductive layer. 13. The method of manufacturing a semiconductor device according to claim 12, wherein a part of said insulating layer is removed by ashing. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the wiring layer is formed with a thickness of about 5 μm, and a difference in height between the upper surface of the conductive layer and the upper surface of the insulating layer is determined by: A method for manufacturing a semiconductor device having a thickness of about 5 μm or less. 15. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of providing a plurality of external terminals on the wiring layer at a position avoiding the conductive layer. Device manufacturing method. 16. The method of manufacturing a semiconductor device according to claim 15, further comprising: providing a protective layer on the insulating layer and around the external terminal. 17. The method for manufacturing a semiconductor device according to claim 9, wherein the insulating layer is formed of a material having a stress relaxation function.