JP2001142843A - Device and method for controlling data transfer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the bus band of an input/output bus by limiting data transfer between a CPU bus and the input/output bus by adding a simple circuit. SOLUTION: The data transfer controller for controlling data transfer between a CPU bus 4 and an image bus 10 has a FIFO memory 22 for temporarily storing data to be transferred, a CPU bus interface part 21 for issuing a data transfer request (C REQ) to the CPU bus 4, transferring the prescribed amount of data from the CPU bus 4 to the FIFO memory 22 and storing these data, an image bus interface part 23 for transferring a prescribed amount of data stored in the FIFO memory 22 to the image bus 10 corresponding to a data transfer request (I REQ) to the image bus 10, a selector 26 and a down counter 25 for delaying the generation of the next data transfer request corresponding to signals 41 and 42 showing the operating state of an image input part or image output part connected to the image bus after the end of data transfer (C DONE or I DONE) by the CPU bus interface part 21 or image bus interface part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device for controlling data transfer between a CPU bus and an input / output bus, and a method therefor.

[0002]

2. Description of the Related Art By connecting a CPU bus and an input / output bus,
A bus bridge circuit that controls data transfer between these two buses is known. In the data transfer using this bridge circuit, the data transfer rate of the bridge circuit is high, and therefore, it is conceivable that most of the bus bandwidth of the input / output bus is occupied. When data transfer by the bridge circuit occupies most of the bus bandwidth of the input / output bus in this way, when data transfer is performed between these buses, for example, a video camera connected to the input / output bus There is a possibility that data input / output to / from a display or the like cannot be transferred via the bus, which may hinder image input and display output.

[0003]

In particular, when a moving image is fetched and the moving image data is displayed in real time, a method usually used for displaying the moving image without hindrance is to use a video bus. Prioritize the arbiters, set the priority of data transfer by the bus bridge circuit low,
Data transfer to a moving image capturing device such as a video camera or a moving image display device is prioritized so as to prevent image distortion or the like.

However, providing such an arbiter and prioritizing the arbiters complicates the circuit configuration and increases the circuit size.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional example, and the addition of a simple circuit limits the data transfer between the CPU bus and the input / output bus, thereby reducing the bus bandwidth of the input / output bus. It is an object of the present invention to provide a data transfer control device and method for securing the same.

Another object of the present invention is to control data transfer between a CPU bus and an input / output bus in accordance with an operation state of an image input / output unit connected to the input / output bus.
It is an object of the present invention to provide a data transfer control device and a method thereof that maximize the data transfer efficiency between buses and do not affect the operation of an image input / output unit connected to an input / output bus.

[0007]

In order to achieve the above object, a data transfer control device according to the present invention has the following arrangement. That is, a data transfer control device for controlling data transfer between a CPU bus and an input / output bus, comprising: storage means for temporarily storing data to be transferred; A CPU for transferring and storing a predetermined amount of data from the CPU bus to the storage means.
Bus interface means; input / output bus interface means for transferring the predetermined amount of data stored in the storage means to the input / output bus in response to a data transfer request to the input / output bus; Means or delay control means for delaying generation of the next data transfer request according to the operation state of the image input unit or image output unit connected to the input / output bus after the data transfer by the input / output bus interface means is completed. , Is characterized by having.

In order to achieve the above object, a data transfer control device according to the present invention has the following configuration. That is, CP
What is claimed is: 1. A data transfer control device for controlling data transfer between a U bus and an input / output bus, comprising: storage means for temporarily storing data to be transferred; An input / output bus interface means for transferring and storing a predetermined amount of data from the input / output bus to the storage means, and the predetermined amount stored in the storage means in response to a data transfer request to the CPU bus. CPU bus interface means for transferring data to the CPU bus, and an image input unit or an image output unit connected to the input / output bus after the data transfer by the CPU bus interface means or the input / output bus interface means is completed. And delay control means for delaying the generation of the next data transfer request in accordance with the operation state of (1).

To achieve the above object, a data transfer method according to the present invention includes the following steps. That is, a data transfer control method for controlling data transfer between a CPU bus and an input / output bus, wherein a predetermined amount of data is transferred from the CPU bus to a memory in response to a data transfer request to the CPU bus. A transfer step of transferring the predetermined amount of data stored in the memory to the input / output bus in response to a data transfer request to the input / output bus; A delay control step of delaying the generation of the next data transfer request according to the operation state of the image input unit or the image output unit connected to the input / output bus after the transfer step is completed.

[0010] In order to achieve the above object, the data transfer method of the present invention comprises the following steps. That is, a data transfer control method for controlling data transfer between a CPU bus and an input / output bus, wherein a predetermined amount of data is transferred from the input / output bus to a memory in response to a data transfer request to the input / output bus. Transferring the predetermined amount of data stored in the memory to the CPU bus in response to a data transfer request to the CPU bus; And a delay control step of delaying the generation of the next data transfer request according to the operation state of the image input unit or the image output unit connected to the input / output bus after the step is completed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present embodiment will be briefly described. A CPU bus and an image bus are connected by a bridge circuit, and each of an image capturing device and a display device connected to the image bus is effective. A signal indicating the scanning period is input to the bridge circuit. In the bridge circuit, based on the signal indicating the effective scanning period supplied from the image capturing device and the display device, for example, if both are not in the effective scanning period, the next immediately after transferring the predetermined amount of data, Start data transfer. On the other hand, if any of the signals indicates the valid scanning period, the next data transfer is started after a predetermined amount of data transfer and after a while. This allows the CPU
The frequency of occurrence of data transfer between the bus and the image bus can be limited, so that the image capturing device and the display device can be given more bus bandwidth in the image bus.

In addition, by limiting the frequency of data transfer of the bridge circuit by inserting a weight in this way, not only the bus bandwidth of the image capturing device and the display device can be ensured as a result, but also the present embodiment is not limited to this. According to this, unlike prioritizing bus use by bus arbiters,
Even when the image capturing device and the display device are in the effective scanning period, it is possible to provide an effect that a certain bus band can be given to data transfer by the bridge circuit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a moving image data transfer apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a CPU, which controls the operation of the entire apparatus. 2 is a CPU memory, a CPU
It is connected to the bus 4, is used as a work memory area during various control operations by the CPU 1, and stores various programs executed by the CPU 1. Three
Is an external device controller that controls the image data stored in the memory 2 to be stored in an external storage element such as a flash card, or controls to read the image data stored in the external storage element.

A bridge circuit 5 connects the CPU bus 4 and the image bus 10 and controls data exchange between these buses. 6 is an image capturing device,
For example, a moving image can be captured like a digital video camera. A display device 7 can capture and display moving image data transmitted via the image bus 10. Reference numeral 8 denotes an image memory which is used to temporarily record a moving image data image captured by the image capturing device 6. A compression / expansion circuit 9 compresses / expands the image captured by the image capturing device 6 as a still image.
Reference numeral 11 denotes an image bus arbiter, which here is a completely fair bus arbiter, which controls data transfer on the image bus 10 fairly without any particular priority. 41
Is a signal (C_ACTIVE) indicating the effective scanning period of the image signal input by the image capturing device 6;
Is a signal (D_ACTIVE) indicating the effective scanning period of the display image output from the display device 7.

FIG. 2 is a block diagram showing a schematic configuration of the bridge circuit 5 according to the present embodiment. In FIG. 2,
Although a circuit configuration for transferring data from the CPU bus 4 to the image bus 10 is mainly shown, a case where data is transferred from the image bus 10 to the CPU bus 4 can be similarly realized.

Reference numeral 21 denotes a CPU bus interface (I
/ F) circuit controls the interface with the CPU bus 4. Reference numeral 22 denotes a FIFO memory which temporarily stores data transferred from the CPU bus 4 to the image bus 10 so as to absorb a difference in data transfer timing between the CPU bus 4 and the image data bus 10. I have. 2
An image bus interface (I / F) circuit 3 controls an interface with the image bus 10.
A controller 24 controls the operations of the CPU bus interface circuit 21 and the image bus interface circuit 23. Reference numeral 25 denotes a down counter which, under the control of the controller 24, receives a signal (I_DONE) indicating that the designated data transfer has been completed, and controls the timing until the next data transfer is started. Reference numeral 26 denotes a selector, which inputs signals 41 and 42 indicating the above-described effective scanning period and determines an initial value to be set in the down counter 25. This initial value means a value set in advance by the CPU or fixed by hardware. Reference numeral 43 denotes a logical sum (OR) circuit, which takes the logical sum of the signal 41 and the signal 42. The selector 26 inputs only the signal 41 when the priority is given to capturing the image signal from the image capturing device 6 or only the signal 42 when the image display on the display device 7 is prioritized. You may make it.

FIGS. 3 and 4 illustrate the operation of the bridge circuit 5 of the present embodiment for transferring four beats of data from the CPU bus 4 to the image memory 8 connected to the image bus 10. FIG. 3 is a timing chart. FIG. 3 shows the case where the A input (0) is selected by the selector 26 (that is, the A input obtained from the image capturing
FIG. 4 shows a case in which the CTIVE signal is at a low level (not during the effective scanning period), and FIG. 4 shows a case where the B input (3) is selected by the selector 26 (that is, the ACTIVE signal obtained from the image capturing device 6 and the display device 7). Is at a high level (in an effective scanning period).

FIG. 9 shows an ACTI showing this directed scanning period.
FIG. 4 is a diagram for explaining a VE signal, in which a video signal is output at a high level during a horizontal scanning period of the video signal while the video signal is valid.

Referring to FIG. 3 and FIG.
Request signal to the CPU bus 4 (C_RE
Q) is supplied through a CPU bus I / F 21 to a CPU bus arbiter (not shown).
A permission signal (C_
GNT) is supplied.

When the permission signal (C_GNT) goes high, the CPU bus interface circuit 21
The operation of reading data from the U bus 4 is started. Specifically, the CPU bus interface circuit 21 reads the read address (C_ADD) set by the controller 24.
R) to the CPU bus 4 to output data (C_DATA) (4 in this example) output from the memory 2 at a predetermined timing.
(For a beat) to the FIFO memory 22.

When the CPU bus interface circuit 21 reads the data (C_DATA) for these four beats and writes the data into the FIFO memory 22, the controller 2
4 indicating that the read operation has been completed (C_
DONE). As a result, the controller 24 outputs a transfer request signal (I_REQ) to the image bus interface circuit 23 via the image bus 10 to request a write operation to the image memory 8. This transfer request signal (I_REQ)
Is supplied to the image bus arbiter 11 through the image bus interface circuit 23. Then, when a signal (I_GNT) indicating that the bus right of the image bus 10 has been obtained is obtained from the arbiter 11, the image bus interface circuit 23 sends the address (I_GNT) from the controller 24.
ADDR), and outputs the write address of the image memory 8 to the image bus 10. After that, the image bus interface circuit 23 reads out the data (I_DATA) to be written in the image memory 8 from the FIFO memory 22 and outputs it to the image bus 10. In this case, the FIFO memory 2
The image data for 4 beats written in 2 is sequentially output to the image bus 10 and written to the address of the image memory 8 specified by the address (I_ADDR) from the controller 24. When the transfer of the image data to the image memory 8 is completed in this manner, the image bus interface circuit 23
Sends a transfer completion signal (I_DONE) indicating that writing of the specified four beats of data has been completed to the controller 2
4 is output.

Further, in this embodiment, the transfer completion signal (I_DONE) is supplied as a load signal of the down counter 25. That is, the transfer completion signal (I_DON
When E) is input, the down counter 25 sets the A or B input value selected by the selector 26 at that time as an initial value. At this time, the image capturing device 6
If either the signal (C_ACTIVE) indicating the effective scanning period of the image display device 7 or the signal (D_ACTIVE) indicating the effective scanning period of the image display device 7 is at a high level, the initial value set in the down counter 25 is the value of the B input ( For example, in the example of FIG. The down counter 25 in which the initial value is set in this way performs a countdown operation in synchronization with the clock signal (CPU CLK), and outputs a borrow (Borrow) signal to the controller 24 when the counter value becomes “0”. . As a result, the controller 24 outputs a request signal (C_REQ) to the CPU bus interface circuit 21 to perform a new data transfer.

Thus, as shown in FIGS. 3 and 4,
Depending on the state of the image capturing device 6 and / or the image display device 7 (whether or not during the effective scanning period), the controller 24 performs the next data transfer with the wait time “0” as shown in FIG. Request signal (C_
REQ) to the CPU bus interface circuit 21. On the other hand, in the case of the effective scanning period in the image capturing device 6 and / or the image display device 7, the CPU_CLK
After waiting for three clocks, the controller 24 outputs a request signal (C_REQ) to the CPU bus interface circuit 21 to perform the next data transfer.

Although the data transfer from the CPU bus 4 to the image bus 10 has been described in the above-described embodiment, the data transfer from the image bus 10 to the CPU bus 4 is realized by the same configuration. it can.

As described above, according to the first embodiment, with a simple circuit configuration, a cycle for displaying the effective scanning area of an image or a cycle during which the effective scanning area of an image is being acquired. The bus load can be reduced.

[Second Embodiment] In the above-described first embodiment, a variable weight is inserted after, for example, one data transfer for four beats, but the timing at which this weight is inserted may of course be other than this. .

FIG. 5 is a block diagram showing a configuration of a data transfer device according to the second embodiment of the present invention. Portions common to the configuration of FIG. 2 described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 5, the down counter 25
At the end of the data transfer from the PU bus 4 to the FIFO memory 22, the transfer completion signal (C_DONE) output from the CPU bus interface circuit 21 loads the initial value selected by the selector 26.

FIG. 6 is a timing chart showing the operation timing of the circuit shown in FIG. 5. When the completion signal (C_DONE) is output after 4-beat data transfer, a signal (C_ACTIVE) indicating the effective scanning period of the image capturing device 6 is output. And a signal (D_ACTIVE) indicating the effective scanning period of the image display device 7 is at a high level.

As a result, the B selected by the selector 26
The input (3) is loaded as an initial value into the down counter 25, and after counting the clock signal (CPU_CLK) for three clocks, a transfer request signal (I_REQ) is output from the controller 24 to the image bus interface circuit 23. I have.

As a result, the designated data amount is
After the transfer to the O memory, a variable wait can be inserted to start the data transfer from the FIFO memory to the image bus.

Third Embodiment In the first and second embodiments, the wait time that can be set in the bridge circuit 5 is controlled in two stages, for example, “0” and “3”. Of course, finer control is possible, and a configuration without using the down counter 25 is also possible.

FIG. 7A is a block diagram showing a configuration of a bridge circuit 5 according to a third embodiment of the present invention. Portions common to the above-described drawings are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 7A, reference numeral 27 denotes a counter.
The CPU bus interface circuit 21 allows the CPU
It is cleared by a completion signal (C_DONE) indicating that the data transfer from the memory 2 of the bus 4 to the FIFO memory 22 has been completed, and the clock (Image_CL) of the image bus 10 while the signal 44 output from the comparator 29 is at a low level.
Count up at K). The selector 28 selects a weight value according to the state of the image capturing device 6 and the display device 7. FIG. 7B shows an example of a method of selecting the weight value. The comparator 29 includes a counter 27
Is compared with the output (B input) of the selector 28, and when A ≧ B, the signal 44 is set to the high level and output to the controller 24 and the counter 27.

FIG. 8 is a timing chart showing the operation of the circuit shown in FIG. 7A. A signal 41 indicating the effective scanning period of the image capturing device 6 when the completion signal (C_DONE) is output after 4-beat data transfer. The case where the B input (3) of the selector 28 is selected by (C_ACTIVE) and the signal 42 (D_ACTIVE) indicating the effective scanning period of the image display device 7 is shown.

Here, the completion signal after data transfer (C_DON
When the counter 28 is reset by E), the A input of the comparator 29 becomes "0", and the output signal 44 thereof becomes low level. This enables the counter 27 to count, and the clock (Image_CL) of the image bus 10
Start counting up in synchronization with K). Thus, when the count value of the counter 27 becomes “3”, the output signal 44 of the comparator 29 becomes high level and is supplied to the controller 24. At the same time, the counter 27 is disabled for counting, and the counting by the counter 27 is stopped.

When the controller 24 detects that the signal 44 has become high level, it outputs a transfer request (I_REQ) to the image bus interface circuit 23, and
Data transfer from the memory 22 to the image memory 8 of the image bus 10 is started.

As described above, according to the third embodiment, the wait time that can be set in the bridge circuit 5 is determined by the signal 4
By making the number of stages possible according to 1 and 42, more flexible circuit design can be performed.

In the third embodiment, the timing at which a wait is inserted is the same as in the second embodiment.
Although the data transfer from the memory to the FIFO memory 22 is terminated, for example, as in the first embodiment,
Of course, it may be at the end of the data transfer from the to the image bus 10.

Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus including one device (for example, a copying machine, a facsimile machine, etc.) ) May be applied.

Another object of the present invention is to provide a storage medium (or a storage medium) storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer of the system or the apparatus. (Or CPU or MPU) by reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. By executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the program code is read based on the instruction of the program code. This also includes the case where the CPU provided in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

As described above, according to the present embodiment, a much simpler circuit configuration than that of prioritizing the bus arbiters is used, and a large number of bus bandwidths are required for an image capturing device or an image display device which needs to be compatible at that time. It is possible to give.

Further, during a period when the image capturing device or the image display device does not require data transfer, the data transfer capability of the bridge circuit can be sufficiently exhibited.

[0047]

As described above, according to the present invention, by adding a simple circuit, the data transfer between the CPU bus and the input / output bus is restricted, thereby securing the bus bandwidth of the input / output bus. can do.

According to the present invention, the data transfer between the CPU bus and the input / output bus is controlled in accordance with the operation state of the image input / output unit connected to the input / output bus.
There is an effect that the operation of the image input / output unit connected to the input / output bus is not affected while maximizing the data transfer efficiency between the buses.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a bridge circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining an operation of the bridge circuit according to the first embodiment.

FIG. 4 is a timing chart for explaining an operation of the bridge circuit according to the first embodiment;

FIG. 5 is a block diagram showing a configuration of a bridge circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the bridge circuit according to the second embodiment.

FIG. 7A is a block diagram showing a configuration of a bridge circuit according to a third embodiment of the present invention, and FIG. 7B is a diagram for explaining selection by a selector.

FIG. 8 is a timing chart for explaining an operation of the bridge circuit according to the third embodiment.

FIG. 9 is a diagram illustrating a signal indicating an effective scanning period of a video signal.

Claims (17)

[Claims] 1. A data transfer control device for controlling data transfer between a CPU bus and an input / output bus, comprising: storage means for temporarily storing data to be transferred; and data transfer to the CPU bus. Upon request, the CP
CPU bus interface means for transferring and storing a predetermined amount of data from a U bus to the storage means; and transferring the predetermined amount of data stored in the storage means in response to a data transfer request to the input / output bus. An input / output bus interface for transferring data to the input / output bus; and an image input unit or an image output unit connected to the input / output bus after data transfer by the CPU bus interface or the input / output bus interface is completed. A data transfer control device, comprising: delay control means for delaying generation of a next data transfer request in accordance with an operation state. 2. A data transfer control device for controlling data transfer between a CPU bus and an input / output bus, comprising: storage means for temporarily storing data to be transferred; An input / output bus interface for transferring and storing a predetermined amount of data from the input / output bus to the storage in response to a transfer request; and storing the data in the storage in response to a data transfer request to the CPU bus. The predetermined amount of data
A CPU bus interface unit for transferring data to the bus, and after the data transfer by the CPU bus interface unit or the input / output bus interface unit is completed, according to an operation state of an image input unit or an image output unit connected to the input / output bus. And a delay control means for delaying the generation of the next data transfer request. 3. The data transfer control device according to claim 1, wherein the image input unit is a video camera. 4. The data transfer control device according to claim 1, wherein the image output unit is a display. 5. The data transfer control device according to claim 1, wherein said storage means includes a first-in first-out memory. 6. The apparatus according to claim 1, wherein the operation state corresponds to whether an image signal is within an effective scanning period at the time of inputting or outputting an image. Data transfer control device. 7. The data transfer control device according to claim 1, wherein said delay control means can set a plurality of delay times. 8. The apparatus according to claim 1, wherein said delay control means can set different delay times according to the respective operation states of said image input section and said image output section. 2. The data transfer control device according to claim 1. 9. A data transfer control method for controlling data transfer between a CPU bus and an input / output bus, the method comprising: controlling the CP in response to a data transfer request to the CPU bus.
Transferring a predetermined amount of data from the U bus to the memory and storing the data; and responding to a data transfer request to the input / output bus, transferring the predetermined amount of data stored in the memory to the input / output bus. A transfer step of transferring, and after the storage step or the transfer step, a delay for delaying generation of a next data transfer request according to an operation state of an image input unit or an image output unit connected to the input / output bus. And a control step. 10. A data transfer control method for controlling data transfer between a CPU bus and an input / output bus, the method comprising the steps of: transferring data from the input / output bus to a memory in response to a data transfer request to the input / output bus; A storage step of transferring and storing a fixed amount of data; a transfer step of transferring the predetermined amount of data stored in the memory to the CPU bus in response to a data transfer request to the CPU bus; After the step and the transfer step, a delay control step of delaying generation of the next data transfer request according to an operation state of the image input unit or the image output unit connected to the input / output bus. Data transfer control method. 11. The data transfer control method according to claim 9, wherein the image input unit is a video camera. 12. The data transfer control method according to claim 9, wherein the image output unit is a display. 13. The data transfer control method according to claim 9, wherein said memory includes a first-in first-out memory. 14. The apparatus according to claim 9, wherein the operation state corresponds to whether an image signal is within an effective scanning period when an image is input or output. Data transfer control method. 15. The delay control step according to claim 9, wherein a plurality of delay times can be set.
The data transfer control method according to any one of the above. 16. The delay control step according to claim 9, wherein different delay times can be set according to the respective operation states of the image input unit and the image output unit. 2. The data transfer control method according to claim 1. 17. A computer-readable storage medium storing a program for executing the data transfer control method according to claim 9. Description: