JP2001136054A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional semiconductor integrated circuit where resetting to a conventional latch circuit has been realized by ANDing a data signal and a reset signal but the configuration like this results in an increase in the area required for addition of a NAND circuit. SOLUTION: The latch circuit of this invention consists of two nMOS transistors(TRs) 102, 104 having terminals 107, 108, by which the respective substrate potentials can be controlled. A substrate potential changeover means employing the terminals 107, 108 is used to control the substrate potentials of the TRs 102, 104. Controlling the substrate potentials to control on/off of the TRs 102, 104 conducts resetting. The latch circuit with a reset function can be produced without the need for addition of a NAND circuit according to the adoption of the method above so as to reduce the area of the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method of resetting a logic held by a latch circuit.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional latch having a synchronous reset function. In FIG. 2, the logical product of the data signal and the reset signal is taken to reset the latch circuit. When resetting, by setting the reset signal to logic "0", the input data to the latch is forcibly set to logic "0", and the logic "0" is latched at the same time as the clock is input, and the reset is performed. Done. FIG. 3 shows a latch circuit having an asynchronous reset function. In FIG.
When a loop is formed by the NAND circuits 303 and 304 and normal operation is performed, logic "1" is input to the reset signal R and the set signal S. To perform a reset, the reset signal is set to logic "0" and the set signal is set to logic "1", so that the NAND circuit 304 is reset.
, The output of the NAND circuit 303 is forcibly fixed to the logic "1", and the output of the NAND circuit 303 is fixed to the logic "0". In both the synchronous type and the asynchronous type, the logic is forcibly determined by taking the logical product with the reset signal.

[0003]

However, FIG.
In the case of the configuration as shown in FIG.
Since one or more circuits are required, 6 to 8 transistors are added as compared with the minimum latch circuit having no reset function shown in FIG. This is approximately the same number of transistors as the latch circuit of FIG. In other words, the area of the latch circuit is doubled only by adding the reset function.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit which can reduce the area of a latch circuit having a reset function.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a plurality of MOS transistors each having a terminal whose substrate potential can be controlled; a latch circuit including the MOS transistor; A semiconductor integrated circuit having substrate potential switching means for controlling a substrate potential by using a semiconductor integrated circuit. An example is shown in FIG. With the configuration of FIG. 1, the number of NAND circuits used in FIGS. 2 and 3 can be reduced, and an increase in area can be suppressed.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In FIG. 1, reference numerals 102 and 104 denote nMOS transistors whose pWELLs are electrically independent. Q is logic "0" from Q is logic "1"
The following shows the procedure of the reset operation. Before resetting
The pWELLs of the nMOS transistors 102 and 104 are dropped to GND by the switches 107 and 108. When resetting, switch the 107, 108 switches to get 102 pWELL
Is given a negative potential, and a positive potential is given to 104 pWELL. By applying a potential to pWELL, a substrate bias effect appears. 102 nMO due to substrate bias effect
Since the threshold value of the S transistor decreases and the transistor is turned on (low resistance), current flows between the drain and the source. On the other hand, the nMOS transistor 104 has an increased threshold value and is turned off (high resistance).
It becomes 0. If this state is continued for a while, the positive feedback is applied, and Q becomes logic “0”. Then 107,108
By switching the switches, the substrate bias of 102, 104 pWELL is set to GND, and the reset operation is completed. Also, the setting operation of Q from logic "0" to logic "1" can be realized by giving a positive potential to pWELL of 102 and a negative potential to pWELL of 104. As an example, FIG. 5 shows a configuration diagram of a latch circuit having set and reset means. Setting and resetting can be performed by switching the switches 507 and 508.

(Second Embodiment) The reset method described in the first embodiment is excellent in resetting many latch circuits at once. For example, it can be applied to a memory circuit such as an SRAM. FIG. 6 shows an example. Two pWELL
And pWELL 1 has 601,602,603 for the nMOS transistors in the two inverters of each memory element.
And 611,612,613 for pWELL 2. The reset operation can be performed by controlling the voltage of the pWELL terminal with the switches 614 and 615. By doing so, the N NAND circuits required in the conventional circuit can be replaced with W circuits.
A reset operation can be performed with only two terminals for controlling ELL. The same applies to the set operation.
You can do this by switching 5.

In the above description, the nMOS transistor
The explanation has been focused on pWELL.
The same effect can be obtained by manipulating the substrate potential of WELL. The same effect can be obtained by simultaneously operating the substrate potentials of pWELL and nWELL, or by operating the substrate potential for one transistor in the inverter loop of the latch circuit.

[0009]

As described above, with the semiconductor integrated circuit shown in the first embodiment, the number of NAND circuits conventionally required for performing a reset operation can be reduced and high integration can be achieved. In particular, when many latch circuits are reset at one time as shown in the second embodiment, the reset operation can be performed only with the terminal for controlling the WELL without depending on the number of latch circuits. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for realizing a first embodiment of the present invention.

FIG. 2 is a conventional latch circuit with synchronous reset.

FIG. 3 is a conventional latch circuit with asynchronous reset.

FIG. 4 is a diagram of an example of a latch circuit with the minimum number of transistors;

FIG. 5 is a circuit diagram for realizing the first embodiment of the present invention.

FIG. 6 is a circuit diagram for realizing a second embodiment of the present invention.

[Explanation of symbols]

101 102 and pMOS transistor forming an inverter circuit 102 pWELL separated 101 and nMOS transistor 103 forming an inverter circuit 103 104 and pMOS transistor forming an inverter circuit 104 103 and pMOS separated nMOS transistor forming an inverter circuit 105 nMOS transistor to be a pass transistor 106 nMOS transistor to be a pass transistor 107 102 pWELL substrate potential switching means 108 102 pWELL substrate potential switching means 201 202 and pMOS transistor 202 pWELL forming an inverter circuit are separated 201 and an nMOS transistor 203 forming an inverter circuit 203 204 and a pMOS transistor 204 forming an inverter circuit 204 with separated pWELLs and an nMOS transistor 205 forming an inverter circuit 205 nMOS transistor as a pass transistor 206 nMOS transistor 207 as a pass transistor NAND circuit that takes the logical product of the signal and reset signal 208 Inverter circuit that inverts the output logic of 207 301 nMOS transistor that serves as a pass transistor 302 nMOS transistor that serves as a pass transistor 303 Logical product of the set signal and latched as a pair with 304 NAND circuit 304 that constitutes the circuit ANDs with the reset signal, and NAND circuit 303 that constitutes a latch circuit in pairs with 303 401 nMOS transistor that is a pass transistor 402 nMOS transistor 403 that is a pass transistor 403 404 constitutes a latch circuit Inverter circuit 404 403 and an inverter circuit 501 which constitutes a latch circuit in pairs with pMOS transistor 502 which constitutes an inverter circuit 502 pWELL 501 separated nMOS transistor which constitutes an inverter circuit 503 504 and a pMOS transistor which constitutes an inverter circuit 504 pWELL separated 503 and inverter circuit Constituting nMOS transistor 505 nMOS transistor to be a pass transistor 506 nMOS transistor to be a pass transistor 507 Means for switching pWELL substrate potential of 502 508 Means for switching pWELL substrate potential of 504 601 Inverter circuit 602 paired with a memory element 602 Inverter circuit that becomes a memory element when paired with 612 603 Inverter circuit that becomes a memory element when paired with 613 611 Inverter circuit that becomes a memory element when paired with 601 612 Inverter circuit that becomes a memory element when paired with 602 613 A memory element that becomes a memory element when paired Inverter circuit 614 Means for switching the substrate potential of pWELL 1 615 Means for switching the substrate potential of pWELL 2

Claims (4)

[Claims] 1. A semiconductor device comprising: a plurality of MOS transistors each having a terminal capable of controlling a substrate potential; a latch circuit including the MOS transistor; and a substrate potential switching means for controlling the substrate potential using the terminal. Characteristic semiconductor integrated circuit. 2. A semiconductor device comprising: two nMOS transistors each having a terminal capable of controlling a substrate potential of each pWELL; a latch circuit including the nMOS transistor; and a substrate potential switching means for controlling the substrate potential using the terminal. A semiconductor integrated circuit characterized by the above. 3. A semiconductor device comprising: two pMOS transistors each having a terminal capable of controlling the substrate potential of each nWELL; a latch circuit including the pMOS transistor; and a substrate potential switching means for controlling the substrate potential using the terminal. A semiconductor integrated circuit characterized by the above. 4. An nMOS transistor having a terminal capable of operating the substrate potential of pWELL, a pMOS transistor having a terminal capable of operating the substrate potential of nWELL, an inverter circuit including the pMOS transistor and the nMOS transistor, A semiconductor integrated circuit, comprising: a latch circuit using an inverter circuit; and substrate potential switching means for controlling a substrate potential using the terminal.