JPH09298299A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the circuit operation, without increasing the current consumption, by changing the threshold of a MOSFET such that this threshold is low, its gate is on, the threshold is high after a specified time const. elapsed, the gate is off, and the threshold returns to the original level after a specified time const. elapsed. SOLUTION: A laminate film having SiO2 films 4 on the upper and lower surfaces of a SiN film 5 beneath gate electrodes 1. In the case of an nMOS, the voltage applied to the gate electrode 1 is changed from L(low level) to H(high level) to flow a current between a source 2 and a drain 3 to trap electrons at an SiN film 5 interfaces between the oxide film 4 to raise the threshold enough according to the trapped amt. of the electrons after a specified time. While the gate is H, the threshold is kept high. When turning from H to L, the trapped electrons are discharged to return the threshold to original level. Since the threshold is different when turning on and off, the circuit operation can be performed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET), and more particularly to a semiconductor integrated circuit having a logic gate composed of a MOSFET.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, when the threshold value of a transistor is lowered, the operation timing is accelerated and the speed is increased, but on the other hand, a through current flows and the consumption current is increased. On the contrary, if the threshold value of the transistor is increased, the current consumption can be reduced, but the operation timing is delayed and the speed cannot be increased.

[0003]

As described above, conventionally, there has been a so-called trade-off relationship between the operation timing determined by the threshold value of the transistor and the current consumption. And in semiconductor integrated circuits, high speed is always required,
In the conventional MOS transistor and its logic gate, there is a problem that the current consumption increases only by lowering the threshold value.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit capable of speeding up circuit operation without increasing current consumption. Especially.

[0005]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure. That is, the present invention is a semiconductor integrated circuit having a logic gate composed of a MOSFET, wherein the MOSFET includes means for trapping electrons or holes, and a threshold value is set when the gate of the MOSFET is turned on. It is characterized in that the threshold value returns to the original low value when a predetermined time constant τ2 elapses after turning off and a current flows after a predetermined time constant τ1 after turning on. .

Here, preferred embodiments of the present invention include the following. (1) Time constants τ1, τ2 and input signal cycle T (= TH + T
L) should be τ1 << TH and τ2 << TL when the transistor is an nMOS transistor, and τ1 << TL and τ2 << TH when it is a pMOS transistor.
However, TH is the time when the input signal is "H" level, TL
Is the time when the input signal is at the “L” level, τ1 is the time until the threshold value of the transistor rises, and τ2 is the time until the threshold value of the transistor returns to the original value. (2) in at least one of the above nMOS and pMOS transistors, and an inverter gate oxide film by using a transistor which is stacked structure of SiN film and the SiO ₂ film, electrons or holes at the interface of the SiN film and the SiO ₂ film Be trapped. (3) A NAND gate is formed by using a transistor whose gate oxide film has a laminated structure of SiN and SiO ₂ for at least one of the nMOS and pMOS transistors. (4) A NOR gate is formed by using a transistor whose gate oxide film has a laminated structure of SiN and SiO ₂ for at least one of the nMOS and pMOS transistors. (5) An EXNOR gate is formed by using a transistor whose gate oxide film has a laminated structure of SiN and SiO ₂ for at least one of the nMOS and pMOS transistors. (6) A transfer gate is formed by using a transistor whose gate oxide film has a laminated structure of SiN and SiO ₂ for at least one of the nMOS and pMOS transistors. (Operation) According to the present invention, since the threshold value of the MOS transistor is low before it is turned on, the operation timing can be accelerated and increased in speed. Since the threshold value of the MOS transistor is high until the gate input is inverted after turning on, the current consumption can be reduced.
In other words, before turning on, the transistor with a low threshold is
A high-speed and low-current-consumption circuit can be realized by maintaining a high threshold value until the gate input is inverted after turning on.

As means for controlling the threshold value of the MOS transistor, the gate oxide film of the MOS transistor is made to have a laminated structure of SiN and SiO ₂ , specifically, between or below the SiO ₂ film as the gate oxide film. By providing the SiN film, it becomes possible to change the threshold value of the same MOS transistor before and after turning on as described above and before the gate input is inverted.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. (First Embodiment) FIGS. 1A and 1B are for explaining an inverter according to a first embodiment of the present invention. FIG. 1A is a circuit configuration diagram and FIG. 1B is an operation waveform diagram.

The inverter shown in FIG. 1A is an nMOS.
It is configured by connecting a transistor and a pMOS transistor in series. In this way, nMOS transistor and p
A circuit configuration itself in which MOS transistors are combined to form an inverter is conventionally known, but in the present embodiment, each transistor has an nMOS transistor as shown in FIG. A pMOS transistor is used as shown. The MOS transistor and the pMOS transistor differ from the MOS transistor forming a normal inverter in that a laminated film having a SiO ₂ film is provided below and above the SiN film under the gate electrode.

First, the operation of the transistor of FIG. 2 will be described. In FIG. 2, 1 is a gate electrode, 2 is a source, 3 is a drain, 4 is a SiO ₂ film, and 5 is a SiN film. Here, the operation of the nMOS transistor will be described as an example.

When the voltage applied to the gate electrode 1 changes from L (low level) to H (high level) to turn on the transistor, a current flows between the source and drain. At this time,
If there is a SiN film between the oxide films, electrons are trapped at the SiN film interface (FIG. 2A), and after a certain period of time τ1, the threshold value of the transistor is sufficiently high depending on the amount of trapped electrons. Become. The threshold value is kept high while the gate voltage is H. Next, when the gate voltage reverses from H to L, trapped electrons begin to be emitted, and after the reversal, the threshold value returns to the original value after a certain time constant τ2.

The time when the gate voltage is H (TH) is τ1
When it is sufficiently longer (τ1 << TH), the threshold value is sufficiently high by the time of inversion, and the transistor turns off quickly when the gate voltage changes from H → L. Further, when the time (TL) when the gate voltage is L is sufficiently longer than τ2 (τ2 << TL), the threshold value has completely returned to the original low value at the time of inversion, and the gate voltage changes from L to H. When doing, the transistor turns on quickly.

The same applies to pMOS transistors, in which case it is holes that are trapped (FIG. 2).
(B)). When the gate voltage changes from H to L and the transistor turns on, a current flows between the source and drain. The holes are trapped at the SiN interface, and the threshold value of the transistor becomes sufficiently high after a certain time τ1. The threshold value is kept high while the gate voltage is L. Next, when the gate voltage is inverted from L to H, the trapped holes begin to be emitted, and after the inversion, the emission threshold value returns to the original value after a certain time constant τ2.

The period (TL) in which the gate voltage is L is τ1
When it is sufficiently longer (τ1 << TL), the threshold value is sufficiently high by the time of inversion, and the transistor turns off quickly when the gate voltage changes from L → H. When the period when the gate voltage is H (TH) is sufficiently longer than τ2 (τ2 << TH), the threshold value completely returns to the original low value at the time of inversion, and the gate voltage changes from H to L. When doing, the transistor turns on quickly.

As described above, since the threshold value is different when the transistor is turned on and when it is turned off, the transistor is turned on quickly,
And it can be turned off quickly. The time constant τ can be controlled by the distance from the Si substrate to the interface between the SiN film and SiO ₂ . The longer this distance is, the longer τ becomes.

FIG. 1A shows an inverter composed of the above transistors, and its operation will be described with reference to the operation waveform of FIG. 1B. For comparison, operation waveforms in the conventional inverter are shown in FIG.

The input potential of the inverter is Vin and the output potential is Vout. Vin rises from L to H, and nMOS
When the threshold value Vthn of the transistor is exceeded, the nMOS transistor is turned on and Vout becomes H → L. After this, Vthn is sufficiently high after a certain time τ1 (Vth <Vthn ').

Next, Vin starts to fall from H to L, and pMO
When the threshold value Vthp of the S transistor is exceeded, the pMOS transistor is turned on and Vout becomes L → H. At this time, both nMOS and pMOS transistors are turned on.
However, although there is a time during which a through current flows, the threshold value of the nMOS transistor is high, so when Vin becomes lower than Vthn ', the nMOS transistor turns off at a timing faster than before.

Therefore, both pMOS and nMOS are turned on.
The operating time is shorter than before and the inverter turns on.
Although OFF is high speed, it requires less through current.
Next, the same applies when Vin rises from L to H.
Since τ2 has passed and the threshold value of the nMOS transistor has returned to the original low value Vthn, when Vin exceeds Vthn, the nMOS transistor turns on and Vout becomes H → L. After τ1, Vthn remains high (Vth <Vthn ') until the gate is inverted again.

On the other hand, the threshold value of the pMOS transistor is high (│Vthp │ <│Vthp'│), so Vin
Exceeds Vcc- | Vthp '|, the pMOS transistor is turned off at a faster timing than before.

Therefore, both pMOS and nMOS are turned on.
The operating time is shorter than before and the inverter turns on.
Although OFF is high speed, it requires less through current.
The threshold value of the pMOS transistor returns to the original low value after τ2 after the gate voltage is inverted, so that the pMOS transistor is turned on quickly when the gate potential is next inverted from H → L.

The longer the distance from the Si substrate to the interface between the SiN film and the SiO ₂ film, the longer τ1 and τ2. By changing this distance, it is possible to set optimal τ1 and τ2 at high speed and with a small through current.

The relationship between the input signal to the circuit and τ1 and τ2 is shown in FIG. The time from the rise of the input signal to the fall is TH, the time from the fall to the rise is TL, and the cycle is T (TH + TL). The nMOS transistor is ON during the period of TH, but it is nM at high speed.
In order for the OS transistor to turn off, the threshold value must be high before the input becomes L.

Next, after the input is changed from H to L and the nMOS transistor is turned off, the trapped electrons of the nMOS transistor are emitted and T is input until the input becomes H again.
Within the time L, the threshold must return to its original low value. Therefore, in the case of an nMOS transistor, τ2 <<
Must be TL.

The same applies to the pMOS transistor. During the period of TH, the pMOS transistor is off, but in order to turn on the pMOS transistor at high speed, trapped holes are released until the input becomes L, and the threshold value returns to the original low value. There must be. Therefore, in case of pMOS transistor, τ2 << TH
Must.

Next, when the input changes from H to L, the pMOS transistor turns on, but in order to turn off the pMOS transistor at high speed, the threshold value becomes high within the time TL until the input becomes high again. Must be Therefore, in the case of a pMOS transistor, τ1 << TL must be satisfied. (Second Embodiment) Next, a second embodiment of the present invention will be described.

In this embodiment, the structure of the MOS transistor is as shown in FIGS. 4 (a) and 4 (b). That is, in the first embodiment, in the MOS transistor forming the circuit, the SiN film 5 is not sandwiched between the SiO ₂ films 4, but the SiN film 5 is attached below the SiO ₂ film 4.

Even in this case, electrons or holes are trapped at the interface between the SiN film and the SiO ₂ film, the operation of the transistor and the circuit is the same as in the first embodiment, and a high speed transistor can be realized.

Further, the same operation and effect as those of the first embodiment can be expected in an inverter using this transistor and other logic circuits. That is, it is possible to obtain a circuit which can be turned on and off at high speed and has a small through current. (Third Embodiment) FIG. 5 is for explaining a two-input NAND gate according to a third embodiment of the present invention.
(A) is a circuit block diagram and (b) is an operation waveform diagram.

Two pMOS transistors P1 and P2 are connected in parallel, and two nMOS transistors N are connected to this.
1, N2 are connected in series, and the gates of P1 and N1 and the gates of P2 and N2 are commonly connected. The circuit configuration is the same as the conventional one, but in the present embodiment, the transistor shown in FIG. 2 or 4 is used as part of the four transistors.

The input potentials of the NAND gate thus constructed are Vin1 and Vin2, and the output potential is Vout. Now, from the state of Vin1 = H, Vin2 = L, Vout = H,
Considering the case where Vin2 rises to H and Vout changes to L, when the input Vin2 goes from L to H, the n2 nMOS transistor which is initially off is turned on. N2 is the first
The transistor of the above embodiment has a low threshold value, and therefore is turned on at high speed.

On the other hand, Vin2 was input to the gate of P2
Turns off. As a result, the output Vout drops from H to L at high speed. Next, when Vin2 goes from H to L, N2 becomes OF
F Here, since the threshold value of N2 is high after τ1 after turning on, it turns off faster than before. On the other hand, since P2 has passed τ2 hours or more, the threshold value has returned to a low value. Therefore, P2 turns on quickly, and as a result, Vout changes from L to H at high speed. Further, since N2 is turned off quickly, the through current is small.

The above is exactly the same even when Vin1 changes, and the same effect can be obtained when both Vin1 and Vin2 change at the same time. Further, although the present embodiment shows the case of two inputs, the same is true for three or more inputs.

By changing the distance from the Si substrate to the interface between the SiN film and SiO ₂ , it is possible to set the optimum values of τ1 and τ2 at a high speed and with a small through current. This value is nM
For OS transistors, τ1 << TL and τ2 << TH, pM
In the OS transistor, τ2 << TL and τ1 << TH may be satisfied. (Fourth Embodiment) FIG. 6 illustrates a 2-input NOR gate according to a fourth embodiment of the present invention.
(A) is a circuit block diagram and (b) is an operation waveform diagram.

Two nMOS transistors N1 and N2 are connected in parallel, and two pMOS transistors P are connected to this.
1 and P2 are connected in series, and the gates of P1 and N1 and the gates of P2 and N2 are commonly connected. The circuit configuration is the same as the conventional one, but in the present embodiment, the transistor shown in FIG. 2 or 4 is used as part of the four transistors.

The input potentials of the NOR gate thus constructed are Vin1 and Vin2, and the output potential is Vout. Now, from the state of Vin1 = L, Vin2 = L, Vout = H,
Considering the case where Vin2 rises to H and Vout changes to L, when the input Vin2 goes from L to H, the n2 nMOS transistor which is initially off is turned on. N2 is the first
The transistor of the above embodiment has a low threshold value, and therefore is turned on at high speed.

On the other hand, Vin2 was input to the gate of P2
Turns off. As a result, the output Vout drops from H to L at high speed. Next, when Vin2 goes from H to L, N2 becomes OF
F Here, since N2 has a high threshold value after τ1 after turning ON, it turns OFF faster than before. On the other hand, since P2 has passed τ2 hours or more, the threshold value has returned to a low value. Therefore, P2 turns on quickly, and as a result, Vout changes from L to H at high speed. Further, since N2 is turned off quickly, the through current is small.

The above is exactly the same even when Vin1 changes, and the same effect can be obtained when both Vin1 and Vin2 change at the same time. Further, although the present embodiment shows the case of two inputs, the same is true for three or more inputs.

By changing the distance from the Si substrate to the interface between the SiN film and SiO ₂ , it is possible to set the optimum values of τ1 and τ2 at high speed and with a small through current. This value is nM
For OS transistors, τ1 << TL and τ2 << TH, pM
In the OS transistor, τ2 << TL and τ1 << TH may be satisfied. (Fifth Embodiment) FIG. 7 is a circuit configuration diagram showing a transfer gate according to a fifth embodiment of the present invention.

The pMOS transistor and the nMOS transistor are connected in parallel, and signals inverted to each other are input to the respective gates. This circuit is A · when the signal φ is H.
B is electrically connected, and L is electrically disconnected.

When the time when the signal φ is H is TH, the time when the signal φ is L is TL, and the period is T (= TH + TL), then nM
For OS transistors, τ1 << TH and τ2 << TL
, PMOS transistors have τ2 << TH and τ
If 1 << TL, both the nMOS and pMOS have a low threshold value when ON, and turn OFF when the threshold value is high. Therefore, high-speed switching is possible. (Sixth Embodiment) FIG. 8 is a schematic diagram for explaining an EXNOR gate according to a sixth embodiment of the present invention.
(A) is a circuit block diagram and (b) is an operation waveform diagram. This circuit is composed of four NANDs 1 to 4, and outputs "0" when the two inputs are equal and outputs "1" when they are not equal.

The input potentials of the EXNOR gates are Vin1, V
The output of NAND1 is Vout1, the output of NAND2 is Vout2, the output of NAND3 is Vout3, and the output of NAND4 is Vout.

Now, Vin1 = L, Vin2 = L, Vout =
Considering the case where Vin2 rises to H and Vout changes to H from the state of L, when the input Vin2 changes from L → H, Vout1
Remains H, but the transistors that make up NAND1 are turned on and off at high speed as in the case of the third embodiment.
I do.

On the other hand, since the input of NAND2 does not change, Vout2 also maintains H. When the input Vin2 of the NAND3 changes from L to H, the pMOS transistor to which Vin2 is input is turned off and the nMOS transistor is turned on. Since this pMOS transistor has a high threshold value after it is turned on, it turns off at a high speed.
Since the S-transistor has been turned off, the threshold value has returned to a low value and is turned on at high speed.

One input of NAND4, Vout3 is H
→ L, and the other input Vout2 remains H, so the output Vout changes from L → H. As Vout3 changes from H to L, the pMOS transistor to which Vout3 is input is turned on and the nMOS transistor is turned off.
Since this pMOS transistor has its threshold value returned to its original low value when turned off, it turns on at a high speed. Since the nMOS transistor is turned on, the threshold value is high, and the nMOS transistor is turned off at high speed. Therefore, Vout changes rapidly, and the transistor that turns off turns off at a fast timing.
Therefore, the through current is small. Therefore, it is possible to realize a high-speed circuit with a small through current.

By changing the distance from the Si substrate to the interface between the SiN film and SiO ₂ , it is possible to set the optimum values of τ1 and τ2 at a high speed and with a small through current. This value is nM
For OS transistors, τ1 << TL and τ2 << TH, pM
In the OS transistor, τ2 << TL and τ1 << TH may be satisfied.

The above is exactly the same when Vin2 changes from H to L, and when Vin1 changes.
The same effect can be obtained when both in1 and Vin2 change at the same time.

In the present invention, the transistor forming the circuit is not limited to the transistor whose gate oxide film has a laminated structure of SiO ₂ and SiN. For example, instead of trapping electrons (or holes) at the interface between the SiO ₂ film and the SiN film, a conductive film (preferably the same material as the gate electrode) such as polysilicon may be provided. Also,
The circuit is not limited to the description of the embodiment.

A circuit composed of transistors having a low threshold value when turned on and a high threshold value when turned off.
1, τ2 and the input signal cycle are τ1 << TH and τ2 << TL for nMOS transistors and τ2 << TH and τ1 << TL for pMOS transistors, the same effect is expected in any element and circuit. it can.

For example, in a basic circuit, a flip-flop, a pulse generator, a clock generator, etc.
It can also be applied to multipliers and adders. Alternatively, in the memory, a NAND that constitutes an address decoding circuit
Application to gates is also effective. In addition, various modifications can be made without departing from the scope of the present invention.

[0051]

As described in detail above, according to the present invention, O
By configuring a logic circuit with a transistor having a low threshold value at N and a high threshold value at OFF, the circuit operation can be speeded up without increasing current consumption. In particular, τ1 (time until the threshold value of the transistor rises), τ2 (time until the threshold value of the transistor returns to the original value) and the cycle of the input signal are τ1 << TH and τ2 for the nMOS transistor. By setting τ2 << TH and τ1 << TL for << TL and pMOS transistors, it is possible to realize a high-speed circuit with a small through current.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram and an operation waveform diagram of an inverter according to a first embodiment.

FIG. 2 is an nMOS and pMOS used in the first embodiment.
FIG. 6 illustrates a structure of a transistor.

FIG. 3 is a diagram showing a relationship between a cycle of an input signal of the logic circuit and time constants τ1 and τ2 in the first embodiment.

FIG. 4 is an nMOS and pMOS used in the second embodiment.
FIG. 6 illustrates a structure of a transistor.

FIG. 5 is an equivalent circuit diagram and operation waveform diagram of a 2-input NAND gate according to the third embodiment.

FIG. 6 is an equivalent circuit diagram and an operation waveform diagram of a 2-input NOR gate according to the fourth embodiment.

FIG. 7 is an equivalent circuit diagram showing a transfer gate according to a fifth embodiment.

FIG. 8 is an equivalent circuit diagram and an operation waveform diagram of an EXOR gate according to the sixth embodiment.

FIG. 9 is an operation waveform diagram of a conventional inverter.

[Explanation of symbols]

1 ... gate 2 ... source 3 ... drain 4 ... SiO ₂ film 5 ... SiN film N1, N2 ... nMOS transistors P1, P2 ... pMOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/788 29/792

Claims (4)

[Claims] 1. A semiconductor integrated circuit having a logic gate composed of a MOSFET, wherein the MOSFET includes means for trapping electrons or holes, and when the gate of the MOSFET turns on, the threshold value is low, Then, after the current flows, the threshold value becomes high after passing a predetermined time constant τ1, and after turning off, a predetermined time constant τ2.
The semiconductor integrated circuit is characterized in that the threshold value returns to the original low value when is elapsed. 2. The time constants τ1 and τ2 and the period T of the input signal.
The relation with (= TH + TL) is that the transistor is nM
In the case of the OS transistor, τ1 << TH and τ2 << TL, and in the case of the pMOS transistor, τ1 << TL and τ2 <<.
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is TH. Where TH is the time when the input signal is at "H" level, TL is the time when the input signal is at "L" level, τ1 is the time until the threshold value of the transistor rises, and τ2 is the threshold value of the transistor. It is the time to return to the original value. 3. A logic gate is formed by using a transistor having a laminated structure of a SiN film and a SiO ₂ film as a gate oxide film for at least one of the nMOS transistor and the pMOS transistor according to claim 2, and the logic gate is formed.
A semiconductor integrated circuit characterized in that electrons or holes are trapped at the interface between _two films. 4. The logic gate is an inverter or a NAND.
4. The semiconductor integrated circuit according to claim 3, which is a gate, a NOR gate, an EXOR gate, or a transfer gate.