JP2001135908A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board where needlessly long wiring nor multilayer for the entire wiring board will not be required. SOLUTION: A semiconductor device 22 comprising a plurality of electrodes 42 is mounted on a wiring board 110. Here, a plurality of external electrodes 43 connected to the plurality of electrodes 42, a first wiring board 24 comprising a plurality of first mutual connections 46, and a second wiring board 26, which is provided so as to face the first wiring board 24, comprises a second mutual connection 44, are provided. The second mutual connection 26 is connected electrically to at least one of the external electrodes 43 in a mounting region, where a two-dimensional range is formed by a region where the plurality of external electrodes 43 are formed while being electrically connected to at least one of the first mutual connections 46 outside the mounting region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board,
In particular, the present invention relates to a wiring board on which a semiconductor device having a large number of electrodes is mounted.

[0002]

2. Description of the Related Art In recent years, in order to reduce the size and weight of electronic devices, semiconductor devices in which all functions of the system are integrated on a single chip, so-called system LSIs, have been actively developed. Further, as the functions of system LSIs have been improved, the size of chips and the number of terminal electrodes have been increasing. Various types of packages have been developed with the increase in the size and the number of electrodes of the semiconductor device. Note that in this specification, a terminal electrode of a semiconductor device is simply referred to as an “electrode”.

A semiconductor device having about 200 electrodes has a QFP (Quad Flat Pa) which can be realized at low cost.
Cage) is generally adopted, and a device in which the electrode pitch is narrowed down to about 0.3 mm in response to the increase in size of a chip is currently realized. However, in consideration of ease of mounting and reliability, it is difficult to further narrow the pitch in the QFP.

In a semiconductor device having more than 300 electrodes,
PGA (Pin Grid Array) in which electrodes are arranged in a grid array (lattice form) on the lower surface of the package
y), BGA (Ball Grid Array) or CSP (Chip Size Package) is adopted. PGA is mounted by inserting electrodes (pins) into holes penetrating a wiring board (printed board), so the electrode pitch is wider than BGA or CSP, and is 2.54 mm.
Is common. For a large-scale semiconductor device having more than 400 electrodes, BGA or CSP capable of further narrowing the electrode pitch is adopted, and standardization has been advanced in recent years. 1.27 mm for BGA electrode pitch
However, the CSP electrode pitch is generally 0.8 mm. Further, as an arrangement form of the electrodes, for example, one in which four or five rows of electrodes are arranged from the vicinity of the outer periphery of the lower surface of the package toward the center, or one in which the electrodes are spread all over the lower surface of the package Is being developed. In this specification, “PGA” and “CSP” are:
A package or a semiconductor device having such a package.

[0005]

A semiconductor device in which electrodes are arranged in a grid array at a high density, especially a BGA or CS
In the case of mounting a semiconductor device having a narrow electrode pitch such as P, a two-dimensional region defined by a region where external electrodes connected to the electrodes of the semiconductor device are formed is projected onto a region of the wiring board ( Hereinafter, it is referred to as “mounting area”.)
The wiring density inside and around is higher than in other regions, and it is difficult to draw out the wiring. In particular, it becomes more difficult for the external electrodes closer to the center of the mounting area to draw out the wiring electrically connected to the external electrodes. For example, when the electrode pitch is smaller than 1.27 mm, only one wiring may be drawn between adjacent external electrodes during pattern design.

Therefore, a method of forming a wiring so as to bypass a region having a high wiring density or increasing the number of wiring layers of a wiring board to draw out the wiring is generally performed.

However, if the wiring is formed so as to bypass the wiring, the wiring length becomes longer, and there is a problem that the signal transmission time becomes longer. Further, when the number of wiring layers of the wiring substrate is increased, the entire substrate is multi-layered for a part of the wiring substrate, so that there is a problem that useless wiring layers are formed and the manufacturing cost increases.

Japanese Patent Laid-Open Publication No. Hei 10-135378 discloses a technique for preventing the concentration of wiring in the mounting area of the wiring board by increasing the electrode pitch of the electrode closer to the outer periphery of the package. . However, since this technique requires a package having a special electrode arrangement, it cannot be applied to a general-purpose general-purpose package (semiconductor device) having electrodes arranged at a constant pitch.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in view of the above circumstances. An object of the present invention is to provide a wiring board which does not require the formation of an unnecessarily long wiring or the multilayering of the entire wiring board. Another object of the present invention is to provide a wiring board that can operate a semiconductor device electrically stably and whose specifications can be easily changed.

[0010]

A wiring board according to a first aspect of the present invention is a wiring board on which a semiconductor device having a plurality of electrodes is mounted, and is connected to the plurality of electrodes of the semiconductor device. A plurality of external electrodes, a first wiring board having a plurality of first interconnects, and a second wiring board disposed to face the first wiring board and having a second interconnect, The second interconnect is electrically connected to at least one external electrode of the plurality of external electrodes in a mounting area in which a two-dimensional range is defined by a region in which the plurality of external electrodes are formed. And, outside the mounting area, electrically connected to at least one first interconnect of the plurality of first interconnects;
Thereby, the above object is achieved.

[0011] At least one other first interconnect of the plurality of first interconnects is electrically connected to at least one other external electrode of the plurality of external electrodes in the mounting area. May be.

[0012] The plurality of external electrodes are formed on an upper surface of the second wiring substrate, and the first wiring substrate is arranged such that an upper surface of the first wiring substrate faces a lower surface of the second wiring substrate. It may be arranged.

[0013] The plurality of external electrodes are formed on an upper surface of the first wiring substrate, and the second wiring substrate is formed such that an upper surface of the second wiring substrate faces a lower surface of the first wiring substrate. It may be arranged.

The second interconnect is connected via a via hole penetrating from the upper surface of the first wiring board to the lower surface.
It may be electrically connected to the at least one external electrode.

The second wiring board further has another external electrode for electrically connecting to an electrode of another semiconductor device, and the other external electrode is at least one of the plurality of external electrodes. Preferably, they are electrically connected to one another.

At least one of the first wiring board and the second wiring board has a ground layer having a ground pattern electrically connected to at least one of the plurality of external electrodes, and the plurality of external electrodes. At least one of a power supply layer having a power supply pattern electrically connected to at least one of the power supply layers.

The first wiring substrate has a plurality of first connection electrodes provided on the lower surface and electrically connected to the plurality of first interconnections, and the second wiring substrate has a structure on the upper surface. A plurality of second connection electrodes that are provided and electrically connected to the second interconnect, and electrically connect the via hole and the second interconnect in the mounting area and outside the mounting area. An electrical connection between the second interconnect and the at least one first interconnect is a conductive connection selectively provided between the plurality of first connection electrodes and the plurality of second connection electrodes. It is preferably performed via a member.

It is preferable that the conductive connecting member is made of conductive rubber.

A wiring board according to a second aspect of the present invention is a wiring board on which a semiconductor device having a plurality of electrodes is mounted, wherein the first multilayer wiring structure having a plurality of first interconnects and the first multilayer wiring structure are provided. A plurality of external electrodes connected to the plurality of electrodes of the semiconductor device formed on an upper surface of the multilayer wiring structure, and a second interconnect provided in contact with a part of the lower surface of the first multilayer wiring structure; A second wiring structure, wherein the second interconnect has at least one of the plurality of external electrodes in a mounting region in which a two-dimensional range is defined by a region where the plurality of external electrodes are formed. Electrically connected to one external electrode, and electrically connected to at least one first interconnect of the plurality of first interconnects outside the mounting area, thereby achieving the above object. Achieved That.

It is preferable that the device further comprises a heat conductive member provided in the mounting area, and is joined to the heat radiating member via the heat conductive member.

A wiring board according to a third aspect of the present invention is a wiring board on which a semiconductor device having a plurality of electrodes is mounted, and a plurality of external electrodes connected to the plurality of electrodes of the semiconductor device; Each of the plurality of wiring layers includes a plurality of wiring layers electrically connected to at least one of the plurality of external electrodes via via holes, and the plurality of wiring layers includes a power supply layer having a power supply pattern and a ground pattern. Having at least one of the ground layers having the number of the via holes formed through at least one of the power layer and the ground layer, The number of the via holes formed without penetrating at least one of them is smaller than that, thereby achieving the above object.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, components having substantially the same function are denoted by the same reference numeral for simplicity.

(Embodiment 1) A wiring board (mounting board) 110 of Embodiment 1 will be described with reference to FIG.

FIG. 1 shows a semiconductor device (semiconductor component) 2 having a plurality of electrodes (terminal electrodes) 42 arranged in an array.
FIG. 4 is a cross-sectional view schematically illustrating a wiring board 110 on which a wiring board 2 is mounted. The semiconductor device 22 is, for example, a BGA.

The wiring substrate 110 includes a first wiring substrate (main wiring substrate) 24 having a plurality of wirings and via holes (first interconnections) 46 and a second wiring substrate (sub-wiring) having wirings (second interconnections) 44. Wiring board or daughter board) 26. The first wiring board 24 and the second wiring board 26 are formed separately. Plural electrodes 4 of semiconductor device 22
A plurality of lands (external electrodes) 43 connected to 2 are formed on the upper surface (mounting surface) 24 a of the first wiring board 24.
The second wiring board 26 has an upper surface 26a that is the first wiring board.
In order to face the lower surface (back surface) 24b of the wiring board 24,
The first wiring board 24 is arranged without being in contact with the lower surface 24b. The second interconnect 44 is connected to the external electrode 43 via the connection member 28 in a mounting area where a two-dimensional range is defined by a region where the external electrode 43 connected to the electrode 42 of the semiconductor device 22 is formed. Electrically connected,
In addition, outside the mounting area, the first
It is electrically connected to the interconnect 46.

The term "interconnect" refers to a component that conducts electricity and includes wiring and via holes (inner vias, vias or through holes).

As described above, in the wiring board 110, the external electrode 43 and the first interconnect 46 formed outside the mounting area are connected to the second interconnect 44 extending from the inside of the mounting area to the outside of the mounting area. Are electrically connected via That is, by providing the second interconnect 44, the region of the first wiring board 24 located below the electrode group 112 of the semiconductor device 22 can be bypassed. Second wiring board 2
The external electrodes 43 connected to the first interconnects 46 formed outside the mounting region of the first wiring board 24 via the second interconnects 44 formed in the first wiring board 24 are not limited to the example shown in FIG. The external electrode 43 may be connected to a plurality of first interconnects 46 outside the mounting area via a plurality of second interconnects. At this time, among the plurality of external electrodes 43, as the external electrode 43 is located inside the mounting area, the area that can be detoured by using the second interconnect 44 becomes wider, so that the wiring density in the mounting area of the first wiring board 24 is reduced. The effect of lowering is large. As described above, when the wiring substrate 110 according to the present invention is used, even in a general-purpose semiconductor device 22 (for example, a BGA) having the electrodes 42 arranged at high density in a grid array at a constant pitch, the mounting area and its periphery Can be efficiently reduced.

The wiring connected to the external electrode 43 is drawn out of the mounting area through the second interconnect 44 formed on the second wiring board 26, so that the wiring is electrically connected to the electrode group 112. The length of the wiring can be reduced as compared with the case where the wiring group (not shown) formed on the one wiring substrate 24 is bypassed in the first wiring substrate 24. Therefore, even today, when the processing speed of the arithmetic element is increased beyond 100 MHz,
The problem that the operation speed of a signal is reduced due to the long wiring can be avoided.

Further, the second wiring board 26 may be selectively provided at a place where a bypass by the second interconnect 44 is required, and it is not necessary to make the entire first wiring board 24 multilayer. That is, only by providing the required minimum size of the second wiring board 26, the wiring board 110 having the same function as that obtained by multilayering the entire first wiring board 24 can be obtained. Therefore, the wiring board 110 can be manufactured at a lower cost than the multilayered first wiring board 24. Further, the specifications of the wiring board 110 can be changed only by changing the configuration of the second wiring board 24. Although FIG. 1 shows one wiring 44 extending from the inside of the mounting area to outside of the mounting area as the second interconnect 44, the present invention is not limited to this, and the external electrode may be connected via an arbitrary number of wirings and via holes. 43 may be connected to a first interconnect 46 outside the mounting area.

Next, referring to FIG. 2, a description will be given of a wiring board 120 which is a more specific version of the wiring board 110 of the present embodiment.

FIG. 2 shows the semiconductor device 22 and the connector 136.
FIG. 5 is a cross-sectional view showing a wiring board 120 on which the components are mounted.

The wiring board 120 includes a four-layer printed board 124 as a first wiring board, a two-layer printed board 126 as a second wiring board, and conductive connecting members 128 and 1.
29. The four-layer printed board 124 and the two-layer printed board 126 are fixed to each other by screws 137. Lands (first connection electrodes) 121 and 123 as connection members are formed on the lower surface 124b of the four-layer printed circuit board 124, and lands (second connection electrodes) 132 and 1 are formed on the upper surface 126a of the two-layer printed circuit board 126.
33 are formed. A conductive connection member 129 is disposed between the first connection electrode 121 and the second connection electrode 133, and a conductive connection member 128 is disposed between the first connection electrode 123 and the second connection electrode 132. Is clamped between them by the tightening force.

The four-layer printed circuit board 124 includes the connector 13
A first wiring 146 as a first interconnect electrically connected to the first wiring 6 and an upper surface 124a, each of which is electrically connected to one of the plurality of electrodes 42 of the semiconductor device 22 by soldering. And a plurality of external electrodes 43
It has connection electrodes 121 and 123 and via holes 125 and 122. The via hole 122 penetrates from the upper surface 124a to the lower surface 124b of the four-layer printed circuit board 124, and electrically connects the external electrode 43 and the first connection electrode 123. The via hole 125 electrically connects the first wiring 146 and the first connection electrode 121.

The two-layer printed circuit board 126 has a second wiring 144 as a second interconnect, second connection electrodes 132 and 133, and via holes 101 and 102. The second connection electrodes 132 and 133 are formed on the upper surface 126a of the two-layer printed board 126, and the first connection electrodes
23 and 121 are disposed respectively. The via hole 101 electrically connects the second wiring 144 to the second connection electrode 132, and the via hole 102
The wiring 144 and the second connection electrode 133 are electrically connected.

The first connection electrode 123 and the second connection electrode 132
Between the first connection electrode 121 and the second connection electrode 133
The conductive connection members 128 and 129 sandwiched between the first and second connection electrodes are electrically connected to the first connection electrode 123 and the second connection electrode 132, for example. By using the conductive connecting members 128 and 129 formed of conductive rubber, a stable electric connection can be obtained by the mechanical tightening force of the screw 137, and
There is an advantage that the connection can be easily redone. Of course, other conductive materials may be used.

The via hole 122, the first connection electrode 123,
The conductive connection member 128, the second connection electrode 132, and the via hole 101 are formed in the mounting area. On the other hand, the via hole 125, the first connection electrode 121, the conductive connection member 1
29, the second connection electrode 133 and the via hole 102 are formed outside the mounting region. The second wiring 144 (second interconnection) of the two-layer printed circuit board 126 has a via hole 101, a second connection electrode 132, a conductive connection member 128, a first connection electrode 123, and a via hole 12 in the mounting area.
2, the via hole 102 and the second connection electrode 1 outside the mounting region.
33, the conductive connection member 129, the first connection electrode 121, and the via hole 125 are electrically connected to the first wiring 146 (first interconnection) of the four-layer printed circuit board 124.

As described above, by electrically connecting the external electrode 43 and the first wiring 146 via the second wiring 144, the four-layer printed circuit board 124 located below the electrode group 112 of the semiconductor device 22 is formed. Area can be bypassed. As described above, when the wiring board 120 according to the present invention is used, even in the general-purpose semiconductor device 22 having the electrodes 42 arranged at high density in a grid array at a constant pitch, the wiring density in the mounting area and the periphery thereof is reduced. It can be reduced efficiently.

The number and position of the external electrodes 43 electrically connected to the second interconnect 144 among the external electrodes 43 are appropriately selected according to the mounting area of the first wiring board 124.
When the external electrode 43 inside the mounting area among the plurality of external electrodes 43 is connected to the second wiring 144, the area that can be bypassed becomes wider, so that the wiring density in the mounting area of the four-layer printed circuit board 124 is reduced. Great effect. Also, the second
The interconnect 144 is formed on the upper surface 124 a of the first wiring board 124.
Electrically connected to the external electrode 43 via the via hole 122 penetrating through the lower surface 124b from the bottom, the wiring density in the mounting region can be effectively suppressed.

The wiring connected to the external electrode 43 is drawn out of the mounting area via the second wiring 144 formed on the second wiring board 126, and is electrically connected to the electrode group 112, and is connected to the first wiring. Rather than bypassing a wiring group (not shown) formed on the substrate 124 in the first wiring substrate 124,
The length of the wiring can be reduced. Therefore, it is possible to avoid the problem that the operation speed of the signal is reduced due to the long wiring.

Further, the two-layer printed circuit board 126 is
What is necessary is just to selectively provide in the place where the bypass by the wiring 144 is needed, and it is not necessary to make the whole 1st wiring board 124 multilayer. That is, the printed circuit board may be locally formed in a pseudo multilayer. Therefore, the wiring substrate 120 is
The wiring board 124 can be manufactured at a lower cost than a multilayer board.

Further, a four-layer printed circuit board (first wiring board)
Reference numeral 124 further includes a ground layer 161 and a power supply layer 163. The ground layer 161 includes a plurality of external electrodes 4.
3 has a ground pattern electrically connected to at least one of them. The power supply layer 163 has a power supply pattern electrically connected to at least one of the plurality of external electrodes 43. The ground pattern and the power supply pattern may be formed on the entire surface of the ground layer 161 and the power supply layer 163, respectively.

The ground pattern and the power supply pattern
Since it serves as a kind of capacitor, it serves as a local and temporary supply source of current consumed inside the semiconductor device 22. Therefore, the semiconductor device 22 can be electrically operated stably by the ground pattern and the power supply pattern. A large pattern (a ground pattern or a power supply pattern) functions like a capacitor having a large capacitance, and a small pattern functions like a capacitor having a small capacitance.

Four-layer printed circuit board (first wiring board) 124
Not limited to this, the two-layer printed board (second wiring board) may further include a ground layer and a power supply layer. In general, the ground electrode and the power supply electrode of the semiconductor device 22 are often provided on the innermost side of the package. Therefore, it is preferable that these electrodes be led out of the mounting area via the second interconnect. Note that the ground pattern is a conductor pattern for making the potential of electrically connected members equal to the potential of the ground and preventing an excessive current from flowing into the semiconductor device.

As described in the fifth embodiment, it is preferable that the number of via holes penetrating the ground pattern and the power supply pattern be as small as possible from the viewpoint of the stability of electrical connection. Therefore, it is preferable that the ground layer and the power supply layer are formed below the wiring board (a wiring layer far from the mounting surface).

The first wiring board and the second wiring board can be independently manufactured by a known wiring board manufacturing method.

(Embodiment 2) In the following embodiments, differences from Embodiment 1 will be mainly described, and description of points common to Embodiment 1 will be simplified or omitted.

The wiring board according to the second embodiment has an external electrode formed on the upper surface of the first wiring substrate in that external electrodes connected to a plurality of electrodes of the semiconductor device are formed on the upper surface of the second wiring substrate. This is mainly different from the wiring board of the first embodiment.

The wiring board 130 according to the second embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view schematically showing a wiring board 130 on which the semiconductor device 22 having a plurality of electrodes 42 arranged in an array is mounted.

A plurality of external electrodes 43 connected to the plurality of electrodes 42 of the semiconductor device 22 are formed on the upper surface 26 a of the second wiring board (sub wiring board or child board) 26. The second wiring board 26 includes a first wiring board (main wiring board) 2
4 is arranged so as to face the lower surface 26b of the second wiring substrate 26 without contacting the upper surface 24a of the first wiring substrate 24. The second interconnect 44 is electrically connected to the external electrode 43 inside the mounting area, and is electrically connected to the first interconnect 46 via a connecting member outside the mounting area.

A plurality of connection terminals 188 are interposed between the first wiring board 24 and the second wiring board 26. The external electrodes 43 other than the external electrodes 43 electrically connected to the second interconnect 44 are electrically connected to wiring (not shown) formed on the second wiring board 24 via the connection terminals 188. ing.

As described above, in the wiring board 130, the external electrode 43 and the first interconnect 46 formed outside the mounting area are connected to the second interconnect 44 extending from inside the mounting area to outside the mounting area. Are electrically connected via That is, by providing the second interconnect 44, the region of the first wiring board 24 located below the electrode group 112 of the semiconductor device 22 can be bypassed. Second wiring board 2
The external electrodes 43 connected to the first interconnects 46 formed outside the mounting region of the first wiring board 24 via the second interconnects 44 formed in the first wiring board 24 are not limited to the example shown in FIG. The external electrode 43 may be connected to a plurality of first interconnects 46 outside the mounting area via a plurality of second interconnects. As described above, when the wiring substrate 130 according to the present invention is used, the electrodes 42 arranged at high density in a grid array at a constant pitch are used.
The general-purpose semiconductor device 22 (e.g., BGA) having the above configuration can efficiently reduce the wiring density in the mounting area of the first wiring board 24 and the periphery thereof. The fact that the wiring density of the mounting area of the first wiring board 24 and the surrounding area is reduced is also evident from the fact that the number of the connection terminals 188 is smaller than the number of the external electrodes 43.

The wiring connected to the external electrode 43 is drawn out of the mounting area via the second interconnect 44 formed on the second wiring board 26, so that the wiring is electrically connected to the electrode group 112. The length of the wiring can be reduced as compared with the case where the wiring group (not shown) formed on the one wiring substrate 24 is bypassed in the first wiring substrate 24. Therefore, even today, when the processing speed of the arithmetic element is increased beyond 100 MHz,
The problem that the operation speed of a signal is reduced due to the long wiring can be avoided.

Further, the second wiring board 26 may be selectively provided at a place where a bypass by the second interconnect 44 is required, and it is not necessary to make the entire first wiring board 24 multilayer. That is, only by providing the required second size wiring board 26 of the minimum size, it is possible to obtain the wiring board 130 exhibiting the same function as the multilayered first wiring board 24 as a whole. Therefore, the wiring board 130 can be manufactured at a lower cost than the multilayered first wiring board 24 as a whole. Further, the specifications of the wiring board 130 can be changed only by changing the configuration of the second wiring board 24. Although FIG. 3 shows one wiring 44 extending from the inside of the mounting area to outside of the mounting area as the second interconnect 44, the present invention is not limited to this, and the external electrode may be connected via an arbitrary number of wirings and via holes. 43 may be connected to a first interconnect 46 outside the mounting area.

Instead of the second wiring substrate 26, a second wiring substrate 26 'shown in FIG. 4 can be used. FIG. 4 is a sectional view showing a second wiring board 26 'on which the semiconductor device 22 and another semiconductor device 23 are mounted.

The second wiring board 26 'is connected to another semiconductor device 2'.
Other external electrodes 41 for electrically connecting to the third electrode 23a, via holes 104 and 105, and wiring 145.
And further. The via hole 104 electrically connects the external electrode 41 and the wiring 145. The via hole 105 is connected to one of the plurality of external electrodes 43 and the wiring 1
45 is electrically connected. That is, the external electrode 4
Numeral 1 is electrically connected to one of the plurality of external electrodes 43 via the via hole 104, the wiring 145, and the via hole 105.

As described above, the electrodes 4 arranged at a narrow pitch
The external electrodes 41 connected to the further semiconductor device 23 are provided on the second wiring substrate 26 provided for suppressing a local increase in the wiring density in and around the mounting region when the semiconductor device 22 having the semiconductor device 22 is mounted. And the specifications of the wiring board 26 ′ are changed by connecting the semiconductor device 22 and the semiconductor device 23 via the second interconnects (105, 145, 104) formed on the second wiring board 26 ′. be able to. For example, the wiring board 1 shown in FIG.
The specifications of the wiring board 130 can be changed only by replacing the second wiring board 26 with the second wiring board 26 'without replacing the first wiring board 24 of 30. That is, the second
By simply changing the specifications of the wiring board 26, the wiring board 130
It can easily respond to changes in the type and number of semiconductor devices (electronic components) to be mounted on the semiconductor device.

One of the plurality of electrodes 42 of the semiconductor device 22 and the electrode 23a of the semiconductor device 23
Can be electrically connected to each other without going through the interconnection of the first wiring board 24. Therefore, the semiconductor device 23
Can be prevented from increasing the wiring density in the mounting area of the first wiring board 24 due to the further mounting of.

Next, referring to FIG. 5, a description will be given of a wiring board 140 which is a more specific example of the wiring board 130 of this embodiment.

FIG. 5 shows the semiconductor device 22 and the connector 136.
FIG. 6 is a cross-sectional view showing a wiring board 140 on which the components are mounted.

The wiring board 140 is a two-layer printed board 12
6, a four-layer printed circuit board 124, and a conductive connection member 127 made of conductive rubber. The two-layer printed board 126 and the four-layer printed board 124 have screws 137.
Are fixed to each other. Two-layer printed circuit board 12
6, a land (second connection electrode) 134 is formed as a connection member on the lower surface 126b of the four-layer printed circuit board 1.
A land (first connection electrode) 135 is provided on the upper surface 124a of
Are formed. A conductive connection member 127 is arranged between the second connection electrode 134 and the first connection electrode 135, and is sandwiched between them by the tightening force of the screw 137.

The two-layer printed circuit board 126 is formed on the second wiring 144 as a second interconnect and the upper surface 126a.
A plurality of external electrodes 43 each electrically connected to one of the plurality of electrodes 42 of the semiconductor device 22 by soldering; a second connection electrode 134 formed on the lower surface 126 b of the two-layer printed circuit board 126; 103 and 102. The via hole 103 electrically connects the second wiring 144 and the external electrode 43. The via hole 102 is formed between the second wiring 144 and the second connection electrode 134.
And are electrically connected.

The four-layer printed circuit board 124 is
6, the first wiring 146 electrically connected to the
a, and has a first connection electrode 135 disposed opposite to the second connection electrode 134 and a via hole 125. The via hole 125 electrically connects the first wiring 146 and the first connection electrode 135.

The second connection electrode 134 and the first connection electrode 135
Is formed of, for example, conductive rubber, and electrically connects the second connection electrode 134 and the first connection electrode 135. The use of the conductive connection member 127 made of conductive rubber has the advantages that a stable electrical connection can be obtained by the mechanical tightening force of the screw 137 and that the connection can be easily redone. Of course, other conductive materials may be used.

A plurality of connection terminals 188 are interposed between the two-layer printed board 126 and the four-layer printed board 124. The external electrodes 43 other than the external electrodes 43 electrically connected to the second wiring 144 are connected to the second wiring board 12.
6 is electrically connected to the wiring (not shown) formed through the connection terminal 188.

The via hole 103 is formed in the mounting area, and the via hole 102, the second connection electrode 134, the conductive connection member 127, the first connection electrode 135, and the via hole 125 are formed outside the mounting area. The second wiring 144 (second interconnection) of the two-layer printed board 126 is connected to the external electrode 43 via the via hole 103 in the mounting area.
Via hole 102, second connection electrode 134, and conductive connection member 1 outside the mounting region.
27, it is electrically connected to the first wiring 146 (first interconnect) of the four-layer printed circuit board 124 via the first connection electrode 135 and the via hole 125.

As described above, by electrically connecting the external electrode 43 and the first wiring 146 via the second wiring 144, the four-layer printed circuit board 124 located below the electrode group 112 of the semiconductor device 22 is formed. Area can be bypassed. As described above, when the wiring board 140 according to the present invention is used, even in the general-purpose semiconductor device 22 having the electrodes 42 arranged at high density in a grid array at a constant pitch, the wiring density in the mounting area and the periphery thereof is reduced. It can be reduced efficiently. The decrease in the wiring density of the mounting area of the first wiring board 124 and the periphery thereof is due to the connection terminal 1
It is clear from the fact that the number 88 is smaller than the number of the external electrodes 43.

The number and position of the external electrodes 43 electrically connected to the second interconnect 144 among the external electrodes 43 are appropriately selected according to the mounting area of the first wiring board 124.
When the external electrode 43 inside the mounting area among the plurality of external electrodes 43 is connected to the second wiring 144, the area that can be bypassed becomes wider, so that the wiring density in the mounting area of the four-layer printed circuit board 124 is reduced. Great effect.

The wiring connected to the external electrode 43 is led out of the mounting area via the second wiring 144 formed on the second wiring board 126, so that the wiring is electrically connected to the electrode group 112 and the first wiring is formed. Rather than bypassing a wiring group (not shown) formed on the substrate 124 in the first wiring substrate 124,
The length of the wiring can be reduced. Therefore, it is possible to avoid the problem that the operation speed of the signal is reduced due to the long wiring.

Further, the two-layer printed circuit board 126 is
What is necessary is just to selectively provide in the place where the bypass by the wiring 144 is needed, and it is not necessary to make the whole 1st wiring board 124 multilayer. That is, the printed circuit board may be locally formed in a pseudo multilayer. Therefore, the wiring board 140 is
The wiring board 124 can be manufactured at a lower cost than a multilayer board.

Further, a four-layer printed circuit board (first wiring board)
Reference numeral 124 further includes a ground layer 161 and a power supply layer 163. The ground layer 161 includes a plurality of external electrodes 4.
3 has a ground pattern electrically connected to at least one of them. The power supply layer 163 has a power supply pattern electrically connected to at least one of the plurality of external electrodes 43. The ground pattern and the power supply pattern may be formed on the entire surface of the ground layer 161 and the power supply layer 163, respectively. Thereby, the semiconductor device 22 can be electrically operated stably. Two-layer printed circuit board (second wiring board)
However, it may further have a ground layer and a power supply layer. In general, the ground electrode and the power supply electrode of the semiconductor device 22 are often provided on the innermost side of the package. Therefore, it is preferable that these electrodes be led out of the mounting area via the second interconnect.

As described in the fifth embodiment, it is preferable that the number of via holes penetrating the ground pattern and the power supply pattern be as small as possible from the viewpoint of the stability of electrical connection. Therefore, it is preferable that the ground layer and the power supply layer are formed below the wiring board (a wiring layer far from the mounting surface).

The first wiring board and the second wiring board can be independently manufactured by a known wiring board manufacturing method.

(Embodiment 3) The wiring board 170 of this embodiment shown in FIG. 6 is different from the wiring board 170 shown in FIG. 2 in that the second wiring board 126 has a plurality of second connection electrodes 133a and 133b which can be selectively used. It is different from the wiring board 120 that has been used.

FIG. 6 shows the semiconductor device 22 and the semiconductor device 22.
a and the wiring board 1 on which the semiconductor device 22b is mounted
FIG.

Four-layer printed circuit board (first wiring board) 124
A plurality of external electrodes 43, a plurality of external electrodes 43a, and a plurality of external electrodes 43b are formed on the upper surface 124a of the first substrate. The plurality of external electrodes 43 are electrically connected to one of the plurality of electrodes 42 of the semiconductor device 22 by soldering. The plurality of external electrodes 43a are connected to the semiconductor device 22a.
Is electrically connected to one of the plurality of electrodes 42a by soldering. The plurality of external electrodes 43b are electrically connected to one of the plurality of electrodes 42b of the semiconductor device 22 by soldering.

The first connection electrodes 121a, 121b and 123 are formed on the lower surface 124b of the four-layer printed circuit board 124.

The four-layer printed circuit board 124 has a via hole 1
22, a via hole 122a and a via hole 122b. The via hole 122 is connected to the external electrode 43.
And the first connection electrode 123 are electrically connected. The via hole 122a electrically connects the external electrode 43a and the first connection electrode 121a. Via hole 122
“b” electrically connects the external electrode 43b and the first connection electrode 121b.

Two-layer printed board 126 (second wiring board)
The first connection electrodes 123, 121a and 121b are provided on the upper surface 126a of the first connection electrodes 123, 121a and 121b.
21b.

The two-layer printed circuit board 126 is formed on the second wiring 14.
4 and via holes 101, 102a and 102b. The via hole 101 has the second wiring 144
And the second connection electrode 132 are electrically connected. The via hole 102a electrically connects the second wiring 144 and the second connection electrode 133a. Via hole 102
“b” electrically connects the second wiring 144 and the second connection electrode 133b.

The four-layer printed circuit board 124 and the two-layer printed circuit board 126 include a first connection electrode 123 and a second connection electrode 13.
2 between the first connection electrode 121a and the second connection electrode 133a or between the first connection electrode 121a and the first connection electrode 133a.
The conductive connection member 129 selectively provided between the connection electrode 121b and the second connection electrode 133b is fixed to each other by screws 137 with the conductive connection member 129 interposed therebetween.

As described above, the electrode 42 of the semiconductor device 22
The object electrically connected to the electrode 4 of the semiconductor device 22a
2a and the electrode 42b of the semiconductor device 22b are determined by the first connection electrode 121a and the second connection electrode 1b.
33a or between the second connection electrode 121b and the second connection electrode 133b.
9 is provided. That is, the first connection electrode 121a
Between the first connection electrode 133a and the conductive connection member 129
Is provided, the external electrode 43, the via hole 122, the first connection electrode 123, the conductive connection member 128, the second connection electrode 1
32, via hole 101, second wiring 144 (second interconnection of second wiring board), via hole 102a, second connection electrode 133a, conductive connection member 129, first connection electrode 12
The electrode 42 of the semiconductor device 22 and the electrode 42a of the semiconductor device 22a are electrically connected via the via 1a, the via hole 122a (the first interconnection of the first wiring board) and the external electrode 43a. On the other hand, when the conductive connection member 129 is provided between the first connection electrode 121b and the second connection electrode 133b, the external electrode 43, the via hole 122, the first connection electrode 123,
Conductive connection member 128, second connection electrode 132, via hole 101, second wiring 144 (second interconnection of second wiring board), via hole 102b, second connection electrode 133b, conductive connection member 129, first connection electrode The electrode 42 of the semiconductor device 22 and the electrode 42b of the semiconductor device 22b are electrically connected via the via 121b, the via hole 122b (first interconnection of the first wiring board) and the external electrode 43b. Therefore, even if a group of semiconductor devices having a plurality of interface modes are mounted on the wiring board 170,
A system having a different function can be configured by simply changing the position where the conductive connection member is provided without changing the zero component.

Further, for example, when the conductive connecting member 129 made of conductive rubber is used, a stable electric connection can be obtained by the mechanical tightening force of the screw 137, and the conductive connecting member 129 can be reused. There is an advantage that the connection can be easily redone. Of course, other conductive materials may be used.

The number of sets of the first connection electrodes and the second connection electrodes is not limited to three as in the case of the wiring board 170.

(Embodiment 4) Wiring board 18 of this embodiment
0 is the first wiring board 12 of the wiring board 120 shown in FIG.
4 and the second wiring board 126 are integrally formed. The components corresponding to the first wiring board 124 are first
Components corresponding to the multilayer wiring structure 124 'and the second multilayer wiring substrate 126 will be referred to as a second multilayer wiring structure 126'.

FIG. 7 shows the semiconductor device 22 and the connector 136.
FIG. 9 is a cross-sectional view showing a wiring board 180 on which is mounted.

The wiring board 180 has a four-layer wiring structure 124 'as the first multilayer wiring structure and a second multilayer wiring structure provided in contact with a part of the lower surface 124'b of the four-layer wiring structure 124'. And a two-layer wiring structure 126 '. That is, the structure of the wiring board 180 is the four-layer wiring structure 12.
This structure is equivalent to a structure in which a wiring structure 126'a for two layers is added to a part of 4 '. On the upper surface 124'a of the four-layer wiring structure 124 ', a plurality of external electrodes 43 electrically connected to one of the plurality of electrodes 42 of the semiconductor device 22 by soldering are formed.

The four-layer wiring structure 124 ′ has a connector 136.
And a first wiring 146 electrically connected to the first wiring 146. 2
The layer wiring structure 126 'has a second wiring 144.
Via hole 122a electrically connected to external electrode 43 and second wiring 144, and second wiring 144 and first wiring 1
Via hole 125a electrically connected to
It is formed through the layer wiring structure 124 'and the two-layer wiring structure 126'.

The via hole 122a is formed in the mounting area. On the other hand, the via hole 125a is formed outside the mounting area. Second wiring 1 of second multilayer wiring structure 126 '
44 (second interconnect) is electrically connected to the external electrode 43 via the via hole 122a in the mounting region,
In addition, outside the mounting region, it is electrically connected to the first wiring 146 (first interconnect) of the first multilayer wiring structure 124 'via the via hole 125a.

The operation and effect of this embodiment are the same as the operation and effect of the first embodiment.

Further, since the four-layer wiring structure 124 'and the two-layer wiring structure 126' are integrated, the wiring board 180 of the fourth embodiment is more structurally structured than the wiring boards of the first to third embodiments. High stability and high reliability.

Further, a four-layer wiring structure 124 '(first multilayer wiring structure) and a two-layer wiring structure 126' (second multilayer wiring structure)
When the wiring board 180 is manufactured by integrally forming the first and second wiring boards, the manufacturing cost is lower than that of the wiring boards of the first to third embodiments manufactured by separately forming the first and second wiring boards. It can be further reduced.

(Embodiment 5) FIG. 8 shows a six-layer printed circuit board 19 as a wiring board on which a semiconductor device 22 is mounted.
FIG. This wiring board 190 may be the first wiring board or the second wiring board in the above embodiment.

The six-layer printed circuit board 190 is a semiconductor device 2
Main surface (mounting surface) 190 on which a plurality of external electrodes 43 electrically connected to one of the two plurality of electrodes 42 are arranged
a and a via hole 1 in one of the plurality of external electrodes 43.
98, and a wiring layer 199 electrically connected thereto. The plurality of wiring layers 199 have via holes 198a formed in the external electrodes 43a electrically connected to the power supply electrodes 42A.
And a ground layer having a ground pattern electrically connected to the external electrode 43b electrically connected to the ground electrode 42B via the via hole 198b. 19
And 3. The wiring layer 199 includes a second layer, a third layer, and a fourth layer from the side closer to the main surface 190a of the six-layer printed board 190.
It is provided in the fifth layer and the fifth layer. The ground layer 193 is
4 from the side closer to the main surface 190a of the six-layer printed circuit board 190
It is provided in the layer. The power supply layer 194 is provided in the fifth layer from the side closer to the main surface 190a of the six-layer printed circuit board 190.

As described above, the main surface 190 a of the wiring board 190 is different from the ground layer 193 and the power supply layer 194.
A wiring layer 195 having neither the ground layer 193 nor the power supply layer 194 is provided closer to. Therefore, the via hole 198 penetrating the ground layer 193 is
External electrode 43a electrically connected to power supply electrode 42A
There is only one via hole 198a that electrically connects the power supply pattern and the power supply pattern. Further, there is no via hole 198 penetrating the power supply layer 194. That is, the via hole 1 electrically connecting the external electrode 43c to the wiring layer 195 having neither the ground layer 193 nor the power supply layer 194.
98c is formed without penetrating both the ground layer 193 and the power supply layer 194.

On the other hand, the main surface 19 of the six-layer printed circuit board 190
Ground layer 19 as the second and third layers from the side closer to 0a.
In the case of a wiring board provided with the power supply layer 3 and the power supply layer 194, there are many via holes 198c penetrating the ground layer 193 and the power supply layer 194. Therefore, the wiring board is provided around each via hole 198c to prevent a short circuit with the power supply layer and the ground layer. Due to the clearance area, the patterns (the power supply pattern and the ground pattern) located at the center of the semiconductor device 22 are separated from the external patterns. That is, the ground layer 193 and the power supply layer 194 are isolated islands.

In the wiring board 190 of this embodiment, since the via hole 198c is formed without penetrating both the ground layer 193 and the power supply layer 194, the ground electrode 42B and the power supply electrode 42A are formed on the innermost periphery of the package. Even when a BGA located in a portion is mounted, the ground layer 193 and the power supply layer 19 are formed by the via holes 198.
4 can be prevented from becoming an isolated island. That is, the functions of the ground layer 193 and the power supply layer 194 are enhanced as compared with the case where many via holes penetrate the ground layer 193 and the power supply layer 194. Therefore, the semiconductor device 22 mounted on the wiring board 190 can be electrically operated more stably.

When the wiring board has a plurality of wiring layers and the wiring layer has at least one of a power supply layer having a power supply pattern and a ground layer having a ground pattern, a plurality of external electrodes are arranged. If at least half of the wiring layers are formed between the main surface and at least one of the power supply layer and the ground layer, the number of via holes passing through the power supply layer and the ground layer is small, so that the wiring layer is mounted on the wiring board. Semiconductor device can be operated stably.

(Embodiment 6) FIG. 9 shows a wiring board 160 on which a semiconductor device 22 having a plurality of electrodes 42 arranged in an array and a connector 136 are mounted, a housing (heat dissipating member) 168, and a heat conductive member. Cushion (heat conductive member) 169
FIG. The wiring board 160 is the same as that shown in FIG.
Has substantially the same configuration as the wiring board 120 shown in FIG.

The four-layer printed circuit board 124 includes a ground layer 161 having a ground pattern and the four-layer printed circuit board 1.
An external electrode 43 a formed on the upper surface 124 a of the semiconductor device 22 and electrically connected to the ground electrode 42 B of the semiconductor device 22 by, for example, soldering, and a first connection electrode 164 formed on the lower surface 124 b of the four-layer printed circuit board 124. Via hole 1 electrically connected to external electrode 43 a, first connection electrode 164, and ground pattern of ground layer 161.
67.

The two-layer printed circuit board 126 is formed on the ground layer 162 having a ground pattern formed as a lower layer of the two wiring layers, and on the upper surface 126 a of the two-layer printed circuit board 126, and faces the first connection electrode 164. The second connection electrode 166 and the second connection electrode 1
66 and a via hole 159 electrically connected to the ground pattern of the ground layer 162.

The four-layer printed circuit board 124 and the two-layer printed circuit board 126 are connected to the conductive connections 128 and 129 and the first
In the state where the conductive connection member 165 further provided between the connection electrode 164 and the second connection electrode 166 is sandwiched, the screw 1
37. Conductive connection member 165
Is preferably made of conductive rubber like the conductive connection members 128 and 129. The two-layer printed board 126 and the housing 168 are
Are fixed to each other with a heat conductive member 169 formed of heat conductive rubber sandwiched between the lower surface 126b of the first member and the housing 168.

As described above, since the heat conductive member 169 is in close contact with the wiring board 160 and the housing 168, the heat generated by the semiconductor device 22 is transmitted through the ground layer 162 of the two-layer printed board 126. After flowing into the heat conductive member 169, it flows into the housing 168. This can prevent the temperature of the semiconductor device 22 from rising.

As the heat conductive rubber, for example, a high heat conductive silicone rubber (thermal conductivity: 3 to 4 × 10 ⁻³ ca)
1 / cm · sec · ° C. or more). The heat radiation member refers to a component for releasing generated heat, and includes a housing. The housing 168 is formed of, for example, a metal material such as aluminum or copper. Further, a configuration may be adopted in which a heat conductive member 169 is disposed between the lower surface 124 b of the second wiring board 124 and the housing 168 by using the wiring board 140 instead of the wiring board 160.

Since the semiconductor device 22 having many electrodes generates a relatively large amount of heat, the heat can be efficiently radiated by bringing the wiring board 160 into contact with the housing via the heat conductive member 169 in the mounting area. it can. Further, instead of the wiring board 160 in FIG. 9, the wiring board of the above embodiment can be appropriately used.

[0105]

According to the present invention, the external electrodes and the first interconnect are electrically connected via the second interconnect of the second wiring board, thereby being located below the electrode group of the semiconductor device. Since the region of the first wiring substrate can be bypassed, a wiring substrate capable of efficiently reducing the wiring density in the mounting region and the periphery thereof is provided. Also, the wiring connected to the external electrode may be formed on the second wiring board formed on the second wiring board.
By pulling out of the mounting area through the interconnect,
Since the length of the wiring is electrically connected to the electrode group and can be shorter than that of the wiring group formed on the first wiring substrate in the first wiring substrate, the length of the wiring increases the signal operation. Provided is a wiring board capable of avoiding the problem that the speed is reduced. Further, by providing the required minimum size of the second wiring board, it is possible to obtain a wiring board having the same function as that obtained by multilayering the entire first wiring board. And a wiring board that can be manufactured at a lower cost than a multilayered board.

[Brief description of the drawings]

FIG. 1 shows a plurality of electrodes (terminal electrodes) arranged in an array.
FIG. 4 is a cross-sectional view schematically showing a wiring board 110 on which a semiconductor device (semiconductor component) 22 having a semiconductor device 42 is mounted.

FIG. 2 is a cross-sectional view showing a wiring board 120 on which a semiconductor device 22 and a connector 136 are mounted.

FIG. 3 is a circuit board 13 on which a semiconductor device 22 is mounted;
FIG.

FIG. 4 is a cross-sectional view showing a second wiring board 26 'on which the semiconductor device 22 and another semiconductor device 23 are mounted.

FIG. 5 is a cross-sectional view showing a wiring board 140 on which the semiconductor device 22 and the connector 136 are mounted.

FIG. 6 is a cross-sectional view showing a wiring board 170 on which the semiconductor device 22, the semiconductor device 22a, and the semiconductor device 22b are mounted.

FIG. 7 is a cross-sectional view showing a wiring board 180 on which the semiconductor device 22 and the connector 136 are mounted.

FIG. 8 is a sectional view showing a six-layer printed circuit board 190 as a wiring board on which the semiconductor device 22 is mounted.

FIG. 9 shows a wiring board 160 on which a semiconductor device 22 having a plurality of electrodes 42 arranged in an array and a connector 136 are mounted, a housing (heat dissipating member) 168, and a heat conductive cushion (heat conductive member) 169. FIG.

[Explanation of symbols]

22, 22a, 22b, 23 Semiconductor device (semiconductor component) 24 First wiring board (main wiring board) 26, 26 'Second wiring board (sub-wiring board or daughter board) 42, 42a, 42b Electrode (terminal electrode) 41 , 43, 43a, 43b, 43c Land (external electrode) 44 Second interconnect 46 First interconnect 101, 102, 102a, 102b, 103, 12
2, 122a, 125, 125a, 159, 167, 1
98, 198a, 198b, 198c Via holes 110, 120, 130, 140, 160, 170, 1
80 Wiring board 121, 121a, 121b, 123, 135, 164
First connection electrodes 124, 124 'Four-layer printed circuit board 126, 126' Two-layer printed circuit board 127, 128, 129, 165 Conductive connection members 132, 133, 133a, 133b, 134, 166
Second connection electrode 161, 162 Ground layer 163 Power supply layer 168 Housing (heat dissipating member) 169 Heat conductive cushion (heat conductive member) 190 Six-layer printed circuit board 190 a Main surface on which a plurality of external electrodes 43 are arranged 193 Ground layer 194 Power supply Layer 199 Wiring layer 201 Power supply layer and ground layer formation area

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayuki Toyama 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5E317 AA11 AA24 CC11 CC25 CC53 CD25 CD27 GG14 5E336 AA04 AA09 AA14 BB03 BC15 BC34 CC32 CC36 CC58 DD02 EE03 EE12 GG30 5E338 AA03 BB25 CC04 CD05 EE23 5E344 AA02 AA09 AA12 AA19 AA22 BB02 CC09 CC23 CD12 DD02 DD07 EE13

Claims (12)

[Claims] 1. A wiring board on which a semiconductor device having a plurality of electrodes is mounted, the first having a plurality of first electrodes and a plurality of external electrodes connected to the plurality of electrodes of the semiconductor device. A second wiring board provided with a second wiring board, which is provided to face the first wiring board and has a second interconnect, wherein the second interconnect is a region where the plurality of external electrodes are formed; Is electrically connected to at least one external electrode of the plurality of external electrodes within a mounting area defined by a two-dimensional range, and the plurality of first interconnects are outside the mounting area. At least one of
A wiring board electrically connected to the two first interconnects. 2. The at least one first interconnect of the plurality of first interconnects is electrically connected to at least one other external electrode of the plurality of external electrodes in the mounting area. The wiring board according to claim 1, wherein the wiring board is connected. 3. The plurality of external electrodes are formed on an upper surface of the second wiring substrate, and the first wiring substrate has an upper surface of the first wiring substrate facing a lower surface of the second wiring substrate. 3. The wiring board according to claim 1, wherein the wiring board is arranged as follows. 4. The plurality of external electrodes are formed on an upper surface of the first wiring substrate, and the second wiring substrate has an upper surface of the second wiring substrate facing a lower surface of the first wiring substrate. 3. The wiring board according to claim 1, wherein the wiring board is arranged as follows. 5. The at least one external electrode according to claim 4, wherein the second interconnect is electrically connected to the at least one external electrode via a via hole penetrating from the upper surface of the first wiring board to the lower surface. Wiring board. 6. The second wiring board further includes another external electrode for electrically connecting to an electrode of another semiconductor device, wherein the other external electrode is one of the plurality of external electrodes. The wiring board according to claim 3, wherein the wiring board is electrically connected to at least one of the wiring boards. 7. A ground layer having a ground pattern electrically connected to at least one of the plurality of external electrodes, wherein at least one of the first wiring board and the second wiring board is provided. 7. The wiring board according to claim 1, further comprising at least one of a power supply layer having a power supply pattern electrically connected to at least one of the external electrodes. 8. The first wiring board includes a plurality of first connection electrodes provided on the lower surface and electrically connected to the plurality of first interconnects. A plurality of second connection electrodes provided on an upper surface and electrically connected to the second interconnect; and an electrical connection between the via hole and the second interconnect in the mounting area; An electrical connection between the second interconnect and the at least one first interconnect outside a region is selectively provided between the plurality of first connection electrodes and the plurality of second connection electrodes. The wiring board according to claim 5, wherein the wiring board is performed via a conductive connection member. 9. The wiring board according to claim 8, wherein the conductive connection member is formed of conductive rubber. 10. A wiring board on which a semiconductor device having a plurality of electrodes is mounted, wherein said first multilayer wiring structure has a plurality of first interconnects and said first multilayer wiring structure is formed on an upper surface of said first multilayer wiring structure. A plurality of external electrodes connected to the plurality of electrodes of the semiconductor device, and a second wiring structure provided in contact with a part of a lower surface of the first multilayer wiring structure and having a second interconnect, The second interconnect is electrically connected to at least one external electrode of the plurality of external electrodes in a mounting area in which a two-dimensional range is defined by a region in which the plurality of external electrodes are formed. And at least one of the plurality of first interconnects outside the mounting area.
A wiring board electrically connected to the two first interconnects. 11. The wiring board according to claim 1, further comprising a heat conductive member provided in the mounting area, and joined to the heat radiating member via the heat conductive member. 12. A wiring board on which a semiconductor device having a plurality of electrodes is mounted, wherein: a plurality of external electrodes connected to the plurality of electrodes of the semiconductor device; At least one of
And a plurality of wiring layers electrically connected via via holes, wherein the plurality of wiring layers have at least one of a power supply layer having a power supply pattern and a ground layer having a ground pattern. The number of the via holes formed through the at least one of the power supply layer and the ground layer is the number of the via holes formed without passing through the at least one of the power supply layer and the ground layer. Wiring board less than the number.