JP2001127197A - Semiconductor package insulating film and method of manufacturing semiconductor package provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To markedly increase the number of semiconductor packages which can be manufactured by using a sheet of insulating film so as to improve them in productivity and to reduce the disused region of the insulating film and the amount of molding compound used to an irreducible minimum. SOLUTION: An insulating film 10 is equipped with circuit patterns 11 formed in the directions of rows and columns on its main surface and circuit pattern plating power supply conductor patterns 14 which comprise main wires 12 arranged so as to surround the circuit patrons 11 and auxiliary wires 13 that extend between the circuit patterns so as to electrically connect the main wires 12 to the circuit patterns 11. In a method of manufacturing a semiconductor package by using the insulating film 10, semiconductor chip is mounted on each of the above circuit patterns, the regions surrounded with the main wires 12 are each demarcated, molding resin is injected into a molding die, and the semiconductor chips are sealed up. Outer connection terminals are connected to each of the circuit patterns, and then the insulating film 10 diced together with the molding resin at the position of the auxiliary wires into separate semiconductor packages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor package, and more particularly to a method of manufacturing a package having a film circuit board such as an LGA (Land Grid Array) or a BGA (Ball Grid Array). The present invention relates to a method capable of dramatically increasing the number and an insulating film used in the method.

[0002]

2. Description of the Related Art With the spread of portable telephones, portable computers, and other small electronic devices, there is an increasing demand for miniaturization of semiconductor packages mounted thereon. LGA and B
The GA-structured semiconductor package has an external connection terminal as an interface to an external board, and two external connection terminals on the bottom of the package.
Since they can be arranged in a three-dimensional manner, they are suitable for miniaturization. On the other hand, these semiconductor packages are QF
There is a problem that the manufacturing cost per unit package is generally higher than that of a package having a conventional structure such as a P (QuadFlat Package).

In manufacturing a package having an LGA or BGA structure, a flexible insulating film made of polyimide resin or the like is used. A plurality of the same circuit patterns are formed in the row and column directions of the insulating film, a semiconductor chip is mounted on each circuit pattern, sealed by a mold, and a plurality of semiconductor packages are manufactured simultaneously and in parallel.

FIG. 6 shows an example of a flexible insulating film used for manufacturing such a package. The insulating film 60 has sprocket holes 60a on both sides in the longitudinal direction so that the film can be wound and transported. Inside the row of the holes 60a of the insulating film 60,
A plurality of circuit patterns 61 made of copper or another metal are formed (specific circuit patterns are omitted in the figure, and only the region is shown). On the surface of the insulating film 60, a conductor pattern 62 and a bridge 63 connecting the conductor pattern 62 and each circuit pattern 61 are formed together with the circuit pattern 61. Conductive pattern 62 and bridge 6
Reference numeral 3 denotes a power supply pattern for plating each circuit pattern 61. By connecting a cathode of a DC power supply to the conductor pattern 62 and performing DC electrolysis in a solution containing plating metal ions, the pattern on the insulating film including the circuit pattern 61 is plated. Plating each circuit pattern 61 is an essential technique for improving the corrosion resistance and solder wettability of the circuit pattern 61. The formation of the circuit pattern 61, the power supply conductor pattern 62, and the bridge 63 on the insulating film 60 is performed by first attaching a metal foil to the entire area of the film, and then using lithography technology to remove unnecessary portions, that is, in the circuit pattern and each This is achieved by removing the area around the circuit pattern.

FIG. 7 shows a conventional semiconductor package manufacturing process using the insulating film 60. In a conventional semiconductor package manufacturing process, a semiconductor chip 71 is mounted on each circuit pattern 61 of the plated insulating film 60 (FIG. 7A), and each chip 7
One electrode pad and the circuit pattern are connected by wire bonding 72 (FIG. 1B). Next, the insulating film 60 is placed in a mold, and each semiconductor chip 71
Is molded 73 (FIG. 7C). Here, the mold has a cavity corresponding to each semiconductor chip 71, and a mold compound 73 is injected into each cavity, whereby the semiconductor chip 71 is sealed and the mold compound 73 The outer shape of the semiconductor package is formed. In the next step shown in FIG. 6D, after a solder bump 74 as an external connection terminal is formed on the back side of the insulating film 60, a punching jig 75 is used as shown in FIG. Then, each semiconductor package 76 is sequentially punched from the insulating film 60.

[0006]

However, in the manufacture of a semiconductor package using the above-mentioned conventional insulating film, there are several problems as described below. (1) In the conventional manufacturing of a semiconductor package, a resin is molded corresponding to each semiconductor package, and cut out individually using a punching jig. It was difficult to make it smaller. Therefore, the number of semiconductor packages that can be manufactured from one insulating film is limited, and
There are many areas on the insulating film that are not used as a substrate of a semiconductor package, which raises the manufacturing cost and hinders the improvement of productivity. (2) In the process of molding a semiconductor chip, a mold having a cavity corresponding to each semiconductor package is used, so that a long runner is required to guide the mold compound into each of the cavities. After injecting the mold compound into each cavity, a large amount of mold compound remains in the long runner. Such useless consumption of the mold compound contributes to raising the manufacturing cost of the semiconductor package. (3) When designing a plurality of types of insulating films having different planar sizes of circuit patterns, it is necessary to individually change the shape of the surrounding conductive pattern for plating depending on the size of the circuit pattern. It was inefficient.

Accordingly, it is an object of the present invention to dramatically increase the number of semiconductor packages that can be manufactured from one insulating film, to improve the productivity, to discard areas on the insulating film, and to use mold compounds. In order to reduce the production cost by minimizing the amount of

Another object of the present invention is to provide an insulating film having a conductor pattern which facilitates the design of a plurality of types of insulating films.

[0009]

SUMMARY OF THE INVENTION The present invention relates to an insulating film for providing an insulating substrate for mounting a semiconductor chip in a semiconductor package. The insulating film of the present invention includes a plurality of circuit patterns formed in the main surface of the insulating film in the row and column directions, a main line arranged to surround the plurality of circuit patterns, and a space between the circuit patterns. And a conductor pattern for plating power supply of the circuit pattern including a sub-line extending to electrically connect the circuit pattern to the main line.

[0010] Preferably, the main line of the conductor pattern is
It is formed for each pattern group consisting of a predetermined number of circuit patterns in the length direction of the insulating film.

Preferably, the main line of the conductor pattern has a pair of first lines extending on both sides in the longitudinal direction of the insulating film, and the pair of first lines extending between the pattern groups and having both ends. And a second line leading to

[0012] Preferably, the sub-line of the conductor pattern includes a grid-like line arranged so as to surround the periphery of each circuit pattern in the main line.

Further, preferably, the sub-line of the conductor pattern includes a plurality of bridges connecting the grid-like line and each circuit pattern.

In the present invention, the line width of the sub-line of the conductor pattern is at least smaller than the blade width of a dicing blade for cutting the insulating film, particularly 100 μm.
The following is preferred. On the other hand, the line width of the main line of the conductor pattern is preferably 0.6 mm or more.

Preferably, the insulating film comprises:
Under each of the circuit patterns, a via hole for mounting an external connection terminal for electrically connecting the circuit pattern to an external substrate is provided.

The present invention also relates to a method for manufacturing a semiconductor package. The manufacturing method of the present invention includes a step of preparing an insulating film having the above configuration, a step of plating each circuit pattern using a conductor pattern on the insulating film, Mounting a semiconductor chip and electrically connecting the circuit pattern and the semiconductor chip, and injecting a mold resin into a mold by partitioning the circuit pattern into regions surrounded by main lines of the conductor pattern. A step of sealing each semiconductor chip, a step of electrically connecting external connection terminals for mounting a semiconductor package to an external substrate to each of the circuit patterns, and a step of attaching the insulating film to the position of the sub-line. Dicing with the mold resin, and separating the semiconductor package into individual semiconductor packages.

In this case, the step of dicing the insulating film is performed by using a dicing blade having a blade width wider than at least the line width of the sub-line of the conductor pattern. Do not leave.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a pattern configuration on an insulating film according to an embodiment of the present invention. In the figure, the insulating film 10 is provided with holes 10a for conveying sprockets along both sides thereof. The insulating film 10 is first supplied as a long film, and is used after being cut into desired dimensions as shown in FIG. Insulating film 1
0 is preferably a polyimide resin film having a thickness of about 50 μm. Although omitted in this drawing, the insulating film 1
Numeral 0 has a plurality of via holes for mounting external connection terminals in a circuit pattern region described later. Via the via hole, the land area in the circuit pattern and the external connection terminal are electrically connected.

The insulating film 10 has on one surface thereof a circuit pattern 11 and a plating conductor pattern 14 including a relatively thick main line 12 and a relatively thin auxiliary line 13. These patterns correspond to the insulating film 1
A metal foil (preferably a copper foil) is once deposited on the entire area on the substrate 0, and the metal foil (preferably a copper foil) is vapor-deposited. It is formed by removing necessary metal parts.

A large number of circuit patterns 11 are regularly arranged on the insulating film 10 in the row and column directions. Each circuit pattern 11 is formed in a region defined by a sub-line 13 of a conductor pattern described later. In the example of the figure, 270 circuit patterns 11 are placed on the insulating film 10.
Is made. In this figure, the circuit patterns 11 are omitted by hatching, but in actuality, as shown in FIG. 2, each circuit pattern 11 has a plurality of lands 11a corresponding to via holes formed on an insulating film. , A plurality of connection lands 11b for wire bonding from the semiconductor chip and a plurality of line segments 11c connecting the lands.

The conductive pattern for plating 14 includes the main line 12 and the sub line 13. Main line of conductor pattern 1
2, the circuit pattern 11 on the insulating film 10 is divided into a plurality of blocks (three blocks 15A to 15A in the example of FIG. 1).
This is a frame-shaped wiring composed of relatively thick lines formed so as to be divided into C). That is, the main wire 12 is the insulating film 1
0, and a vertical line 12b formed at a predetermined interval in the longitudinal direction of the insulating film 10, that is, every predetermined number of circuit patterns. In one preferred embodiment, the horizontal line 12a has a line width of 0.6 to 1.0 mm, and the vertical line 12b has a line width of 0.1 to 1.0 mm.
3 to 2.0 mm. In the step of plating the circuit pattern 11, the cathode of the DC power supply is directly connected to the main line 12.

The sub-line 13 of the conductor pattern is
It is a grid-like wiring composed of relatively thin lines formed in each of the blocks 15A to 15C surrounded by. That is, the sub-line 13 has a vertical line 13a whose both ends are connected to the horizontal line 12a of the main line, and a vertical line 13b whose both ends are connected to the vertical line 12b of the main line.
Is formed by a horizontal line 13b. Each of the circuit patterns 11 is arranged in a grid cell formed by the vertical lines 13a and the horizontal lines 13b.

The line width of the sub-line 13 is determined by the relationship with the blade width of a dicing blade used in a later-described semiconductor package manufacturing process using the present insulating film.
When separating each semiconductor package, the insulating film 1
0 is cut and separated at the position of the sub-line 13 using a dicing blade. In the present manufacturing process, it is necessary to prevent the auxiliary line 13 from remaining on the insulating film 10 after cutting. The sub-line 13 causes a short circuit between the wirings in each circuit pattern 11. Removal of sub-line 13 is performed by sub-line 1
This is achieved by using a dicing blade having a blade width wider than the line width of No. 3. FIG. 3 is a view showing the relationship between the sub-line 13 and the blade width of the dicing blade used in the present manufacturing process, for such a purpose. Line width W
The insulating film 10 is cut along one sub-line 13 using a dicing blade having a blade width W2. Thereby, each line 11a-
11d are electrically separated from each other. The width of the insulating film 10 cut by the dicing blade having the blade width W2 is actually larger than the blade width. In one preferred embodiment, the blade width of the dicing blade is 15
When the distance is about 0 to 250 μm,
It is a fine line of 0 μm or less, more preferably 50 μm.

FIG. 2 is an enlarged view of a part of FIG. 1 showing a connection relationship between the circuit pattern 11 and the conductor pattern 14. As shown in the figure, around each circuit pattern 11,
A vertical line 13a and a horizontal line 13b as sub-lines of the conductor pattern extend. In addition, this figure shows the specific configuration of the circuit pattern 11, that is, the land 11a, the connection land 11b, and the line segment 11c as described above. In the example of the figure, among the lands 11a of the circuit pattern 11, only the surrounding lands contribute to electrical conduction between the semiconductor chip and the external substrate, and a plurality of lands inside are used for heat radiation and other purposes. It is a dummy land. In the present embodiment, the dummy lands are not subjected to plating.

As is apparent from FIG. 2, the conductor pattern 14 further includes vertical lines 13a and horizontal lines 13b of the sub-lines.
And a bridge 13c extending from the bridge 13c. Each bridge 1
3c is connected to each of the connection lands 11b of the circuit pattern 11. As a result, the circuit pattern 11 is electrically connected to the sub-line 13 of the conductor pattern (the sub-line 13 is connected to the main line 12). Therefore, the conductor pattern 1
4, all the circuit patterns 11 of the insulating film 10
Can be plated. In FIG. 2, a region 16 indicated by a virtual line is a mounting region of the semiconductor chip.

Next, a manufacturing process of a semiconductor package using the insulating film 10 will be described. FIG. 4 is a flowchart showing the manufacturing process, and FIG. 5 is a schematic side view corresponding to each process in FIG. Prior to this step, the insulating film 10 is prepared, and the circuit pattern 11 is subjected to a desired plating. Further, an adhesive made of thermoplastic polyimide or another material is applied on the semiconductor chip mounting area of each circuit pattern 11.

In the first step 401 and FIG. 5A, the insulating film 10 is disposed with the surface on which the circuit pattern is formed facing upward, and the semiconductor chip 51 is moved to the region on the circuit pattern to which the adhesive has been applied. Put on. In this state, the semiconductor chip 51 is fixed on the insulating film 10 by passing through a reflow furnace to melt the adhesive. Next step 402
5B, wire bonding is performed between the electrode pads of each semiconductor chip 51 and the connection lands of the corresponding circuit pattern (conductor wire 52).

Next, in step 403 and FIG. 5C, each semiconductor chip 51 is resin-sealed with a mold 53. In the molding process, a mold having cavities (that is, three cavities) corresponding to the regions of the blocks 15A to 15C (see FIG. 1) partitioned by the main line 12 is used. The mold compound supplied to the mold is guided into each cavity through a runner (in one embodiment, two runners are provided for one cavity), and a plurality of semiconductor chips 51 arranged in the block. Cover at the same time. The region on the insulating film 10 covered by the mold 53 includes the sub-line 13 of the conductor pattern. The main line 1 of the conductor pattern
Part or all of 2 may be included.

In the next step 404 and FIG.
Solder bumps 54, that is, lands having an LGA structure are formed on the back surface of the insulating film 10 as external connection terminals. Each solder bump 54 is electrically connected to a land of the circuit pattern 11 via a via hole 55 formed in the insulating film. Arranging a metal mask having a hole corresponding to the position of the via hole 55 along the back surface of the insulating film 10, filling a solder paste in the hole using a squeegee, and forming the solder bump 54 through a reflow furnace. Can be. However, it will be apparent to those skilled in the art that the process of the present invention can also be applied to the manufacture of a package having a BGA structure in which a solder ball is transferred and fixed onto a via hole filled with solder.

Next, in step 405 and FIG. 5E, the insulating film 1 is
The semiconductor chip 0 and the mold 53 are diced and separated into individual semiconductor packages 58. In the dicing, the insulating film 10 is fixed with the mold side down on the dicing tape 57 as shown in FIG.
Using a dicing blade with a blade width wider than the line width of 3,
This is performed at the position of the sub line 13. Thereby, the insulating film 10 and the mold 53 are divided into each semiconductor package unit, and the sub-lines 13 that electrically connect the respective wirings in each circuit pattern are removed.

As described above, a large number of semiconductor packages 58 are manufactured simultaneously using the insulating film 10. In the above manufacturing, the entire area surrounded by the main line 12 of the conductor pattern on the insulating film 10 is used as the area of the substrate of the semiconductor package (excluding the area of the sub line 13 removed by dicing) and is discarded. The area on the insulating film is only a small area outside the main line 12. Conventionally, the discarded area on the insulating film, which was 40% to 50%, was reduced to about 6% in one embodiment of the present invention.

The embodiment of the present invention has been described with reference to the drawings. Obviously, the scope of application of the present invention is not limited to the items shown in the above embodiment. In the above embodiment, the semiconductor chip was connected to the circuit pattern on the insulating film by wire bonding. However, even in a package using a so-called flip chip mounting in which the main surface of the semiconductor chip is mounted downward,
The insulating film of the present invention and the above manufacturing method are suitably used.

[0033]

As described above, according to the present invention, the number of semiconductor packages that can be manufactured from one insulating film is dramatically increased, and the productivity is improved. In the manufacture of a semiconductor package using the present insulating film, the discarded area on the insulating film and the amount of mold compound used are minimized, which reduces the cost of the semiconductor package. Further, even when designing a plurality of insulating films having circuit patterns of different planar sizes, it is not necessary to change the basic configuration of the conductor pattern for plating, and the design efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a view showing a pattern configuration on an insulating film according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a part of FIG. 1, showing a connection relationship between a circuit pattern and a conductor pattern;

FIG. 3 is a diagram showing a relationship between a sub line and a blade width of a dicing blade used in the present manufacturing process.

FIG. 4 is a flowchart showing a manufacturing process according to the present invention.

FIG. 5 is a schematic side view corresponding to each step of FIG. 4;

FIG. 6 is a diagram showing a pattern configuration on a flexible insulating film having a conventional structure used for manufacturing a semiconductor package.

FIG. 7 is a view showing a conventional semiconductor package manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating film 10a Hole 11 Circuit pattern 11a Land 11b Connection land 11c Line segment 12 Main line 12a Horizontal line 12b Vertical line 13 Subline 13a Vertical line 13b Horizontal line 13c Bridge 14 Conductor pattern 15A to 15C Block 51 Semiconductor chip 52 Conductor wire 53 Mold 54 Bump 55 Via hole 56 Dicing blade 57 Dicing tape 58 Semiconductor package

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kenji Masumoto 4260 Takao, Kawasaki, Hiji-cho, Hami-gun, Oita Prefecture F-term (reference) 5F061 AA01 BA05 CA01 CB13 in Texas Instruments Japan Limited

Claims (12)

[Claims] 1. An insulating film for providing an insulating substrate on which a semiconductor chip is mounted in a semiconductor package, comprising: a plurality of circuit patterns formed on a main surface of the insulating film in row and column directions; A main line arranged to surround the periphery of the pattern, and a conductor pattern for plating power supply of the circuit pattern including a sub-line extending between the circuit patterns and electrically connecting the circuit pattern and the main line, An insulating film having: 2. The insulating film according to claim 1, wherein the main line of the conductor pattern is formed for each pattern group including a predetermined number of circuit patterns in a length direction of the insulating film. 3. A main line of the conductive pattern extends between a pair of first lines extending on both sides in a length direction of the insulating film, and extends between the pattern groups and both ends are connected to the pair of first lines. The insulating film according to claim 2, further comprising a second wire. 4. The insulating film according to claim 1, wherein the sub-line of the conductor pattern includes a grid-like line disposed so as to surround each circuit pattern in the main line. 5. The insulating film according to claim 4, wherein the sub-line of the conductor pattern includes a plurality of bridges connecting the grid-like line and each circuit pattern. 6. The insulating film according to claim 1, wherein a line width of the sub-line of the conductor pattern is smaller than at least a blade width of a dicing blade for cutting the insulating film. 7. The line width of a sub-line of the conductor pattern is 10
The insulating film according to claim 1, which has a thickness of 0 μm or less. 8. The conductor pattern according to claim 1, wherein a main line has a line width of 0.1.
The insulating film according to any one of claims 1 to 7, which is 6 mm or more. 9. The insulating film according to claim 1, further comprising a via hole under each of the circuit patterns for mounting an external connection terminal for electrically connecting the circuit pattern to an external substrate. 3. The insulating film according to claim 1. 10. The insulating film according to claim 1, wherein the insulating film is made of a polyimide resin. 11. A method for manufacturing a semiconductor package, comprising: a step of preparing the insulating film according to claim 1; a step of plating each of the circuit patterns using a conductor pattern on the insulating film; A step of mounting a semiconductor chip in a predetermined region of each circuit pattern of the film and electrically connecting the circuit pattern and the semiconductor chip; and dividing the circuit pattern into regions surrounded by main lines of the conductor pattern. A step of injecting a mold resin into a mold and sealing each semiconductor chip; a step of electrically connecting external connection terminals for mounting a semiconductor package to an external substrate to each of the circuit patterns; Dicing the film together with the molding resin at the position of the sub-line and separating the film into individual semiconductor packages. Method of manufacturing the over-di. 12. The step of dicing the insulating film uses a dicing blade having a blade width wider than at least a line width of a sub-line of the conductor pattern, so that the sub-line does not remain after cutting the insulating film. 12. The method of manufacturing a semiconductor package according to claim 11, wherein: