JP2001124818A - Inspection device of semiconductor test program and inspection method of semiconductor test program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection device and an inspection method of a semiconductor test program for automatically conducting inspection of plural conditional branches of a conditional branching instruction in the inspection of the semiconductor test program. SOLUTION: A plural conditions automatically execution means 17 records either one of truth and falsehood a conditional instruction executes in a execution condition memory port 18, and takes out it for determination at the time of judgement. The plural conditions automatically execution means 17 controls so that the conditional instruction is both conditions of truth and falsehood, the instruction in a semiconductor test program 11 is simulatively executed with a program instruction simulation executing means 12, and inspected with a program inspection means 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for inspecting a semiconductor test program, and more particularly to an apparatus and method for inspecting a semiconductor test program that automatically and simulates a conditional branch instruction of a program under a plurality of conditions. About.

[0002]

2. Description of the Related Art Conventionally, this type of semiconductor test program inspection apparatus and method have been used for the purpose of determining whether or not a created semiconductor test program satisfies the restrictions of the semiconductor test apparatus. Here, the limitation of the semiconductor test apparatus is a connection state of each terminal between the semiconductor test apparatus and the semiconductor device to be measured when an instruction to apply a voltage for measurement to the semiconductor device to be measured is executed. However, the semiconductor test equipment and the device under test when executing the instruction are executed so that the device under test is not destroyed or deteriorated when the instruction is executed, or a normal test result is not obtained. This limits the connection state of each terminal with the semiconductor device.

FIG. 7 is a block diagram showing an example of a conventional semiconductor test program inspection apparatus. In this figure, a semiconductor test program 21 includes an instruction for testing a semiconductor with a semiconductor test device. The program instruction simulation execution processing means 22 reads an instruction for testing the semiconductor included in the program 21, and executes the instruction in a simulated manner (simulates).

The test apparatus simulation execution means 23 reads an instruction for the semiconductor test apparatus included in the semiconductor test program 21 and executes the instruction in a simulated manner. The test apparatus state storage device 24 stores the restrictions of the semiconductor device necessary for simulating the operation of the semiconductor test apparatus, and stores the state of the semiconductor test apparatus after simulated execution.

The program inspection means 25 compares the above-mentioned restrictions with the state of the semiconductor test apparatus after the simulation, and determines whether or not the semiconductor test program 21 satisfies the restrictions of the semiconductor test apparatus. Then, the determination result is displayed on the display device 26.

Next, the operation of the conventional semiconductor test program inspection apparatus will be described with reference to FIG. The program instruction simulation execution means 22 reads an instruction included in the semiconductor test program 21 from the head, and simulates the read instruction. And the program instruction simulation execution means 22
When an instruction for the semiconductor test apparatus is read from the semiconductor test program 21, the execution of the instruction is instructed to the test apparatus simulation execution means 23, and the instruction is executed by the test apparatus simulation execution means.
Transfer to 23.

As a result, the test apparatus simulation execution means 23
The transferred instruction is decoded, and the operation of the semiconductor test apparatus is simulated based on the decoded result. Then, the test apparatus simulation execution means 23 stores the result of simulating the semiconductor test apparatus in the test apparatus state data storage device 24. At this time, the program instruction simulation execution means 22 instructs the program inspection means 25 to execute the inspection of the semiconductor test program 21 before or after the execution of the instruction to the semiconductor test apparatus.

The program checking means 25 simulates the result of simulating the operation of the semiconductor test device stored in the test device status data storage device 24 via the test device simulating execution device 23 or directly. read out. Next, the program inspection means 25 determines whether or not the semiconductor test program 21 satisfies the restrictions of the semiconductor test device from the content of the result of the simulation, and displays the result on the display device 26. Thereafter, the semiconductor test program inspection device repeats the same operation for the instructions included in the semiconductor test program 21 until a program end instruction in the semiconductor test program 21 is executed.

[0009]

However, in the above-described conventional semiconductor test program inspection apparatus and semiconductor test program inspection method, inspection is performed only in one execution path from the beginning to execution of a program end instruction. At this time, the semiconductor test program can use a conditional branch instruction to test the semiconductor. For this conditional branch instruction, it is necessary to check for two types of operations for one instruction, both in the case where the condition is true and in the case where the condition is false.

For this reason, in the conventional semiconductor test program inspection apparatus and the conventional semiconductor test program inspection method, in the inspection of the semiconductor test program, one semiconductor test program usually includes a plurality of conditional branch instructions.
In order to cover the inspection of the plurality of execution paths, it is necessary to repeatedly perform inspection of a single semiconductor test program a plurality of times. Therefore, when the conventional semiconductor test program inspection apparatus and the conventional semiconductor test program inspection method include many conditional branch instructions,
There is a problem that the inspection time becomes longer corresponding to the number of conditional branch instructions, and the productivity is reduced.

The present invention has been made under such a background, and a semiconductor test program capable of improving the productivity of a semiconductor test program without lengthening the inspection time corresponding to the number of conditional branch instructions. An inspection apparatus and a semiconductor test program inspection method are provided.

[0012]

According to the first aspect of the present invention,
In a semiconductor test program inspection device for determining whether a semiconductor test program satisfies restrictions of a semiconductor test device, a program instruction simulation execution means for simulating an instruction included in the semiconductor test program; and A plurality of condition automatic execution means for simulating execution of a conditional branch instruction of a test program under a plurality of branch conditions; a test apparatus simulating execution means for simulating the operation of the semiconductor test apparatus; and an operation of the semiconductor test apparatus. A readable test apparatus state storage device in which a state after being simulated is stored, and whether or not the semiconductor test program satisfies the restrictions of the semiconductor test apparatus is determined and a test result is output. It is characterized by comprising program inspection means and a display device for displaying the inspection result.

According to a second aspect of the present invention, in the semiconductor test program inspection apparatus of the first aspect, a branch condition which is simulated by the plural condition automatic execution means with respect to the conditional branch instruction is replaced with the branch condition instruction. An execution condition storage unit is provided for storing each execution condition.

According to a third aspect of the present invention, in the semiconductor test program inspection apparatus according to the second aspect, the plurality of condition automatic execution means searches for a branch condition for each of the conditional branch instructions stored in the execution condition storage unit. Then, it is determined whether or not the simulated operation for all the conditional branch instructions stored in the execution condition storage unit has been completed.

According to a fourth aspect of the present invention, in the semiconductor test program inspecting method, it is determined whether the semiconductor test program satisfies the restrictions of the semiconductor test apparatus. The semiconductor test program and the semiconductor test apparatus are operated simulated under a plurality of branch conditions in a conditional branch instruction.

According to a fifth aspect of the present invention, there is provided a semiconductor test program inspection method for judging whether a semiconductor test program satisfies restrictions of a semiconductor test apparatus,
A first step in which program instruction simulation execution means simulates execution of an instruction included in the semiconductor test program; and a multiple-condition automatic execution means automatically executes a conditional branch instruction of the semiconductor test program under a plurality of conditions. A second step of simulating the operation; a third step of simulating the operation of the semiconductor test apparatus by the test apparatus simulating unit; and a test apparatus state storage device of the operation of the semiconductor test apparatus. A readable fourth process in which the state after simulated execution is stored, and the program inspection means determines whether the semiconductor test program satisfies the restrictions of the semiconductor test apparatus, A fifth step of outputting the inspection result and a sixth step of the display device displaying the inspection result are provided.

According to a sixth aspect of the present invention, in the semiconductor test program inspection method according to the fifth aspect, the plural condition automatic execution means executes a branch condition simulated for the conditional branch instruction by the branch condition. A step of storing in the execution condition storage unit for each instruction; and the plural-condition automatic execution means searching for the branch conditions of all the conditional branch instructions in the execution condition storage unit, and executing all the conditions stored in the execution condition storage unit. And determining whether or not the processing for performing the simulated operation of the conditional branch instruction has been completed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor test program inspection device according to one embodiment of the present invention. In this figure, the semiconductor test program
11 includes a command for operating the semiconductor test device, for testing the semiconductor with the semiconductor test device. The program instruction simulation execution means 12 sequentially reads the instructions described in the semiconductor test program 11 from the head, and simulates the read instructions (simulation).

The multiple condition automatic execution means 17 executes an execution condition storage unit 18 so that the conditional branch instruction included in the semiconductor test program 11 is simulated under both true and false conditions.
The program instruction simulating execution means 12 is controlled based on the data of the execution result of the conditional branch instruction stored in the program instruction. The execution condition storage unit 18 stores information such as a conditional branch instruction that is a target of a simulated execution necessary for the processing of the multiple condition automatic execution means 17 and an executed condition.

The test device simulation execution means 13 decodes the input command to the semiconductor test device and executes the command in a simulated manner. The test apparatus state storage device 14 stores or reads information (data) necessary for simulating the operation of the semiconductor test apparatus. The program checking means 15
Based on the request from the program instruction simulation execution means 12, the determination as to whether the semiconductor test program 11 satisfies the restrictions on the semiconductor test apparatus is made based on the restrictions on the semiconductor test apparatus stored in the test apparatus state storage device 14. , And the state corresponding to the limitation of the semiconductor test equipment,
This determination result is displayed on the display device 16.

Next, an example of the operation of the embodiment will be described with reference to FIG. 1, FIG. 2 and FIG. Semiconductor test program 11
Is to be checked, the program instruction simulation execution means
The semiconductor test program 12 is activated by a control signal from a control device (not shown) for starting the test (step 301).
(Step 302), the instructions included in the semiconductor test program 11 are sequentially read from the beginning, and the read instructions are simulated (step 3).
03). Then, the program instruction simulation execution means 12 requests the program inspection means 15 to inspect the read instruction (Step # 320).

Next, the program instruction simulation execution means 12
It is determined whether or not the read command is a command for the semiconductor test apparatus (Step 304). When determining that the read command is a command for the semiconductor test device, the program command simulation execution unit 12 sends the command to the test device simulation execution unit 13 (command for the semiconductor test device). To execute the simulation (Step # 30)
Five). As a result, the test apparatus simulation execution means 13 executes the input command in a simulated manner, and stores the executed result in the test apparatus state storage device 14.

Here, referring to FIG. 3, the operation of simulating the execution of the instruction to the semiconductor test apparatus by the test apparatus simulating means 13 performed in step # 305 based on the instruction from the program instruction simulating execution means 12 will be described in detail. explain. When a simulation execution instruction is input from the program instruction simulation execution means 12, the test apparatus simulation execution means 13 is activated (step # 40).
1), decode the instruction for the semiconductor test device requested by the program instruction simulation execution means 12 (step # 402).

Then, the test apparatus simulation execution means 13 determines whether the instruction for the semiconductor test apparatus is a data write instruction for the semiconductor test apparatus (step # 403), and if the instruction is a data write instruction for the semiconductor test apparatus. If it is determined, the data attached to the data write command is written to the test apparatus state storage device 14 (step # 404). On the other hand, when the test apparatus simulation execution means 13 determines that the command is not a data write command to the semiconductor test apparatus, the process proceeds to step 405 (step 40).
3).

Next, the test apparatus simulation execution means 13 determines whether or not the input command for the semiconductor test apparatus is a data read command for the semiconductor test apparatus (Step 405).
If it is determined that the command is a data read command to the semiconductor test device, the data stored at the address assigned to the data read command is read from the test device status storage device 14 (step # 406). On the other hand, the test device simulation execution means 13
Determines that the command is not a data read command to the semiconductor test apparatus, advances the process to step 407 (step 405).

Next, the test apparatus simulation execution means 13 determines whether or not the command for the semiconductor test apparatus is a function command for the semiconductor test apparatus (step # 407). In response to the operation of the function command, data is read from the test device status storage device 14 (step 408) and data is written to the test device status storage device 14 (step 409). Then, the test apparatus simulation execution means 13 stops the processing when the execution of the simulation operation of the instruction for the semiconductor test apparatus is completed.

Further, in FIG. 1, FIG. 2, and FIG.
The execution of simulated processing of a plurality of conditions of a conditional branch instruction will be described. If the program command simulation execution means 12 determines that the read command is not a command for the semiconductor test device in the semiconductor program 11, the program command simulation execution means 12 proceeds to step 306 (step 304).

The program instruction simulation execution means 12
Determines whether the read instruction is a conditional branch instruction, and when it is determined that the instruction is a conditional branch instruction, advances the process to step # 307 (step # 306). As a result, the program instruction simulation execution means 12 inquires of the multiple-condition automatic execution means 17 about an execution condition for executing the read conditional branch instruction under the true or false condition (step # 307).

Upon receiving the inquiry about the execution condition, the plural condition automatic execution means 17 executes the processing shown in FIG. 5 (step # 60).
1). Then, the multiple condition automatic execution means 17 determines whether or not the inquiry from the program instruction simulation execution means 12 is an inquiry about the execution condition of the conditional branch instruction. The process proceeds to step 620 (step # 602).

Then, the multiple condition automatic execution means 17 reads the execution condition corresponding to the input conditional branch instruction stored in the execution condition storage section 18 (step # 620). Next, the multi-condition automatic execution means 17 determines that the input conditional branch instruction is
Whether or not registered in the execution condition storage unit 18 is determined based on the execution condition read from the execution condition storage unit 18,
If it is determined that it has not been registered, the process proceeds to step 604 (step 603).

Thus, the multiple condition automatic execution means 17
The information for identifying the input conditional branch instruction is registered (step # 604), and the fact that the execution condition is true is registered (step # 605). Then, the multiple-conditions automatic execution means 17 replies to the program instruction simulation execution means 12 to execute the inquired conditional branch instruction under a true condition (step # 60).
6).

On the other hand, in the determination as to whether or not the input conditional branch instruction is registered in the execution condition storage unit 18, the multiple condition automatic execution means 17 advances the processing to step 604. (Step 603). Then, if the condition command is registered in the execution condition storage unit 18, the multiple condition automatic execution unit 17 replies to the program command simulation execution unit 12 to execute under the registered condition (Step # 607). As a result, the multiple condition automatic execution means 17 ends the operation of the multiple condition automatic execution processing (Step # 608).

Next, in the flowchart of FIG. 2, the program instruction simulating execution means 12 is a multi-condition automatic execution means.
It is determined whether the answer to the execution condition from 17 is made under a true condition or a false condition (step # 308). At this time, if it is determined in step 308 that the answer to the execution condition is to be performed under the true condition, the program instruction simulation execution means 12 simulates the operation of the conditional branch instruction under the true condition (step 309). ).

On the other hand, the program instruction simulation execution means 12
If it is determined in step # 308 that the answer to the execution condition is to be performed under a false condition, the operation of the conditional branch instruction is simulated according to the false condition (step # 310). Then, the program instruction simulation execution means 12 instructs the program inspection means 15 to execute the inspection of the semiconductor test program 11 (step 32).
1).

The program instruction simulation execution means 12
If it is determined that the input instruction is not a conditional branch instruction,
The process proceeds to step 310 (step 306). Then, the program instruction simulation execution means 12 simulates the operation of the instruction and advances the process to step 321 (step 310).

Next, the program checking means 15 starts execution of the flowchart shown in FIG. 4 according to the instruction from the program instruction simulation execution means 12 (step # 501). FIG.
6 is a flowchart illustrating an operation example of a program checking unit 15. Then, the program checking means 15 reads out the data of the simulated instruction result, which is stored in the test equipment state storage device 14 via the test equipment simulation execution means 13 or directly (step # 502).

Next, the program checking means 15 determines whether or not the data content satisfies the restrictions of the semiconductor test apparatus. If not, the process proceeds to step 504 (step 504). 503). If the content of the data does not satisfy the restrictions of the semiconductor test device, the program inspection means 15 displays the content of the data on a display device.
16 is displayed, and the process proceeds to step 505 (step 504).

On the other hand, when the contents of the data satisfy the restrictions of the semiconductor test apparatus,
The process proceeds to step 505. Thus, the program checking means 15 ends the program checking process (step 50).
Five). Thereafter, the same operation is repeated for the instructions included in the semiconductor test program 11 until a program end instruction is executed (Step # 501 to Step # 505).

Next, in the flowcharts of FIGS. 2 and 5, the program instruction simulation execution means 12 determines whether or not the instruction read from the semiconductor test program 11 is a program end instruction (step # 312). At this time, if the program instruction simulation execution means 12 determines that the instruction read from the semiconductor test program 11 is not a program end instruction, the process proceeds to step 303. On the other hand, when the program instruction simulation execution means 12 determines that the instruction read from the semiconductor test program 11 is a program end instruction, the process proceeds to step 313.

Then, the program instruction simulation execution means 12
Executes the program termination command, and then inquires of the multiple condition automatic execution means 17 whether or not the retest should be executed (step # 313). That is, the program instruction simulation execution means 12 determines whether or not there is a branch instruction in which all of a plurality of branch conditions are not performed among the conditional branch instructions in the semiconductor test program 11.

Thus, the multiple condition automatic execution means 17
It is determined whether or not the inquiry from the program instruction simulation execution means 12 is a retest of the semiconductor test program 11 (step # 609). At this time, the multiple condition automatic execution means 17
If it is determined that the inquiry from the program instruction simulation execution means 12 is not a retest of the semiconductor test program 11, the process proceeds to step 610 (step 609). Then, since the inquiry is not a re-examination, the multiple condition automatic execution means 17 processes this inquiry as an abnormal inquiry, and proceeds to step 608 (step 610).

On the other hand, when the multiple condition automatic execution means 17 determines that the inquiry from the program instruction simulation execution means 12 is a retest of the semiconductor test program 11, the processing proceeds to step 612 (step 609). Then, the multiple condition automatic execution means 17 reads the branch condition of the branch condition instruction in the execution condition recording unit 18 (Step 621). Then, the multiple condition automatic execution means 17 sequentially determines the execution state of the branch condition read from the execution condition recording unit 18, that is, whether the registered conditional branch instruction is simulated under both true and false conditions. It is determined whether or not all the registered branch condition instructions are present (step # 611).

At this time, when the multi-condition automatic execution means 17 determines that the read branch condition instruction is found to include a conditional branch instruction in which either the true or false branch condition has not been executed, the processing proceeds. To step 613 (step 611). Thereby, the multiple condition automatic execution means 17
Searches for a conditional branch instruction that has simulated the operation of the conditional branch instruction last among the retrieved unexecuted conditional branch instructions (step # 613).

Next, the multiple condition automatic execution means 17 registers an unexecuted branch condition as an execution condition in the searched condition branch instruction which simulated the operation of the conditional branch instruction last (step # 614). . And a multiple condition automatic execution means
17 replies to the program instruction simulation execution means 12 the re-test execution of the semiconductor test program 11 (step # 615).

On the other hand, if the plural condition automatic execution means 17 determines that there is no condition branch instruction in which the true or false branch condition has not been executed among the read branch condition instructions, the process proceeds to step # 612. (Step 611). In other words, when all the conditional branch instructions have been simulated under both the true and false branch conditions, the multiple-condition automatic execution means 17 informs the program instruction simulated execution means 12 that re-checking is unnecessary. Answer (Step # 612).

The program instruction simulation execution means 12 determines whether or not the response from the multiple condition automatic execution means 17 indicates that the semiconductor test program is to be retested (step # 314). At this time, the program instruction simulation execution means
When it is determined that the answer from the multiple condition automatic execution means 17 indicates that the semiconductor test program is to be re-examined, the process returns to step # 302 (step # 314). That is, the program instruction simulation execution means 12 performs the inspection of the semiconductor test program 11 until all of the registered conditional branch instructions are simulated under both true and false conditions.

On the other hand, the program instruction simulation execution means 12
If it is determined that the response from the multiple condition automatic execution means 17 indicates that the semiconductor test program is not to be retested, the process proceeds to step 315 (step 314). Accordingly, the program instruction simulation execution means 12 determines that the simulated operation has been executed under both true and false branch conditions in all the conditional branch instructions in the instructions of the semiconductor test program 11, and The simulated execution of the instruction ends (step # 315).

Next, a specific operation of the semiconductor test program inspection apparatus according to an embodiment of the present invention will be described using an actual program example. For example, it is assumed that a semiconductor test program 11 shown in FIG. 6 is given as a program example. 6, instruction 701, instruction 704, instruction 70
It is assumed that the instruction 8 is an instruction other than the conditional branch instruction.

When the semiconductor test program inspection device is started by a control device (not shown), the program instruction simulation execution means 12 executes the first instruction 701 of the semiconductor test program 11.
Is read, and an inspection of the semiconductor test program 11 is requested to the program inspection means 15 before execution of the simulation. Next, the program instruction simulation execution means 12 simulates the operation of the read instruction 701.

Then, the program instruction simulation execution means 12
Requests the program checking means 15 to check the semiconductor test program 11 after simulated execution of the operation of the instruction 701. Thereafter, the program instruction simulation execution means 12 shall similarly request the inspection to the program inspection means 15 before and after the simulated execution of the instructions sequentially read from the semiconductor test program 11, and the description regarding this Hereinafter, the description is omitted.

Next, the program instruction simulation execution means 12
It is assumed that the conditional branch instruction 702 is read from the semiconductor test program 11. Thereby, the program instruction simulation execution means
12 inquires the multiple condition automatic execution means 17 about the execution condition of the read conditional branch instruction 702. Then, the multiple condition automatic execution means 17 reads the execution condition from the execution condition storage unit 18. However, since no condition branch instruction has been registered as the execution condition, the condition branch instruction 702 is stored in the execution condition storage unit 18. Register with.

Further, the multiple condition automatic execution means 17 registers the execution condition of the conditional branch instruction 702 registered in the execution condition storage section 18 as true, and returns true to the program instruction simulation execution means 12 as the execution condition. Next, the program instruction simulation execution means 12 executes the conditional branch instruction 7 in the line next to the conditional branch instruction 702.
Read 03.

The program instruction simulation execution means 12
Makes an inquiry to the multiple condition automatic execution means 17 about the execution condition of the read conditional branch instruction 703. As a result, the multiple condition automatic execution means 17 reads the execution condition from the execution condition storage unit 18, but the condition branch instruction 703 is not registered in the execution condition storage unit 18. Register to 18. Then, the multiple condition automatic execution means 17
Registers true as the execution condition of the conditional branch instruction 703 registered in the execution condition storage unit 18, and returns true as the execution condition to the program instruction simulation execution means 12.

Next, the program instruction simulation execution means 12
Since the execution condition of the conditional branch instruction 702 is false, the instructions 704, 705, and 706 are sequentially read from the semiconductor test program 11, and the operations of these instructions are sequentially executed in a simulated manner. On the other hand, the program instruction simulation execution means 12
The instructions 7, 708, and 709 are executed when the execution condition of the conditional branch instruction 702 is false, and therefore are not executed because the present time is true.

Next, the program instruction simulation execution means 12
The instruction 710 is read, and the operation of the instruction 710 is simulated. At this time, since the instruction 710 is a program end instruction, the program instruction simulation execution means 12 inquires of the multiple condition automatic execution means 17 whether or not the semiconductor test program 11 is to be retested.

Then, the multiple condition automatic execution means 17 reads the branch condition of the conditional branch instruction registered in the execution condition storage section 18. Then, the multiple condition automatic execution means 17 detects that the execution conditions of the previously registered conditional branch instructions 702 and 703 are both executed only when the execution condition is true.
As a result, the multiple automatic condition execution means 17 searches for a conditional branch instruction having an unexecuted execution condition executed last, and detects the conditional branch instruction 703 as a search result.

Next, the multiple condition automatic execution means 17 changes the execution condition of the conditional branch instruction 703 from true to false. And
The multiple condition automatic execution means 17 replies to the program instruction simulation execution means 12 that the semiconductor test program 11 needs to be retested. Next, program instruction simulation execution means
12 receives the response indicating that the retest is necessary, reads the first instruction 701 in the semiconductor test program 11 again, and simulates the operation of the instruction 701.

Next, the program instruction simulation execution means 12
The conditional branch instruction 702 in the semiconductor test program 11 is read, and the execution condition of the conditional branch instruction 702 is inquired to the multiple condition automatic execution means 17. Thereby, the multiple condition automatic execution means 17 stores the execution condition of the condition instruction 702 in the execution condition storage unit 1.
Read from 8.

Since the conditional branch instruction 702 has already been registered from the execution condition read from the execution condition storage unit 18 and the execution condition remains true, there is no change. Answer true as a condition. Next, the program instruction simulation execution means 12 executes the semiconductor test program.
The conditional branch instruction 703 is read from 11 and the execution condition of the conditional branch is inquired to the multiple condition automatic execution means 17.

Thus, the multiple condition automatic execution means 17
The execution condition of the condition instruction 703 is read from the execution condition storage unit 18. Then, the multiple condition automatic execution means 17 calculates the condition branch instruction 703 from the execution condition read from the execution condition storage unit 18.
Is registered, and since the execution condition has been changed from true to false, false is returned as the branch condition. In response to this answer, the program instruction simulation execution means 12 reads the program end instruction of the instruction 710 next because the execution condition of the conditional branch instruction 703 is false, and simulates the operation of the instruction 710.

Next, the program instruction simulation execution means 12
Since the instruction 710 is a program end instruction, the multi-condition automatic execution means 17 is inquired again as to whether or not there is a retest. As a result, the multiple condition automatic execution means 17 reads out the execution conditions of all the registered conditional branch instructions from the execution condition storage unit 18.

Then, from the execution condition storage unit 18, the multiple-condition automatic execution means 17 executes, from among the execution conditions of the previously registered conditional branch instruction 702 and conditional branch instruction 703, the conditional instruction It has been executed under the condition, while the condition instruction 702 detects that it has not yet been executed under the false condition.

As a result, the multiple condition automatic execution means 17 searches for a condition instruction having an unexecuted execution condition executed last, and detects a condition instruction 702 as a search result. And
The multiple condition automatic execution means 17 changes the execution condition of the conditional branch instruction 702 from true to false, and replies to the program instruction simulation execution means 12 that it is necessary to recheck.

Next, the program instruction simulation execution means 12
Upon receiving a response from the multiple condition automatic execution means 17 indicating that re-inspection is necessary, the first instruction 701 of the semiconductor test program 11 is read again, and the operation of this instruction 701 is simulated. Then, the program instruction simulation execution means 12 reads the conditional branch instruction 702 from the semiconductor test program 11, and inquires the multiple condition automatic execution means 17 about the execution condition of the conditional branch instruction 702.

As a result, the multiple condition automatic execution means 17
The execution condition of the condition instruction 702 is read from the execution condition storage unit 18. Then, the multiple condition automatic execution means 17
702 has been registered, and detects that the execution condition has been changed to false, and returns false as the execution condition. As a result, the program instruction simulation execution means 12 next reads the instruction 708 from the semiconductor test program 11, and simulates the operation of the instruction 708.

The program instruction simulation execution means 12
Reads the program end command of the command 710 from the semiconductor test program 11. As a result, the program instruction simulation execution means 12 again inquires of the multiple condition automatic execution means 17 whether or not there is a recheck. Then, the multiple condition automatic execution means 17 reads the execution condition of the registered conditional branch instruction from the execution condition storage unit 18.

As a result, from the execution conditions read from the execution condition storage unit 1, the multiple condition automatic execution means 17 determines that the execution conditions of the previously registered conditional branch instruction 702 and conditional branch instruction 703 are both true and false conditions. To detect that it has already been executed. Then, the multiple condition automatic execution means 17 replies to the program instruction simulation execution means 12 that the inspection of the semiconductor test program 11 has been completed.

Thus, the program instruction simulation execution means
12 receives the response to the completion of the inspection by the multiple condition automatic execution means 17, and ends all the program command simulation executions for the semiconductor test program 11. As described above, according to the embodiment of the present invention, the inspection of the semiconductor test program can be performed only once for a plurality of conditions, and even in the inspection of the semiconductor test program in which a plurality of conditional branch instructions exist, a plurality of inspections can be performed. Since it is not necessary to change the condition setting of a plurality of conditional branches for each conditional branch instruction and perform the inspection, the time required for the inspection can be reduced, and the productivity of the semiconductor test program is improved.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention.

[0070]

As described above, according to the semiconductor test program inspecting apparatus of the present invention, the multiple condition automatic execution means for controlling the conditional branch instruction to perform one inspection process under a plurality of conditions is provided. This eliminates the need to change the plurality of branch conditions for each test and repeat the test process of the semiconductor test program, which is required when using the conventional test apparatus for a semiconductor test program. And the productivity of the semiconductor test program is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor test program inspection device according to an embodiment of the present invention.

FIG. 2 is a flowchart of a program instruction simulation execution unit according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation example of a test apparatus simulation execution unit according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation example of a program checking unit according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating an operation example of a multiple condition automatic execution unit according to an embodiment of the present invention.

FIG. 6 is a specific example of a semiconductor test program.

FIG. 7 is a block diagram showing a configuration of a semiconductor test program inspection device according to the related art.

[Explanation of symbols]

 11 Semiconductor test program 12 Program instruction simulation execution means 13 Test equipment simulation execution means 14 Test equipment state storage device 15 Program inspection means 16 Display device 17 Multiple condition automatic execution means 18 Execution condition storage unit 21 Semiconductor test program 22 Program instruction simulation execution means 23 Test equipment simulation execution means 24 Test equipment status storage device 25 Program inspection means 26 Display device

Claims (6)

[Claims] 1. A semiconductor test program inspection device for determining whether a semiconductor test program satisfies restrictions of a semiconductor test device, wherein a program instruction simulated execution for simulately executing an instruction included in the semiconductor test program is provided. Means, a plurality of conditions automatic execution means for simulating the conditional branch instruction of the semiconductor test program under a plurality of branch conditions, a test apparatus simulating execution means for simulating the operation of the semiconductor test apparatus, and the semiconductor A readable test device state storage device in which a state after the operation of the test device is simulated is stored, and it is determined whether the semiconductor test program satisfies the restrictions of the semiconductor test device, A program inspection means for outputting an inspection result; and a display device for displaying the inspection result. Semiconductor test program inspection equipment. 2. An execution condition storage unit for storing, for each branch condition instruction, a branch condition simulated by the multiple condition automatic execution means for the conditional branch instruction. 2. The semiconductor test program inspection device according to 1. 3. The multi-condition automatic execution unit searches for a branch condition for each of the conditional branch instructions stored in the execution condition storage unit, and searches for all of the conditional branch instructions stored in the execution condition storage unit. 3. The semiconductor test program inspection device according to claim 2, wherein it is determined whether or not the simulated operation has been completed. 4. A semiconductor test program inspection method for judging whether a semiconductor test program satisfies restrictions of a semiconductor test apparatus, comprising the steps of: determining a semiconductor test program under a plurality of branch conditions in a conditional branch instruction included in the semiconductor test program; A semiconductor test program inspection method characterized by simulating a test program and a semiconductor test apparatus. 5. A semiconductor test program inspection method for determining whether a semiconductor test program satisfies restrictions of a semiconductor test apparatus, wherein a program instruction simulation execution means simulates an instruction included in the semiconductor test program. A second step of automatically executing a conditional branch instruction of the semiconductor test program in a plurality of conditions in a simulated manner; A third step in which the operation of the semiconductor test apparatus is simulated; and a readable third state in which the state after the operation of the semiconductor test apparatus is simulated is stored. In step 4, the program inspection means determines whether the semiconductor test program satisfies the restrictions of the semiconductor test apparatus, and outputs an inspection result. Fifth and processes of the display device is a semiconductor test program testing method characterized by having a sixth step of displaying the test results. 6. A step of storing a branch condition simulated for the conditional branch instruction in an execution condition storage unit for each of the branch condition instructions, wherein the plural condition automatic execution means stores the condition. Means for retrieving the branch conditions of all the conditional branch instructions in the execution condition storage unit and completing the process of performing the simulated operation of all the conditional branch instructions stored in the execution condition storage unit 6. The semiconductor test program inspection method according to claim 5, further comprising a step of determining whether or not the semiconductor test program is valid.