JP2001119030A - Method for manufacturing thin-film transistor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin-film transistor array for preventing display failure and drive failures from occurring. SOLUTION: A metal film layer corresponding to at least a gate electrode shape and a scanning line wiring shape is etched for two times by double patterning in first and second patterning processes. At this time, the metal film layer has been surely eliminated between a region, where a scanning line Y and a gate electrode 16 are formed, and a region where a signal line contact 13 and a pixel contact 14 are formed. Therefore, even if when pixels are arranged with high density and the margin between wires, electrodes, the wires and electrodes, or the like becomes narrow in terms of planes the short- circuiting between them can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor applied to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device is constituted by sandwiching a liquid crystal composition between an array substrate and a counter substrate. The array substrate is composed of a scanning line and a signal line arranged in a matrix on a glass substrate, a pixel electrode arranged in a pixel region defined by the scanning line and the signal line, and a scanning line and a signal line. It has a thin film transistor or TFT as a switching element arranged at the intersection.

[0003] These devices are subjected to a series of photolithography steps: film formation, photoresist coating, exposure,
It is formed by performing the steps of development, etching, and photoresist stripping a plurality of times.

In such a photolithography process, if particles are present on the photoresist or the photomask before exposing the photoresist,
A desired pattern cannot be formed during etching. For this reason, etching failure occurs, which causes disconnection or short-circuit on the wiring. In some cases, a point defect or a line defect is generated, which causes a problem of lowering the production yield.

In order to solve such a problem, there has been proposed a method in which wiring is formed in two layers and each wiring is formed in a separate photolithography step. According to this method, even if the photoresist is partially lost due to particles or the like at the time of forming one of the wirings and is removed at the time of etching and the wiring is broken, the disconnection occurs at the time of forming the other wiring. If the portion can be supplemented, the occurrence of disconnection failure can be prevented as a result. That is, this method is an example of a redundant design of wiring.

[0006]

However, the above-mentioned method can cope with the disconnection of the wiring,
A short between wires cannot be corrected at all. In particular, when pixels are arranged at high density in the display area, margins between wirings, between electrodes, between wirings and electrodes, etc. are narrow in plan view. For this reason, for example, when patterning a scanning line, if a patterning defect in which a part of the scanning line extends on a contact electrode for a signal line or a pixel electrode occurs, the scanning line and the signal line or the pixel electrode are Is short-circuited, which causes a problem of display failure.

In the case where an n-channel thin film transistor and a p-channel thin film transistor are arranged as drive circuits in the vicinity of a peripheral area located in the periphery of the display area, one of the gate electrodes is patterned when the respective gate electrodes are patterned. When the patterning failure in which the gate electrode extends to the other side occurs, a short circuit occurs between the respective gate electrodes of the n-channel type and p-channel type thin film transistors, causing a problem that normal driving cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and has as its object to provide a method of manufacturing a thin film transistor array applicable to a liquid crystal display device, which can prevent display defects and drive defects. An object of the present invention is to provide a method for manufacturing a thin film transistor array.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a thin film transistor array, comprising the steps of: forming a semiconductor layer on a substrate; A thin film transistor array including: a step of forming a scanning line integrally with a gate electrode via a first insulating layer; and a step of forming a signal line on the first insulating layer and the scanning line via a second insulating layer. Forming the scanning line integral with the gate electrode by forming a metal film on the first insulating film and patterning at least a part of the metal film at least twice. It is characterized by being performed.

According to a fifth aspect of the present invention, in the method of manufacturing a thin film transistor array having an n-channel thin film transistor and a p-channel thin film transistor on the same substrate, the gate of the n-channel thin film transistor and the gate of the p-channel thin film transistor are provided. The electrode layer includes a step of forming a metal film over the semiconductor layer with an insulating film interposed therebetween, a region substantially equal to the electrode shape of the gate electrode of the one thin film transistor, and a region including the electrode shape of the gate electrode of the other thin film transistor. And a first etching step of etching the other region, a region substantially equal to the electrode shape of the gate electrode of the other thin film transistor, and a region including the electrode shape of the gate electrode of the one thin film transistor, and the other region Etching for etching When having a region to be etched by said first and second etching step, and at least partially overlap.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a thin film transistor array according to the present invention will be described below with reference to the drawings. The method for manufacturing a thin film transistor according to the present invention is applicable, for example, as a method for manufacturing an n-channel thin film transistor and a p-channel thin film transistor that function as switching elements and drive circuit elements of an active matrix liquid crystal display device. The switching element is arranged in a display area of an array substrate constituting the liquid crystal display device. Further, the n-channel thin film transistor and the p-channel thin film transistor as driving circuit elements function as complementary circuits and are arranged in a peripheral area around the display area.

FIG. 1 schematically shows an example of a liquid crystal display panel of a liquid crystal display device using an n-channel thin film transistor and a p-channel thin film transistor formed on the same substrate as a driving circuit.

FIG. 2 schematically shows a circuit configuration of an active matrix type liquid crystal display device.

As shown in FIGS. 1 and 2, the liquid crystal display panel 10 includes an array substrate 100 as a first substrate, an opposing substrate 200 as a second substrate disposed opposite to the array substrate 100, and an array substrate. 100 and a liquid crystal composition 300 disposed between the opposing substrate 200. In such a liquid crystal display panel 10, a display area 102 for displaying an image includes an array substrate 100 and a counter substrate 20.
And a peripheral area 104 having various wiring patterns and a driving circuit formed in a region surrounded by a sealing material 106 for pasting with 0.
Are formed in a region outside the sealing material 106.

The display area 102 of the array substrate 100 is
As shown in FIG. 2, mxn pixel electrodes 151 arranged in a matrix on a transparent insulating substrate, for example, a glass substrate having a thickness of 0.7 mm, are formed along the row direction of the pixel electrodes 151. M scanning lines Y1 to Ym, n signal lines X1 to Xn formed along the column direction of these pixel electrodes 151, and scanning lines Y1 to Ym and signal lines corresponding to mxn pixel electrodes 151. Mxn thin film transistors, ie, pixel TFTs 121, arranged as switching elements near the intersections of X1 to Xn,
The scanning line driving circuit 18 for driving Ym, these signal lines X1
To Xn.

The scanning lines Y and the signal lines X are formed of a low-resistance material such as aluminum or a molybdenum-tungsten alloy. The pixel electrode 151 is made of a transparent conductive material, for example, indium-tin-oxide or I
It is formed by TO.

The TFT 121 is constituted by, for example, a top gate type polycrystalline silicon thin film transistor having a portion protruding from the scanning line Y as a gate electrode and a polycrystalline silicon thin film as an active layer. The source region of the semiconductor layer is
A source electrode electrically connected to the pixel electrode 151 is in contact, and a drain region of the semiconductor layer is in contact with a drain electrode forming a part of a signal line.

The surface of the pixel electrode 151 is
And is covered with an alignment film for aligning the liquid crystal composition 300 interposed between them.

Each of the TFTs 121 is driven by a corresponding one of the scanning line driving circuits 18 so that the corresponding one of the pixel electrodes 151 is selected.
Are used as switching elements that apply the potentials of the signal lines X1 to Xn driven by the pixel electrodes 151 to the pixel electrodes 151 in the corresponding rows.

The scanning line driving circuit 18 provided in the peripheral area 104Y sequentially supplies a scanning voltage to the scanning lines Y1 to Ym, and the signal line driving circuit 1 provided in the peripheral area 104X.
9 supplies the pixel signal voltage to the signal lines X1 to Xn.

Each of the scanning line driving circuit 18 and the signal line driving circuit 19 is constituted by a complementary circuit composed of an n-channel thin film transistor and a p-channel thin film transistor. These thin film transistors are top gate thin film transistors using a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film, that is, a non-single-crystal semiconductor thin film as an active layer.

The display area 10 of the array substrate 100
2 and non-pixel portions in the peripheral area 104 (X, Y),
That is, wiring patterns such as signal lines X and scanning lines Y, T
The array substrate 10 is placed on the FT 121, the peripheral frame, and the like.
A spacer for forming a gap of about 5 μm is provided between the first substrate 0 and the counter substrate 200, thereby setting the gap between the array substrate 100 and the counter substrate 200.

The display area 102 of the opposing substrate 200 is made of a transparent conductive member that forms a potential difference between the pixel electrode 151 and a transparent insulating substrate, for example, a glass substrate having a thickness of 0.7 mm. Counter electrode 20 formed of, for example, indium-tin-oxide or ITO.
4 and an alignment film for aligning the liquid crystal composition 300 interposed between the liquid crystal composition 300 and the array substrate 100.

The counter electrode 204 includes a plurality of pixel electrodes 151.
Are set to the reference potential. An electrode transfer material, that is, a silver paste as a transfer, disposed around the substrate is provided to supply a voltage from the array substrate 100 to the counter substrate 200, and the counter electrode 204 is connected to the counter electrode drive connected via the transfer. Driven by the circuit 20.

The liquid crystal capacitance CL is formed by the liquid crystal layer 300 sandwiched between the pixel electrode 151 and the counter electrode 204. The array substrate 100 includes a pair of electrodes for forming an auxiliary capacitance CS in parallel with the liquid crystal capacitance CL. That is, the storage capacitor CS is formed by a potential difference formed between the storage capacitor electrode 61 having the same potential as the pixel electrode 151 and the storage capacitor line 52 set to a predetermined potential.

On the front and back surfaces of the liquid crystal display panel 10, that is, on the outer surfaces of the array substrate 100 and the opposing substrate 200, a polarization axis whose deflection axis is selected according to the display mode of the liquid crystal display device, the twist angle of the liquid crystal composition, and the like. Boards are provided as needed.

Next, a method of manufacturing a pixel TFT as a switching element provided in a display area of the liquid crystal display device will be described.

Such a thin film transistor is formed by the steps shown in FIGS. 3 (a) to 3 (c), FIGS. 4 and 5.

That is, as shown in FIG. 3A, an amorphous silicon thin film having a thickness of 50 nm is deposited as an amorphous semiconductor thin film on an insulating substrate, for example, a glass substrate 11 by a plasma CVD method. . Then, the glass substrate on which the amorphous silicon thin film is formed is annealed in an annealing furnace to perform a dehydrogenation process for removing hydrogen contained in the amorphous silicon thin film.

Subsequently, the entire surface of the deposited amorphous silicon thin film is irradiated with, for example, excimer laser light to melt and crystallize the amorphous silicon. Thus, a polycrystalline silicon thin film 12 having a defect level is formed.

Subsequently, the polycrystalline silicon thin film is patterned into a predetermined shape by, for example, photolithography to form an active layer 12C of the thin film transistor, a signal line contact 13 for contacting a signal line, and a pixel contact 14 for contacting a pixel electrode. To form

Subsequently, a gate insulating film 15 is formed to a thickness of 100 nm so as to cover the polycrystalline silicon thin film 12 over the entire surface of the glass substrate.
It is formed with a film thickness of.

Subsequently, as shown in FIG.
A 300 nm-thick metal film is formed over the entire surface of the gate insulating film 15 as an insulating film by a sputtering method. Then, in the first patterning step, the metal film is patterned to form the gate electrode 16 of the pixel TFT 121 and the scanning line Y integrally.

That is, in the first patterning step, first, a first photoresist is applied to the entire surface of the metal film formed on the gate insulating film 15. And this first
The photoresist is applied to the electrode shape of the gate electrode 16 and
Exposure is performed via a first photomask M1 having a pattern corresponding to the wiring shape of the scanning line Y. Then, the first photoresist is developed with a predetermined developing solution to leave a portion corresponding to the shape of the gate electrode 16 and the wiring shape of the scanning line Y and remove the other portion to expose the metal film.
Then, the exposed metal film is removed by etching with a predetermined etching solution. Then, the remaining first photoresist is removed, and a gate electrode 16 and a scanning line Y having a predetermined shape are formed.

Subsequently, as shown in FIG. 3C, the metal film which has not been completely removed on the gate insulating film 15 is patterned by a second patterning step.

That is, in the second patterning step, first, a second photoresist is applied on the metal film remaining on the gate insulating film 15 and on the exposed gate insulating film 15. Then, the second photoresist is exposed through a second photomask M2. In the present embodiment, the second photomask M2 has an electrode shape of the gate electrode 16,
And a pattern corresponding to the wiring shape of the scanning line Y.

Then, the second photoresist is developed with a predetermined developing solution to leave a portion corresponding to the shape of the gate electrode 16, the wiring shape of the scanning line Y, and the shape of the polycrystalline silicon thin film portion 12. The portion is removed to expose the metal film. Then, with a predetermined etching solution,
The exposed metal film is removed by etching. Then, the remaining second photoresist is removed.

As described above, by the first and second patterning steps, the metal film layer is etched twice by performing the patterning twice. At this time, between the region where the scanning line Y and the gate electrode 16 are formed and the region where the signal line contact 13 and the pixel contact 14 are formed, the metal film layer is surely removed by the two patternings. I have. For this reason, even if pixels are arranged at a high density and a margin between wirings, between electrodes, and between wirings and electrodes is narrowed in a plane, a short circuit between them is prevented. Can be.

For example, when patterning the scanning line Y and the gate line 16 in the first patterning step, the signal line contact 13 of the polycrystalline silicon thin film 12 and the signal line contact 13 due to the particles and the like attached to the first photomask M1. When a patterning defect in which a part of the scanning line Y extends on the pixel contact 14 occurs, in the second patterning step, the metal film layer is patterned again based on the second photomask M2. It is possible to prevent a short circuit between the signal line and the pixel electrode.

Subsequently, using the gate electrode 16 as a mask, the active layer 1 is formed using a non-mass separation type ion implantation apparatus.
Impurities are lightly implanted into both sides of 2C.

Subsequently, a resist mask is formed on a portion of the polycrystalline silicon thin film 12 adjacent to the active layer 12C, and impurities are implanted at a high concentration to form a source region 17S and a drain region 17D. Then, annealing is performed at 600 ° C. for 1 hour to activate the impurities implanted into the source region 17S and the drain region 17D.

Subsequently, an interlayer insulating film 18 having a thickness of 600 nm is formed on the gate insulating film 15 and the gate electrode 16.

Then, as shown in FIGS. 4 and 5, a polycrystalline silicon thin film 1 is formed on the interlayer insulating film and the gate insulating film.
Contact holes 19S and 19D penetrating to the second source region 17S and the drain region 17D are formed. Then, the source region 17S is formed via the contact hole 19S.
A source electrode 20S formed integrally with the signal line X and a drain electrode 2 contacting the drain region 17D via the contact hole 19D.
0D is formed.

The drain electrode 20D is connected to the pixel electrode 151 formed on the insulating film 21 such as a color filter.
They are electrically connected via contact holes.

The pixel TFT 121 formed by the steps described above can prevent a short circuit between each electrode, between each wiring, and between an electrode and a wiring. In the device, it is possible to prevent display defects from occurring.

Next, a method of manufacturing an n-channel thin film transistor and a p-channel thin film transistor used as a driving circuit provided in a peripheral area of the liquid crystal display device will be described.

Such a thin film transistor is formed by the steps shown in FIGS. 6A to 6F and FIGS. 7A to 7D.

That is, as shown in FIG. 6A, an amorphous silicon thin film having a thickness of 50 nm is deposited as an amorphous semiconductor thin film on an insulating substrate, for example, a glass substrate 31 by a plasma CVD method. . Then, the amorphous silicon thin film is annealed to perform a dehydrogenation process for removing hydrogen contained in the amorphous silicon thin film. Then, the entire surface of the amorphous silicon thin film is irradiated with, for example, excimer laser light to melt and crystallize the amorphous silicon, thereby forming a polycrystalline silicon thin film 33.

Subsequently, as shown in FIG. 6B, the polycrystalline silicon thin film 33 is formed by photolithography, for example.
Is patterned into a predetermined shape to form active layers 33a and 33b of the thin film transistor. Subsequently, the active layer 3
On the gate insulating films 35a and 33b, a gate insulating film 35 of 100 nm
It is formed with a film thickness of. Then, a metal film 36 having a thickness of 300 nm is formed on the gate insulating film 35 by sputtering.
To form

Subsequently, the metal film 36 is patterned by photolithography to form a gate electrode 36a of one of the thin film transistors.

That is, as shown in FIG. 6C, in the first patterning step, first, the first photoresist P is formed on the entire surface of the metal film 36 formed on the gate insulating film 35.
Apply R1. Then, the first photoresist PR
1 is exposed through a first photomask having a pattern corresponding to the shape of the gate electrode 36a of one of the thin film transistors. Then, the first photoresist PR
1 is developed with a predetermined developing solution to leave a portion corresponding to the shape of the gate electrode 36a of one of the thin film transistors and the shape of the other thin film transistor (a shape covering at least the polycrystalline silicon thin film of the other thin film transistor), and to leave the other portion. This is removed to expose the metal film 36.

Then, as shown in FIG. 6D, the exposed metal film is removed by etching with a predetermined etching solution, and the gate electrode 36a of one of the thin film transistors is formed.
To form

Subsequently, as shown in FIG. 6E, using the gate electrode 36a and the remaining metal film 36 as a mask, the active layer 3 is formed using a non-mass separation type ion implantation apparatus.
A p-type impurity is implanted at a high concentration on both sides of 3a to form a source region 37as and a drain region 37ad. Then, the first photoresist PR1 is removed.

Subsequently, as shown in FIG. 6F, the metal film remaining on the gate insulating film 35 is patterned by a second patterning step.

That is, in the second patterning step, first, the second photoresist P is formed on the metal film 36 remaining on the gate insulating film 35 and on the exposed gate insulating film 35.
Apply R2. Then, the second photoresist PR
2 is exposed through a second photomask having a different pattern from the first photomask. The second photomask has a pattern corresponding to the shape of the gate electrode of the other thin film transistor.

Then, the second photoresist PR2 is developed with a predetermined developing solution to correspond to the shape of the gate electrode 36b of the other thin film transistor and the shape of one of the thin film transistors (the shape covering the polycrystalline silicon thin film of at least one thin film transistor). While leaving the part
The other portions are removed to expose the metal film 36.

Then, as shown in FIG. 7A, the exposed metal film is removed by etching with a predetermined etching solution, and the gate electrode 36b of the other thin film transistor is removed.
To form

Subsequently, as shown in FIG. 7B, the gate electrode 36b and the remaining second photomask PR2 are formed.
Is used as a mask, n-type impurities are implanted at low concentration into both sides of the active layer 33b using a non-mass separation type ion implantation apparatus. Then, the second photoresist PR2 is removed.

As described above, by the first and second patterning steps, the metal film layer in at least a part of the region is etched twice by performing the patterning twice. At this time, between the region where the gate electrode 36a is formed and the region where the gate electrode 36b is formed, the metal film layer is surely removed by performing the patterning twice. For this reason,
Even when the margin between the electrodes becomes narrow, a short circuit between them can be prevented.

Subsequently, as shown in FIG. 7C, the gate insulating film 35 on which the gate electrodes 36a and 36b are formed is formed.
A third photoresist PR3 is applied thereon. Then, the third photoresist PR3 is exposed through a third photomask. The third photomask has a pattern corresponding to a shape that covers one thin film transistor and covers the gate electrode 36b of the other thin film transistor and the periphery of the gate electrode 36b.

Then, the third photoresist PR3 is developed with a predetermined developing solution.

Then, using the third photomask PR3 as a mask, an n-type impurity is implanted at a high concentration by using a non-mass separation type ion implantation apparatus to form a high-concentration impurity region 37bs.
(+) And 37bd (+) are formed, and the low-concentration impurity regions 37bs (-) and 3
7bd (−) is formed. Then, the third photoresist PR3 is removed.

Then, annealing is performed at a temperature of 600 ° C. for one hour to activate the impurities implanted into the source regions 37as and 37bs and the drain regions 37ad and 37bd.

Subsequently, as shown in FIG. 7D, an interlayer insulating film 38 having a thickness of 600 nm is formed on the gate electrodes 36a and 36b. Then, the interlayer insulating film 38
Then, a contact hole is formed in the gate insulating film 35.
Then, the source region 37 is formed through the contact hole.
as and 37bs and drain regions 37ad and 37b
d, the source electrodes 39as and 3
9bs and drain electrodes 39ad and 39bd are formed.

The thin film transistors 40a and 40b formed by the steps described above are formed as a p-channel thin film transistor and an n-channel thin film transistor, respectively.

The TFT formed as a drive circuit element formed by the above-described steps can prevent a short circuit between the respective electrodes. In a liquid crystal display device having such a drive circuit element, a drive failure occurs. Can be prevented from occurring.

[0067]

As described above, according to the present invention, it is possible to provide a method of manufacturing a thin film transistor array that can prevent display defects and drive defects from occurring.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration and an appearance of a liquid crystal display panel of a liquid crystal display device using a complementary circuit manufactured by a method of manufacturing a thin film transistor array according to the present invention as a drive circuit.

FIG. 2 is a diagram schematically showing a configuration of a liquid crystal display panel shown in FIG.

FIGS. 3A to 3C are views for explaining a method for manufacturing a thin film transistor array according to the present invention.

FIG. 4 is a diagram for explaining a method of manufacturing a thin film transistor array according to the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor shown in FIG.
It is sectional drawing at the time of cutting by the B line.

FIGS. 6A to 6F are views for explaining a method of manufacturing a thin film transistor array according to the present invention.

FIGS. 7A to 7D are views for explaining a method of manufacturing a thin film transistor array according to the present invention.

[Explanation of symbols]

 10 liquid crystal display panel 11, 31 glass substrate 12, 33 (a, b) polycrystalline silicon thin film 15, 35 gate insulating film 16, 36 (a, b) gate electrode 17s, 37 (as, bs) ... source regions 17d, 37 (ad, bd) ... drain regions 18, 38 ... interlayer insulating films 20s, 39 (as, bs) ... source electrodes 20d, 39 (ad, bd) ... drain electrodes 40 (a, b) ... Thin film transistor 100: Array substrate 102: Display area 104 (X, Y): Peripheral area 121: Pixel TFT 151: Pixel electrode 200: Counter substrate

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 JA25 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA04 KA07 KA16 KA18 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA30 MA32 MA35 MA41 NA16 NA25 A27 NA09 AA21 AA42 AA43 AA48 BA03 BA43 CA19 DA13 DB01 DB04 EA04 EA10 EB02 FA01 FB02 FB12 FB15 GB10 5F110 AA03 BB01 BB04 CC02 DD02 EE03 EE06 EE44 GG02 GG13 GG45 HJ13 HJ23 HL03 OH04 NN04 HM04

Claims (5)

[Claims] A step of forming a semiconductor layer on the substrate; a step of forming a scanning line integrally with the gate electrode on the semiconductor layer via a first insulating layer; and a step of forming the first insulating layer and the scanning. Forming a signal line on a line via a second insulating layer; and forming a scanning line integral with the gate electrode, wherein a metal film is formed on the first insulating film. And forming at least a part of the metal film by patterning at least twice. 2. A first photomask used in the patterning step has a pattern corresponding to an electrode shape of the gate electrode and a wiring shape of the scanning line, and is used after patterning based on the first photomask. 2. The method according to claim 1, wherein the second photomask has a pattern corresponding to a shape of the gate electrode, the scanning line, and the semiconductor layer. 3. 3. The thin film transistor has a source electrode and a drain electrode, and is provided between a region where the scanning line and the gate electrode are formed and a region where the source electrode and the drain electrode of the thin film transistor are formed. Is
2. The method according to claim 1, wherein the metal film formed on the first insulating film is removed by at least two patterning steps. 4. The patterning step comprises applying a first photoresist on the metal film, and applying the first photoresist through a first photomask having a pattern corresponding to an electrode shape of the gate electrode and a wiring shape of the scanning line. Exposing a first photoresist, developing the first photoresist, etching and removing the exposed metal film based on the developed first photoresist, removing the first photoresist, Applying a second photoresist on a metal film, exposing the second photoresist via a second photomask having a pattern corresponding to the shape of the gate electrode, the scanning line, and the semiconductor layer; Developing a second photoresist and etching and removing the exposed metal film based on the developed second photoresist. Method of manufacturing a thin film transistor array according to claim 1, wherein the. 5. A method of manufacturing a thin film transistor array having an n-channel thin film transistor and a p-channel thin film transistor on the same substrate, wherein the gate electrode layers of the n-channel thin film transistor and the p-channel thin film transistor are formed on the semiconductor layer by an insulating film. A step of forming a metal film through the step of etching the remaining region while leaving a region substantially equal to the electrode shape of the gate electrode of the one thin film transistor and a region including the electrode shape of the gate electrode of the other thin film transistor. A first etching step, and a second etching step of leaving a region substantially equal to the electrode shape of the gate electrode of the other thin film transistor and a region including the electrode shape of the gate electrode of one thin film transistor, and etching the other region. In the first and second etching steps, Region to be quenching, the method of manufacturing a thin film transistor array, characterized in that the at least partially overlap.