JP2001110980A - Semiconductor chip, manufacturing method thereof, semiconductor device, circuit board, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip, a method of manufacturing the semiconductor chip, a semiconductor device, a circuit board, and an electronic device, wherein semiconductor chips can be laminated using no interposers, and wherein the laminated semiconductor chips can be electrically connected independently of their size. SOLUTION: In a semiconductor chip 10, fillers 22 made of copper are attached to recesses formed so as to extend between electrode pads 20 and side surfaces 14 of the chip 10, respectively. Further, an insulating member 40 is provided except for portions of each side surface 14 to which the members 22 are exposed. As a result, the side surfaces of the chip 10 can be used for electrical connection, and thus a semiconductor device wherein semiconductor chips can be laminated without interposers can be manufactured with ease.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, a method for manufacturing the same, a semiconductor device, a circuit board, and an electronic apparatus, and more particularly to a semiconductor chip suitable for stacking a plurality of semiconductor chips.

[0002]

2. Description of the Related Art In the field of semiconductor devices, in recent years, in order to reduce the size and weight of semiconductor devices, a plurality of semiconductor chips are provided in a single package, and in particular, many semiconductor chips are provided in a stacked state. Has been developed. Such a semiconductor device is a multi-chip package (MC
P), or multi-chip module (MCM). A specific example of such a device is the invention disclosed in Japanese Utility Model Laid-Open No. Sho 62-158840. That is, a plurality of chips are stacked in a single ceramic package, and the electrodes of each chip are connected by wires. Another example is disclosed in Japanese Patent Application Laid-Open No. 11-1357.
As in the invention of No. 11, a semiconductor chip is mounted on a wiring board called an interposer, and the interposers are connected to each other and stacked to form a single semiconductor device.

[0003]

However, in the case where the size of the semiconductor chips to be stacked is substantially the same, the actual size of the semiconductor chip is as follows.
In the invention of No. 58840, bonding becomes difficult since the electrodes other than the uppermost semiconductor chip are hidden by the uppermost semiconductor chip. In the invention of Japanese Patent Application Laid-Open No. 11-135711, it is easy to stack semiconductor chips of substantially the same size to form a single semiconductor device. However, each semiconductor chip is mounted on an interposer, and the interposer is further mounted. In order to secure the electrical connection between
This requires a more complicated manufacturing process than the invention of No. 8840.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and can be stacked without interposing other members such as an interposer. It is an object of the present invention to provide a semiconductor chip, a method of manufacturing the same, a semiconductor device, a circuit board, and an electronic device that can be electrically connected without any problem.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor chip having electrodes formed thereon, wherein the semiconductor chip is connected to the electrodes and at least a part thereof is formed on a side surface of the semiconductor chip. And a conductive means formed on the substrate.

In the present invention having the above-described structure, the side surface of the semiconductor chip can be used for electrical connection, so that a semiconductor chip suitable for a multi-chip package having a configuration in which a plurality of semiconductor chips are stacked can be provided.

In the above-mentioned semiconductor chip, the conductive means is made of a conductive filler filled in a recess formed over the side surface and the active element forming surface of the semiconductor chip. .

In the present invention having such a configuration, the electrodes can be connected to both the active element forming surface (hereinafter referred to as the active surface) and the side surface of the semiconductor chip.

In the above-mentioned semiconductor chip, an insulating film is formed on an inner surface of the recess.

[0010] In the present invention having such a configuration, it is possible to reliably insulate the filler from the active elements of the semiconductor chip and the metal wiring layer.

The material of the insulating film is a silicon oxide film (SiO ₂ ) which can be easily formed on the inner surface of the recess.
Alternatively, a silicon nitride film (SiN) is preferable.

Further, in the above-mentioned semiconductor chip, an insulating film is formed on a portion other than the filler on the side surface.

According to the present invention, the active elements and the metal wiring layers of the semiconductor chip can be reliably insulated and protected.

Further, in the above-mentioned semiconductor chip, a conductive material is formed on the insulating film formed on the side surface.

In the present invention thus configured, the side surfaces of the semiconductor chip can be appropriately used for electrical connection.

Further, in the above-mentioned semiconductor chip, the conductive material is connected to the electrode.

In the present invention configured as described above, the semiconductor chip can be electrically connected to an arbitrary portion on the side surface of the semiconductor chip.

Further, in the above-mentioned semiconductor chip, the semiconductor chip comprises a conductive material formed on a side surface of the semiconductor chip, and a second conductive material connecting the electrode and the conductive material. To do.

In the present invention configured as described above, the side surface of the semiconductor chip can be appropriately used for electrical connection.

Further, in the above-mentioned semiconductor chip, the conductive material is formed on an insulating film formed on the side surface.

According to the present invention having such a configuration, it is possible to reliably insulate the conductive material from the active elements and the metal wiring layers of the semiconductor chip.

The semiconductor device is characterized in that any one of the above-mentioned semiconductor chips is laminated in a plurality of layers.

In the present invention configured as described above, the semiconductor chips that can be electrically connected to each other on the side surface are stacked, so that semiconductor chips of substantially the same size can be stacked, and a semiconductor chip such as an interposer can be stacked. Auxiliary means for connecting in a stacked state is not required.

In the above semiconductor device, at least one of the electrode and the conductive material of the stacked semiconductor chips is connected by a connecting member provided on a side of the semiconductor chip. did.

In the present invention configured as described above, electrical continuity between the stacked semiconductor chips can be easily ensured.

In the above-mentioned semiconductor device, the connection member is a wire.

In the present invention configured as described above, the semiconductor chip can be electrically connected by a generally used bonder, so that the manufacturing cost can be reduced.

In the above-described semiconductor device, the connection member is a wiring pattern formed on a substrate.

In the present invention configured as described above, the semiconductor device can be mounted only by connecting the side surfaces of the stacked semiconductor chips to the wiring pattern, that is, by attaching the semiconductor chips to the substrate.

In addition, the present invention is characterized in that any one of the above semiconductor devices is mounted on a circuit board.

In the present invention configured as described above, since the mounting area required for the above-described semiconductor device is equivalent to a bare chip, it is possible to provide a circuit board that is smaller than the conventional one.

Further, an electronic device is provided with the above-mentioned circuit board.

In the present invention configured as described above, since the circuit board smaller than the conventional one is used, it is easy to reduce the size of the electronic device itself.

In the method of manufacturing a semiconductor chip having electrodes formed thereon, a step of forming a recess in an electrode provided on a first surface of a semiconductor wafer having the semiconductor chip formed thereon; Forming an insulating film on the inner surface of the semiconductor device, filling the recessed portion with a conductive filler, and forming the first surface on each of the semiconductor chips,
Forming a groove so that at least a part of the filler is cut off, filling the groove with an insulating material, and exposing at least the insulating material to the second surface of the semiconductor wafer. The method includes at least a step of grinding, a step of cutting the semiconductor wafer for each semiconductor chip, and a step of removing the insulating material covering the filler.

According to the present invention configured as described above, it is possible to easily manufacture a semiconductor chip that can be electrically connected to the side surface.

In the above method of manufacturing a semiconductor chip, a step of forming a conductive material on an inner surface of the groove before filling the groove with an insulating material; and a step of cutting the semiconductor wafer into each of the semiconductor chips. Removing the insulating material covering the conductive material.

In the present invention configured as described above, the conductive material is formed on the side surface of the semiconductor chip, and the conductive material is covered to easily remove the insulating material.

Further, in the above method for manufacturing a semiconductor chip, the conductive material is formed by plating.

In the present invention configured as described above, the conductive material can be easily formed at low cost.

In the above method for manufacturing a semiconductor chip, the groove is formed so that its depth is equal to or greater than the thickness of the cut semiconductor chip.

In the present invention configured as described above, by cutting the insulating material after grinding the semiconductor wafer, the semiconductor wafer can be easily cut for each semiconductor chip.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a wiring board, a method of manufacturing the same, a semiconductor device, a circuit board, and electronic equipment according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is an explanatory view of a semiconductor chip according to a first embodiment of the present invention, wherein (1) is a perspective view of the semiconductor chip, and (2) is a partially enlarged perspective view near an electrode. is there. FIGS. 2A and 2B are explanatory diagrams of a semiconductor chip according to a second embodiment of the present invention. FIG. 2A is a perspective view of the semiconductor chip, and FIG. 2B is a partially enlarged perspective view of the vicinity of the electrodes. . FIG. 3 is a perspective view showing a modified example of the conductive material according to the second embodiment of the present invention. FIGS. 4A and 4B are explanatory views of a semiconductor chip according to a third embodiment of the present invention. FIG. 4A is a perspective view of the semiconductor chip, and FIG. 4B is a partially enlarged side view near the electrodes. . FIG. 5 is an explanatory diagram of a semiconductor device in which semiconductor chips according to a second embodiment of the present invention are stacked, (1) is a side view of a semiconductor chip connected by wires, and (2) FIG. 3 is a side view of the components connected by a substrate. FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor chip according to the embodiment of the present invention. FIG. 7 is an explanatory diagram of a manufacturing process of the semiconductor chip according to the embodiment of the present invention. FIG. 8 is an explanatory diagram of a manufacturing process of the semiconductor chip according to the embodiment of the present invention.
FIG. 9 is an explanatory diagram of an electronic apparatus including a circuit board on which the semiconductor device according to the embodiment of the present invention is mounted.
FIG. 10 is an explanatory diagram of a computer including the semiconductor device according to the embodiment of the present invention.

First, a first embodiment of the present invention will be described. As shown in FIG. 1A, in a semiconductor chip 10 according to the present embodiment, a filler 22 is filled in a recess provided over an electrode pad 20 and a side surface 14 of the semiconductor chip 10. An insulating film (not shown) is formed on the inner surface of the recess. Further, as shown in FIG. 1 (2), an insulating material 40 is provided except for a portion of the side surface 14 where the filler 22 is exposed. The filler 22 has its upper end connected to the electrode pad 20. The filler 22 is made of copper (Cu) and has conductivity. The insulating material 40 is made of BCB (Benzocyclobute).
ne) and has insulating properties. Note that the electrode 12 may be aluminum (Al), aluminum-silicon (Al-Si), copper, aluminum-silicon-copper (Al-Si-Cu), or any other electrode commonly used as an electrode or wiring. Any material may be used.

The material of the filler 22 may be any material having conductivity, such as gold (Au), which can be easily filled into the recess by the method described later.
A metal such as solder or a metal paste (conductive paste) is preferable. Alternatively, low-resistance polycrystalline silicon may be filled. Further, the material of the insulating material 40 is not limited to BCB, but may be another epoxy resin. further,
Other resins may be used as long as they have good adhesion to the semiconductor chip body 12. In addition, inorganic SOG, organic SOG
But it is good.

Therefore, in the semiconductor chip 10 according to the first embodiment, the filler 22 can be electrically connected to the outside together with the electrode pad 20, and the filler 22 is closer to the side surface 14 of the semiconductor chip 10. If the portion exposed to the side is used, it is possible to electrically connect from the side surface 14 side. In addition, since the side surface 14 is provided with the insulating material 40 except for the portion where the filler 22 is exposed, insulation between the adjacent fillers 22 can be ensured.
Insulation with active elements and metal wiring layers inside the semiconductor chip 10 can be ensured. Since an insulating film is formed on the inner surface of the recess provided with the filler 22, it is possible to prevent the leakage current from flowing from the filler 22 to the above-described active elements and the like.

The electrode pad 20 may be provided with a through hole, and the through hole may be filled with the filler 22. In this case, the filler 22 is exposed in a wider area on the side surface of the semiconductor chip body 12, so that it is easier to ensure electrical conduction. In addition, since the tip of the filler 22 is also exposed on the back surface of the active surface (not shown), electrical connection is possible on all of the active surface, side surface 14 and back surface of the semiconductor chip body 12.

The filler 2 in the active surface and the side surface 14
An insulating film for protecting the portion may be formed on the surface where 2 is not exposed or on the rear surface by a method such as potting, vapor deposition, or transfer molding. This insulating film
Silicon oxide film (SiO ₂ ) or silicon nitride film (Si
N) is most preferred. Furthermore, in order to improve the connectivity between the electrode pad 20 and / or the filler 22 and an external device, the electrode pad 20 and / or the filler 22 may be soldered,
The protrusion may be formed of a metal such as gold or copper, or a composite material thereof, or an organic conductive material such as a conductive paste. In addition, in FIG. 1, the semiconductor chip 10
An example in which the electrode pads 20 are provided on two opposing sides has been described as an example.
May be provided.

Next, a process for forming the connection hole and the conductive material according to the first embodiment will be described with reference to FIGS. The following steps are performed after pattern formation on a semiconductor wafer.

First, FIG. 6A shows a cross section of the electrode pad 20 cut off near the center.

First, as shown in FIG. 6B, a recess 24 is formed in the electrode pad 20 by using a laser beam. The recess 24 is formed so that the opening of the recess 24 is surrounded by the electrode pad 20, that is, in the electrode pad 20, in order to ensure the electrical connection between the filling material described later and the electrode pad 20. Although it is preferable to provide it, it may be provided so that only a part of the opening is in contact with the electrode pad 20. In any case, it is preferable to form the active element and the metal wiring layer formed inside the semiconductor chip 10 at a position where they are not damaged. Further, it is preferable that the depth of the concave portion 24 is sufficient to secure the surface area of the filler described later.

The recess 24 may be formed by wet etching or dry etching. In the case of the etching method, a longer time is required for perforation than the method using a laser beam, but the possibility of damaging active elements inside the semiconductor chip 10 is small. As another specific etching method, a method used in silicon processing such as a method using an alkaline solution such as KOH for wet etching, a method using an etching gas such as CF _{4 for} dry etching, and a method using plasma may be used. You can do it.

Next, as shown in FIG.
The insulating film 26 is formed on the inner surface of the substrate 4. The insulating film 26 is formed by forming a silicon oxide film on the inner surface of the recess 24 by a thermal oxidation method. The active surface 1 of the semiconductor chip 10
In general, a silicon oxide film as a protective film is formed on the surface of the active surface 12, so that the formation of the silicon oxide film on the inner surface of the recessed portion involves forming the protective film on the active surface 12. It is preferable to perform it at the same time. Further, it is preferable that the heating temperature during the thermal oxidation be in a range where the metal wiring layer formed inside the semiconductor chip is not melted.

The method of forming the protective film 26 is not limited to the thermal oxidation method, but may be any method such as a CVD method as long as it can form a silicon oxide film. Further, a silicon nitride film may be formed instead of the silicon oxide film.

Next, as shown in FIG.
4 is filled with a filler. That is, the recess 22 is filled with the filler 22 by applying a photoresist (not shown) and subsequently performing plating. After filling the filler 22, the photoresist (not shown) is removed. The material of the filler 22 may be any material such as solder, gold (Au), and copper (Cu) as long as it is suitable for the plating method. Further, it may be formed by a method other than the plating method, for example, printing. In this case, the material of the conductive material 16 is a metal such as aluminum or solder, or a composite material thereof,
Alternatively, an organic conductive material such as a conductive paste may be used.

Further, a method of cutting the semiconductor wafer on which the filler is formed in the above steps for each semiconductor chip will be described.

First, FIG. 7A shows a part of a cross section of the semiconductor wafer 16 and shows a cross section in which the electrode pad 20 is cut off near the center similarly to FIG. The range indicated by the symbol A indicates a range formed as one semiconductor chip. Although not specifically shown, the same configuration as the portion indicated by the reference numeral A is formed for each portion of the semiconductor wafer 16 other than the reference numeral A, which is one semiconductor chip.

First, as shown in FIG. 7B, the semiconductor wafer 16 is half-cut for each semiconductor chip by a dicer. At this time, the cut groove 28 is formed so that a part of the filler 22 is also cut. The depth of the cut groove 28 is set to be equal to or greater than the thickness of the semiconductor chip after the grinding step described later. Due to the formation of the cut groove 28, a part of the filler 22 is exposed on the inner surface of the cut groove 28. Note that the half-cutting method is not limited to the dicing method using a dicer. If the electrode 20 and the filler 22 can be half-cut together with the semiconductor wafer 16, the half-cutting may be performed by dry etching or wet etching. May be. In the case of using the etching method, an etching gas, an etching solution, or the like may be switched for each etching target.

Next, as shown in FIG.
Is filled with an insulating material 40. The insulating material 40 is made of a resin such as BCB as described above, and is filled with a squeegee. The filling method is not limited to a method using a squeegee, but may be any method as long as the insulating material 40 can be filled. After the filling, the insulating material 40 is cured by a method according to the filled insulating material 40, for example, by heating or irradiating ultraviolet rays.

Next, as shown in FIG. 7D, the semiconductor wafer 16 is ground from the back side by a lapping apparatus. At this time, grinding is performed until the insulating material 40 is exposed. As a result, the semiconductor wafer 16 is divided into individual semiconductor chips 10, and these semiconductor chips 10 are bonded to each other by an insulating material 40 formed around the semiconductor chips.

Next, as shown in FIG. 7E, the insulating material 40 is fully cut for each semiconductor chip by a dicer. By this dicing, each semiconductor chip 10 is separated. The thickness of the insulating material 40 remaining on the side surface of the semiconductor chip 10 without being diced is determined between the fillers 22 or between the active element or the metal wiring layer inside the semiconductor chip 10 and the external connected to the filler 22. Preferably, it is sufficient to ensure insulation from the device.
Note that the method of full cutting is not limited to the method of dicing with a dicer, and if the insulating material 40 can be fully cut, half cutting may be performed by dry etching or wet etching.

The above steps are all wafer processes, and processing for each semiconductor chip can be performed collectively.

Next, as shown in FIG.
With respect to the side surface 14 to which 0 is attached on the entire surface, a portion of the insulating material 40 attached to the filler 22 is removed by etching. As a result, as shown in FIG.
Is exposed, so that the exposed part is connected to an external device (not shown).
And the like, the electrical connection between the semiconductor chip 10 and an external device becomes possible.

Further, a second embodiment of the present invention will be described. As shown in FIGS. 2A and 2B, the conductive material 30 is provided on the side surface 14 of the semiconductor chip 10 in the configuration described in the first embodiment. The conductive material 30 is provided so as to cover a part of the filler 22 exposed on the side surface 14 side and the periphery thereof. Note that the insulating material 40 is not provided below the conductive material 30. The conductive material 30 is formed of copper. Therefore,
The filler 22 is electrically connected to the electrode pad 20.

Further, the conductive material 30 is
A photoresist is provided on a portion where the conductive material 30 is not formed,
Subsequently, copper is attached to a portion where no photoresist is provided by a plating method. The material of the conductive material 30 may be any material such as solder, gold (Au), or copper (Cu) as long as it is suitable for the plating method. Further, it may be formed by a method other than the plating method, for example, printing. In this case, the material of the conductive material 16 is a metal such as aluminum or solder, or a composite material thereof,
Alternatively, an organic conductive material such as a conductive paste may be used.

Therefore, in the semiconductor chip 10 according to the second embodiment, the same operation and effects as those of the first embodiment are obtained, and the provision of the conductive material 30 provides electric connection. Since the area of the portion is increased, electrical connection on the side surface of the semiconductor chip can be more easily performed than that according to the first embodiment.

The conductive material 30 may cover all of the filler 22 exposed on the side surface 14 of the semiconductor chip 10. Further, any shape may be used as long as the adjacent conductive materials 30 do not contact each other. For example, as shown in FIG. 3, the conductive material 32 may be formed so as to extend in the circumferential direction of the semiconductor chip 10, or the conductive material 34 may be provided so as to straddle the two side surfaces 14. In this way, the site for electrical connection can be set freely.

In the same manner as in the first embodiment, potting, vapor deposition, transfer molding, or the like is performed on the active surface (not shown), the side surface 14 where the filler 22 is not exposed, or the back surface (not shown). An insulating film for protecting the portion may be formed by a method. In addition, the electrode pad 20 and / or the filler 22 and / or the conductive material 3
In order to improve the connectivity between the electrode pad 20 and an external device, the electrode pad 20 and / or the filler 22 and / or the conductive material 30 may be plated, printed, or mounted on a ball by a method such as ball mounting.
The protrusion may be formed of a metal such as solder, gold, or copper, or a composite material thereof, or an organic conductive material such as a conductive paste.

Next, a third embodiment of the present invention will be described. As shown in FIG. 4A, the semiconductor chip 10
Is provided with a first conductive material 36 which is connected to the electrode pad 20 and whose end is positioned along the edge of the active surface 12 of the semiconductor chip 10. Furthermore, a second conductive material 38 whose upper end is connected to the first conductive material 36 is provided on the side surface 14 of the semiconductor chip 10. Further, the first conductive material 36 and the second conductive material 38 are formed of copper. Therefore, the second conductive material is electrically connected to the electrode pad 20.

The first conductive material 36 and the second conductive material 3
8 has a conductive material 30 on the active surface 12 and the side surface 14.
Is formed on a portion where no photoresist is formed, and then copper is adhered to a portion where no photoresist is provided by a plating method. The material of the conductive material 30 may be solder, gold (A) if it is suitable for the plating method.
u), copper (Cu) and the like. Also,
It may be formed by a method other than the plating method, for example, printing. In this case, the material of the conductive material 16 may be a metal such as aluminum or solder, a composite material thereof, or an organic conductive material such as a conductive paste. Further, the first conductive material 36 and the second conductive material 38 may be formed by different materials and forming methods.

Therefore, in the semiconductor chip 10 according to the second embodiment, only the first conductive material 36 and the second conductive material 38 are added to the conventional semiconductor chip, and the semiconductor Electrical connection to the chip 10 can be made. In addition, there is no need for a process such as providing a recess in the semiconductor chip 10.

Similarly to the first and second embodiments, an insulating film for protecting the relevant portion may be formed on the active surface 12, the side surface 14, or the back surface by a method such as potting, vapor deposition, or transfer molding. good. In addition, the first
In order to improve the connectivity between the conductive material 36 and / or the second conductive material 38 and an external device, a method such as plating, printing, and mounting a ball on the first conductive material 36 and / or the second conductive material 38 Thus, a protrusion may be formed of a metal such as solder, gold, or copper, a composite material thereof, or an organic conductive material such as a conductive paste.

Further, an example of a semiconductor device using the semiconductor chip according to the above embodiment will be described.

FIG. 5A shows a semiconductor device 100 formed by stacking five layers of semiconductor chips 10 according to the second embodiment. The stacked semiconductor chips 10 are bonded to each other by an adhesive 56, and in addition, the respective conductive members 30 are connected by wires 50. Furthermore, it is connected to an external device (not shown) by an external connection wire. Note that the wire 50 is formed of gold. The adhesive 56 is
Any material may be used as long as it uses an insulating resin such as an epoxy resin.

Therefore, even when semiconductor chips of the same size are stacked, the semiconductor device 100 can be easily interconnected by using the conductive material 30 provided on the side surface, and can be connected to an external device. External connection wire 60
Can be easily done via Further, it is not necessary to use an auxiliary means such as an interposer for interconnecting the semiconductor chips 10.

The number of semiconductor chips to be stacked is not limited to five, and any number of semiconductor chips may be stacked as much as possible. Further, the material of the wire 50 is not limited to gold, and other metals such as aluminum may be appropriately used. Alternatively, a configuration may be adopted in which a heat sink is sandwiched between the semiconductor chips 10 and stacked. further,
In the above example, the connection between the semiconductor chips 10 and the connection with the external device are performed by wires. However, the connection may be performed by another method such as forming a wiring pattern by printing or attaching a heat seal. good. Further, the semiconductor chips 10 are stacked with the back surface facing upward,
An electrode formed on the active surface of the semiconductor chip 10 located at the lowermost layer may be used for connection with an external device. In the case of this configuration, it is not necessary to provide the external connection wire 60.

FIG. 5B shows a semiconductor device 100 in which the semiconductor chips 10 according to the second embodiment are stacked over five layers and connected to a wiring board 58. Each semiconductor chip 10 is adhered by an adhesive 56. In addition, each conductive material 30 is attached to a wiring pattern 54 of a wiring board 58 disposed above and below the semiconductor chip. The stacked semiconductor chips 10 are bonded to each other by an adhesive 56. The semiconductor chip 10 and the wiring board 58
It is adhered with a conductive adhesive material 62.

The material of the substrate 52 of the wiring substrate 58 is
Either an organic material or an inorganic material may be used. Examples of the organic material include polyimide, polyester, and polysulfone resin, and examples of the inorganic material include silicon, glass, and metal. In the wiring board according to the present invention, any of organic or inorganic materials may be used, or a combination of both materials may be used.

The anisotropic conductive adhesive material 62 may be a sheet (ACF) or a paste (ACF).
P) may be used. Further, the conductive material 30 and the wiring pattern 5
A conductive member such as a solder, a brazing material, or an anisotropic conductive adhesive may be arranged only between the first and fourth members, and the other portions may be covered with a resin. Further, an adhesive 56 may be used instead of the anisotropic conductive adhesive material 62. In this case, since the conductive particles are not present, the reliability of the electrical connection between the semiconductor chips is slightly reduced, but the cost is lower than in the case of using an anisotropic conductive adhesive material. In addition, the bumps formed on the wiring pattern 54 may be connected to the conductive material 30. Alternatively, a configuration may be adopted in which a heat sink is sandwiched between the semiconductor chips 10 and stacked.

As described above, in the semiconductor device according to the embodiment of the present invention, when a plurality of semiconductor chips are stacked to form one semiconductor device, the electrical connection between the stacked semiconductor chips is established. The steps for performing are facilitated. In addition, the mounting area can be reduced. In addition, in one semiconductor device, the configuration illustrated in FIG. 5A and the configuration illustrated in FIG. 5B may be used in combination. Further, the semiconductor chip according to the first or third embodiment may be used for the above-described semiconductor device. Furthermore, one semiconductor device may be configured by appropriately combining the semiconductor chips according to the above-described embodiments.

FIG. 9 shows a circuit board 1000 on which a semiconductor device 1100 according to the embodiment of the present invention is mounted. For the circuit board 1000, an organic substrate such as a glass epoxy substrate is generally used. On the circuit board 1000, a bonding portion made of, for example, copper is formed so as to form a desired circuit. Then, by electrically connecting the bonding portion and the external electrode of the semiconductor device 1100, their electrical continuity is achieved.

Since the mounting area of the semiconductor device 1100 can be reduced to the area for mounting with bare chips, the size of the electric equipment itself can be reduced by using the circuit board 1000 for electronic equipment. Further, in the same area, more mounting space can be secured, and higher functionality can be achieved.

FIG. 10 shows a notebook personal computer 1200 as an electronic apparatus having the circuit board 1000.

[0084]

As described above, according to the present invention, in a semiconductor chip having an electrode formed thereon, the semiconductor chip is connected to the electrode and at least a part is formed on a side surface of the semiconductor chip. Since the semiconductor device has a configuration having conductive means, the semiconductor chips can be electrically connected only by stacking the semiconductor chips and electrically connecting the conductive means, so that the semiconductor chips are electrically connected to each other. Can be simplified. In addition, since the layers can be stacked without using an interposer, the semiconductor device can be downsized and the cost of the semiconductor device can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a semiconductor chip according to a first embodiment of the present invention, (1) is a perspective view of the semiconductor chip, and (2) is a partially enlarged perspective view near an electrode.

FIGS. 2A and 2B are explanatory diagrams of a semiconductor chip according to a second embodiment of the present invention; FIG. 2A is a perspective view of the semiconductor chip; FIG.

FIG. 3 is a perspective view showing a modified example of the conductive material according to the second embodiment of the present invention.

FIG. 4 is an explanatory view of a semiconductor chip according to a third embodiment of the present invention, wherein (1) is a perspective view of the semiconductor chip, and (2) is a partially enlarged side view near an electrode.

FIG. 5 is an explanatory view of a semiconductor device in which semiconductor chips according to a second embodiment of the present invention are stacked, (1) is a side view of a semiconductor chip connected by wires, and (2)
FIG. 3 is a side view of the components connected by a substrate.

FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor chip according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a semiconductor chip manufacturing process according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a semiconductor chip manufacturing process according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram of an electronic apparatus including a circuit board on which the semiconductor device according to the embodiment of the present invention is mounted.

FIG. 10 is an explanatory diagram of a computer including a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Active surface 14 Side surface 16 Semiconductor wafer 18 Adjacent semiconductor chip 20 Electrode pad 22 Filler 24 Depression 26 Insulating film 28 Cut groove 30 Conductive material 32 Conductive material 34 Conductive material 36 First conductive material 38 Second conductive material REFERENCE SIGNS LIST 40 insulating material 42 opening 50 wire 52 substrate 54 wiring pattern 56 adhesive 58 wiring substrate 60 external connection wire 62 conductive adhesive material 100 semiconductor device 1000 circuit substrate 1100 semiconductor device 1200 notebook personal computer

Claims (19)

[Claims] 1. A semiconductor chip having electrodes formed thereon, the semiconductor chip having conductive means connected to the electrodes and having at least a part formed on a side surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the conductive means is made of a conductive filler filled in a recess formed over the side surface and the active element forming surface of the semiconductor chip. 2. The semiconductor chip according to 1. 3. The semiconductor chip according to claim 2, wherein an insulating film is formed on an inner surface of the recess. 4. The semiconductor chip according to claim 1, wherein an insulating film is formed on a portion other than the filler on the side surface. 5. The semiconductor chip according to claim 4, wherein a conductive material is formed on said insulating film formed on said side surface. 6. The semiconductor chip according to claim 4, wherein said conductive material is connected to said electrode. 7. The conductive means comprises: a conductive material formed on a side surface of the semiconductor chip; and a second conductive material connecting the electrode and the conductive material. The semiconductor chip according to claim 1. 8. The semiconductor chip according to claim 7, wherein said conductive material is formed on an insulating film formed on said side surface. 9. The semiconductor chip according to claim 5, wherein the insulating material is formed of a resin. 10. A semiconductor device comprising a plurality of the semiconductor chips according to claim 1 stacked on each other. 11. The semiconductor according to claim 10, wherein at least one of the electrode or the conductive material of the stacked semiconductor chips is connected by a connecting member provided on a side of the semiconductor chip. apparatus. 12. The semiconductor device according to claim 11, wherein said connection member is a wire. 13. The semiconductor device according to claim 11, wherein said connection member is a wiring pattern formed on a substrate. 14. A circuit board on which the semiconductor device according to claim 10 is mounted. 15. An electronic apparatus comprising the circuit board according to claim 14. 16. A method of manufacturing a semiconductor chip having electrodes formed therein, wherein a step of forming a recess in an electrode provided on a first surface of a semiconductor wafer on which the semiconductor chip is formed; Filling the first surface with a conductive material, forming a groove in the first surface for each of the semiconductor chips, and cutting off at least a part of the filler. Filling an insulating material into the semiconductor wafer; grinding the second surface of the semiconductor wafer at least until the insulating material is exposed; cutting the semiconductor wafer into individual semiconductor chips; and covering the filler material And a step of removing the insulating material. 17. A step of forming a conductive material on an inner surface of the groove before filling the groove with an insulating material; and forming the conductive material on the semiconductor wafer after cutting the semiconductor wafer into individual semiconductor chips. 17. The method for manufacturing a semiconductor chip according to claim 16, further comprising: removing a material. 18. The method according to claim 17, wherein the conductive material is formed by plating. 19. The semiconductor chip according to claim 16, wherein said groove is formed so that its depth is equal to or greater than the thickness of said cut semiconductor chip.