JP2001109785A - Method for designing pass transistor logical circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design technique of a high speed pass transistor logical circuit with a small circuit scale, by which power consumption is low. SOLUTION: (1) The appearance frequency of an input pair to be inputted to the same gate of the logical circuit is calculated and inputs are made into a group based on the result. (2) Optimum order for Shannon expansion is decided by input group unit. (3) Optimum input signal order for Shannon expansion in the same input group is decided based on a signal transition probability. (4) Shannon expansion is executed in input signal order concerning the logical circuit. (5) A binary decision diagram corresponding to the logical circuit is generated. (6) Each node in the diagram is replaced with a two-input selector circuit by a pass transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for automatically designing a circuit such as an LSI, and more particularly to a logic design at a stage which does not depend on a process technology for generating a pass transistor logic circuit based on a description of a circuit function.

[0002]

2. Description of the Related Art Recently, a CMO that has been widely used
S (Complementary metal-oxi)
de semiconductor, faster than logic,
Pass transistor logic, which has features of low power consumption and small area, has attracted attention.

On the other hand, in order to cope with an increase in the design man-hour of an LSI which is becoming large-scale, an LSI is described using a hardware description language.
A top-down design method for describing a function of a logic circuit automatically and automatically designing a logic circuit using an automatic logic synthesizer has become widespread. The automatic logic synthesis technology based on the function description is a key technology of this top-down design method, and has been intensively researched and developed.

As the top-down design method has become widespread as described above, even if the above-mentioned pass transistor logic is
Even if it has better characteristics than OS logic, if it cannot be automatically designed and must be carefully designed by hand, it cannot be widely used as logic design technology. It is considered that only the special circuit is used.

Therefore, it is essential to establish an automatic design technique for improving the performance and reducing the cost of an LSI by utilizing the excellent characteristics of the pass transistor logic.

As an example of a conventional pass transistor logic design method, for example, “Lean Integration”
n: Achieving a Quantum Le
apin Performance and Cost
of Logic LSIs "(IEEE 1994)
Custom Integrated Circuit
ts Conference) and JP-A-9-6821.

Hereinafter, the design procedure described in the above document will be described.

First, a binary decision diagram is generated from a logical specification expressed in a hardware description language or the like.

Next, the nodes of the binary decision graph are replaced with pass transistors to form a transistor network.

Next, a buffer for the purpose of restoring the potential level and amplifying the current is inserted into an appropriate place in the network (however, this procedure is not directly related to the present invention).

Next, a prepared lean cell (a basic circuit for a pass transistor circuit having a structure in which NMOS pass transistors are connected in a tree shape and a buffer is arranged at the output) is allocated to the generated circuit, and a netlist is output. (This procedure is also not directly related to the present invention).

Of the above processes, the first two steps are technology-independent processes that do not depend on a specific cell library, and the last two steps are technology-dependent processes.

In order to actually perform the above procedure efficiently, an apparatus combining a CPU, a memory, a dictionary (such as a database), a keyboard, a CRT and the like has been developed. In addition, it is a man / machine system that is operated and modified by a person as needed. However, this is a well-known technique described in, for example, the above-mentioned Japanese Patent Application Laid-Open No. Hei 9-6821, and if the general design of the pass transistor, the principle and concept of the invention, and the functions and functions of each device are understood. There is no particular difficulty in manufacturing, realizing, or implementing both hardware and software. Therefore, their description is omitted.

Similarly, in the embodiment of the present invention, a specific description of hardware and software of an apparatus for carrying out the embodiment is omitted.

[0015]

Among the above-mentioned conventional design procedures, there are the following problems in technology-independent processing. (1) Low power consumption With the advance of semiconductor integrated circuit technology, the number of elements that can be integrated on one chip exceeds several million, and as a result, heat generation of LSI has become a serious problem. Also, with environmental changes such as intensified competition accompanying the expansion of the market for portable devices, reducing power consumption of LSIs has become an important issue.

The same applies to a pass transistor logic characterized by lower power consumption than CMOS.

On the other hand, if the design method is such that the binary decision diagram (BDD) is simply generated from the logical specification and each node of the graph is replaced with a pass transistor, as in the above-described conventional method, finally, The configuration of the generated circuit largely depends on the configuration of the intermediately generated BDD. The number of logic stages between the input and output of the pass transistor circuit depends on the number of node stages between the input and output of the BDD. The latter strongly depends on the input signal order in the Shannon expansion process when generating the BDD.

By the way, some input signals change frequently (high transition frequency) and others do not change much (low transition frequency). In the path between the input signal with high transition frequency and the output, In many cases, the included internal signals have a high transition frequency. For this reason, in the case of such a circuit having a large number of logic stages between an input and an output having a high transition frequency, the power consumption increases. (2) Speed-up Although the pass transistor logic is said to be faster than the CMOS logic, the actual performance of the circuit is often determined by the delay of a specific critical path. For this reason,
No matter how many paths are on average faster than a CMOS circuit, if the delay of a particular critical path is large, the performance of the entire circuit will be reduced.

As described above, in the conventional design method using the BDD, the number of logic stages between the input and output of the pass transistor circuit depends on the number of nodes between the input and output of the BDD. It strongly depends on the input signal order in Shannon expansion processing. Therefore, if the input signal serving as the critical path is processed later in the Shannon expansion processing when generating the BDD, or if such a circuit is used, the number of logic stages of the critical path increases, The delay becomes large as a whole circuit. (3) Circuit Size Reduction In the conventional design method in which each node of the generated BDD is replaced with a pass transistor, the finally generated circuit size largely depends on the size of the BDD. On the other hand, it is known that the size of BDD depends on the input signal order in Shannon expansion processing. Therefore, in order to reduce the circuit scale, it is necessary to optimize the input signal order. However, this is a problem that is difficult to determine.
Minimization of Minute Decision Diagram "(Technical Report CO of the Institute of Information and Communication Engineers CO
As described in MP91-15 P27), at present, when the number of inputs exceeds about 17, no effective method for strict optimization is known.

On the other hand, in an actual circuit, the number of input signals slightly exceeds 100. For this reason, it is impossible to strictly optimize the input signal sequence of an actual circuit. As a result, the size of the BDD is inevitably larger than the optimum size, and the final circuit scale is also increased.

For this reason, a perfect transistor logic design method which is excellent in terms of low power consumption, high speed, and small circuit scale by some means, and which can be automated as much as possible and which is versatile even if a complete method is impossible. The development of was desired.

[0022]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above problems, and it is possible to group input signals based on their characteristics and experiences, which is effective for achieving the object. It focuses on that there is.

Specifically, the following is performed.

According to the first aspect of the present invention, in a method of designing a pass transistor logic circuit based on a logic specification of a given circuit, characteristic operations and processes are performed in each unique step as described below. .

In the appearance frequency calculation step, the appearance frequency is calculated by a predetermined procedure such as counting the appearance frequencies of input pairs that enter the same gate of the logic circuit one by one. In the grouping step, the input signals are grouped based on the calculated appearance frequency and, in some cases, also taking into account empirical rules and the like. In the optimal order determination step for each group, based on signal transition probabilities due to simulations, etc., for each input signal grouped,
Further, in some cases, the optimal order for Shannon expansion is determined in consideration of empirical rules and simple guesswork.

In the optimum input signal order determination step, the optimum input for Shannon expansion (or when performing Shannon expansion) is also based on the signal transition probability and the like in the same input group for which the optimum order has been determined. Determine the signal deployment order. In a binary decision diagram generation step, a Shannon expansion is applied to the logic circuit in the order of the input signals to generate a binary decision diagram corresponding to the logic circuit.

As a result, of the inputs of the circuit, logically related inputs are continuously Shannon-expanded, so that the number of nodes of the obtained binary decision graph is reduced and the circuit scale is reduced. Become. Further, since the distance from the input signal having a high transition probability to the output is reduced, the power consumption is also reduced.

It should be noted that, as a precautionary measure, it is needless to say that a buffer is inserted as necessary, and finally a test is performed in some form. This is the same in the inventions of the other claims.

According to the second aspect of the present invention, in the method of designing a pass transistor logic circuit based on a given logic specification of a circuit, the following characteristic processing is performed in each unique step.

In the appearance frequency calculation step, the appearance frequency of a pair of input signals entering the same gate of the logic circuit is calculated by a predetermined means such as a program created in consideration of the characteristics of the processing object. In the grouping step, the input signals are grouped on the basis of the calculated appearance frequency and taking into account empirical rules as necessary. In the distance calculation step, the distance from the input terminal to the output terminal of each input signal of the logic circuit having at least a delay constraint is calculated by a predetermined procedure. In the group unit distance calculation step, for a group having at least a delay-constrained input signal, a distance from each input group to an output is calculated based on the calculated distance between each input and output of each input signal having a delay constraint. calculate. In the constraint stage number calculation step, a pass transistor stage number constraint corresponding to the delay time constraint is calculated from a delay time constraint between input / output signals of a given circuit and a predetermined delay time such as an average delay time of the pass transistor circuit.

In the optimal input signal order determining step, the first
Satisfies the constraint on the number of pass transistors between input and output signals, secondly, continuity of inputs in the same group, and thirdly, information on the distance for each input group (for example, in all groups, output In accordance with the rule of deciding the shortest distance to), an optimal input signal order for Shannon expansion is determined. In the binary decision diagram generation step, a binary decision diagram corresponding to the logic circuit is generated by applying Shannon expansion to the logic circuit in the order of the input signals. In the two-input selector circuit replacement step, a technology-independent pass transistor logic circuit is generated by replacing each node of the binary decision graph with a two-input selector circuit using pass transistors.

As a result, the number of stages of the pass transistors between the input signal and the output signal to which the delay time constraint is given is limited, and the speed of the generated circuit is increased so as to satisfy the given delay time constraint. .

According to the third aspect of the present invention, in a method of designing a pass transistor logic circuit based on a given logic specification of a circuit, the following characteristic processing is performed in each unique step.

In the appearance frequency calculation step, the appearance frequency of the input pair entering the same gate of the logic circuit is calculated by a predetermined procedure. In the input grouping step, inputs are grouped in a predetermined procedure based on the calculated appearance frequency. In the distance calculation step, the distance from the input terminal to the output terminal is calculated by a predetermined procedure for each input signal of the generated logic circuit. In the distance calculation step for each group, the distance from the group to the output is calculated for each input group based on the calculation result of the distance calculation step. In an optimum order determination step for each group, an optimum order for Shannon expansion is determined for each input group. In an optimal input signal order determining step within a group, an optimal input signal order for Shannon expansion is determined within the same input group.

In the first binary decision diagram generation step,
A first binary decision graph corresponding to the logic circuit is generated by applying the Shannon expansion process to the logic circuit in the order of the input signals determined in the group-by-group distance calculation step and the intra-group optimum input signal order determination step. I do. Second
In the binary decision diagram generation step, a second binary decision graph is generated by applying Shannon expansion processing to the logic circuit in a new input signal order in which the input group order is changed in a predetermined procedure.

In the comparing step, the superiority of the first binary decision diagram and the superiority of the second binary decision diagram are compared. Excellent 2 minutes decision graph In the decision step, 2 which was determined to be excellent as a result of comparison
The minute decision graph is newly defined as a first binary decision graph. In the iterative type best binary decision diagram determination step, the second binary decision diagram generation step and the excellent binary decision diagram determination step are repeated in a predetermined procedure (the number of repetitions at this time, For example, a predetermined number of times determined based on experience, an approximate circuit, the size of a group, and the like, and an improvement rate of a comparison result are considered.) The best binary decision graph is determined.

In the two-input selector circuit replacement step, technology-independent pass transistor logic circuits are generated by replacing each node of the finally obtained binary decision diagram with a two-input selector circuit using pass transistors.

As a result, Shannon expansion is performed in an optimized input order, and the number of nodes in the obtained binary decision diagram is reduced, and the circuit scale is reduced.

Further, since the generated input / output distance of the pass transistor circuit reflects the input / output distance of the original logic circuit, the speed is increased.

According to the fourth aspect of the present invention, in the step of determining an optimum order for each group in place of the distance calculation step of the second aspect of the present invention, the input signals are grouped in units of:
An optimal order for Shannon expansion is determined based on a predetermined signal transition probability in each group.

Then, in the intra-group optimum input signal order determining step, within the same input group for which the optimum order has been determined, the optimum input signal order for Shannon expansion within the group is determined based on the signal transition probability. decide.

Thereafter, the same processing as in the second aspect of the invention is performed.

According to the fifth aspect of the present invention, the second aspect is provided.
In the optimal input signal order determining step reflecting the signal transition probability in place of the optimal input signal order determining step of the described invention,
The first is to satisfy the constraint on the number of pass transistors between input and output signals (therefore, it is determined whether or not the constraint on the number of stages is satisfied for each new order). The second is to make the inputs in the same group continuous. Second, considering the signal transition probability of each input signal thirdly, the optimal input signal order for Shannon expansion is determined for each input group and for each input signal in the same group.

According to the sixth aspect of the present invention, the third aspect is provided.
In the invention described above, a delay constraint is provided or related from a predetermined delay time constraint between input and output signals of each signal of a given circuit and a predetermined delay time at each stage of the pass transistor circuit. For each input signal,
Each of them has a constraint stage number calculating step of calculating a pass transistor stage number constraint corresponding to the delay time constraint.

The step of determining the optimum order for each group includes the first step in which the calculated restriction on the number of pass transistors between input and output signals and the second step in which information relating to the distance between input and output are considered. This is a decision step. Similarly, the step of determining the optimum input signal order includes the first step of limiting the number of pass transistor stages between the calculated input and output signals.
The step of determining the optimal input signal order reflecting the number of stages reflecting the information on the distance between the input and the output second.

In the invention according to claim 7, claim 4
The described invention further has or relates to a delay constraint from a predetermined delay time constraint between input and output signals for each signal of a given circuit and a predetermined delay time at each stage of the pass transistor circuit. Each input signal has a constraint stage number calculation step of calculating a pass transistor stage number constraint corresponding to the delay time constraint for each input signal.

Further, the step of determining the optimum order for each group reflects the stage number signal transition probability in which the constraint on the number of pass transistor stages between the calculated input and output signals is considered first and the predetermined signal transition probability of each input signal is considered second. This is an optimal order determination step for each group. Similarly, the step of determining the optimal input signal order includes first setting the constraint on the number of pass transistors between the calculated input and output signals and setting the predetermined signal transition probability of each input signal to the second.
This is a step of determining the optimal input signal order reflecting the number of signal transition probabilities in stages.

In the invention described in claim 8, the second binary decision diagram generation step in the invention described in claim 3, 4, 6, or 7 is a continuous procedure as a predetermined procedure. This is a continuous input group replacement type second binary decision diagram generation step of replacing the order of input groups.

According to the ninth aspect of the present invention, in the sixth aspect,
Alternatively, the second binary decision graph generation step of the invention according to claim 7 is a step-number constraint reflecting type second step of changing the order of input signals so as to satisfy the constraint on the number of pass transistors between input and output signals as a predetermined procedure. This is a binary decision diagram generation step.

According to a tenth aspect of the present invention, in each of the above-described inventions, a logic circuit including a normal logic gate is generated from the logic specification. In the subsequent logic circuit generation step, a redundant part of the logic is deleted by a predetermined procedure. Specifically, if there are several types of logic, the shortest logic is adopted. In addition, a logic which is best determined by experience according to a signal to be processed is employed.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on embodiments with reference to the drawings.

(First Embodiment) The present embodiment relates to grouping input signals based on appearance frequency to reduce power consumption.

FIG. 1 shows a processing flow (procedure) in the pass transistor logic circuit designing method of the present embodiment. Hereinafter, the contents will be described based on this figure and also with reference to other figures.

(Step 1) Logic specifications are determined. Here, the logical specification is a description of a logical specification of a circuit to be designed in a format such as a hardware description language or a logical expression. Note that the logical specification itself may be determined by a device in which this circuit is used, its function, or the like, or may be uniquely determined as a general-purpose circuit.

First, the present embodiment is a combination circuit.
And it is possible to directly process by the design method of the present invention using BDD. However, the sequential circuit can also be divided into a combinational circuit and a flip-flop (circuit).
Therefore, the design method of the present invention can be applied to the combinational circuit portion.

FIG. 2 shows a hardware description language veril.
An example of a function description using ogHDL is shown. This is a and b
Describes the operation of a 4-bit adder that outputs the result of adding two 4-bit input values to y. Although the logic is simple in order to easily understand the contents of the present invention, a much more complicated circuit is actually targeted.

FIG. 3 is an example of a logical expression representing the most significant bit y3 of the output y of the 4-bit adder. Here, “&” indicates a logical product, and “|” indicates a logical sum (a vertical line is shown for convenience of input, but actually a two-divided vertical line as shown in the figure).
Is an operator representing exclusive OR. The logical expression is an example of the logical specification, similarly to the above-described function description.

(Step 2) A logic circuit composed of ordinary gates is generated based on logical specifications such as a functional description and a logical expression in a hardware description language (HDL). In this step, there are a method of manually performing a logic design and a method of using a logic synthesis tool, and any method may be used. In the present embodiment, the latter is adopted.

FIG. 4 is an example of a logic circuit generated by the processing of step 2 from the logic equation shown in FIG. In the figure, 301 and 303 are AND circuits, and 302
And 305 are EXOR circuits, and 306, 307 and 30
8 is a NAND circuit. Since a and b are each 4 bits, there are four signal lines. As shown in this figure, the above-described addition circuit is represented here by a network of logic gates such as AND and OR.

In each embodiment of the present invention, this one-output logic circuit will be described as an example (and a simple one) for easy understanding of the contents of the invention. Even a multi- (2) output logic circuit in which b is divided by a to output a quotient and a remainder is basically handled in the same manner. That is, four signal lines a and b and an AND circuit or N
Of course, it can be expressed by a connection such as an AND circuit.

(Step 3) Each gate of the logic circuit generated in step 2 is examined, and if there is a pair directly input to the same gate by the input signal of the logic circuit, the number of appearances is counted. The appearance frequency of the input pair calculated as described above for the logic circuit shown in FIG. 4 is shown in FIG.
Shown in

For example, since the input signals a0 and b0 are both input to the gate 302, the appearance frequency is 1. Since both the input signals a1 and b1 are input to the gate 301 and the gate 303, the appearance frequency is 2.

(Step 4) Inputs are grouped based on the result of Step 3. In this embodiment, the appearance frequency is 1
The above input pairs are grouped as the same group. At this time, one input always belongs to one input group. FIG. 6 shows the result of grouping in this manner.

However, such a method can be used for a small-scale circuit, but when dealing with a large-scale circuit, it is necessary to use a more complicated algorithm than the method used here for grouping. . In such a case, the information on the appearance frequency becomes effective.

To briefly explain the basics (point of focus) of the algorithm creation, in the case of simple addition of two numerical values, the input pair of the least significant bit always has an appearance frequency of 1, and the input digit in the middle digit A pair has one or more appearance frequencies determined by the digit. Also, in the multiplication, the pair of least significant bits of both numerical values has an appearance frequency of 1, and
An input pair of the numerical value of one least significant bit and the bit value of another certain digit has one or more appearance frequencies determined from that digit. In the case of division, the quotient digit is determined from the number of divisions and the number of divisions, and the frequency of appearance of the value of each digit of the division number is greater than the value of each digit of the division number. Therefore, it is created according to the digit of the signal (numerical value) to be processed or the content of the processing. It should be noted that, based on the knowledge and experience of the designer with respect to the properties of each circuit, inputs having high local computing properties may be manually grouped together (man-machine system). (Therefore, the design result in the middle stage is displayed on the CRT, and the designer may perform necessary processing or input by operating the keyboard or the like.) (Step 5) Input of each input of the logic circuit generated in Step 2 Evaluate the signal transition probability. Usually, logic circuits are often designed in a synchronous manner that operates in synchronization with a clock. In this case, the values of all the signals in the circuit are determined in synchronization with the clock, the values change from the previous cycle in one clock cycle, and retain the values of the previous cycle in another clock cycle. The signal transition probability is defined by dividing the number of clock cycles whose value changes by the total number of clock cycles.

The power consumption of each signal in the logic circuit is given by the following equation (1). Since this equation is related to the following equation 2, it can be seen that the power consumption of each signal is proportional to the signal transition probability. By the way, since the power consumption of the entire circuit is the sum of the power consumption caused by the change of each signal in the circuit, it is important to reduce the signal transition probability of each signal of the circuit in order to reduce the power consumption of the circuit. . (Of course, there can be a leak current, etc., but in the context of the present invention, it can be practically ignored.) P = (１ ／) · C · Vdd ² · SWR (Formula 1) where C is the load of the signal Vdd represents the power supply voltage of the circuit, and SWR represents the number of transitions of the signal per unit time. SWR = STR / Tcycle (Formula 2) Here, STR means a signal transition probability, and Tcycle means a clock cycle time. When the logic circuit is an entire circuit to be designed, its input is an external input of the entire circuit, and its signal transition probability is determined by the specification of a signal input to the circuit. Now, a normal circuit is complicated, and therefore, it is often designed hierarchically and logically designed for each sub-circuit. Specifically, in the video signal of one screen, the signal transition probability is high in the central part of the screen, and the peripheral part is rarely actually seen by a person, and is rare. Therefore, in the case where some processing is performed for each small screen obtained by cutting one screen in several directions in the vertical and horizontal directions, the transition establishment of the circuit for processing the small screen in the center becomes high. In addition, a multi-digit operation is often performed by dividing a digit into several. In these cases, the signal transition probability at the input of the sub-circuit is roughly determined by the specification of the signal given to the external input of the entire circuit and the logic of the peripheral sub-circuit connected to the sub-circuit.

By the way, there are several methods for evaluating the signal transition probability. In the present embodiment, the evaluation is made by logic simulation.

FIG. 7 shows an example of a test vector given to an input signal in a logic simulation.

In this figure, each row has one vector, and a signal applied to an input in a certain clock cycle is described. Each number in the vector represents the value of the corresponding input signal at the position. The first row describes the vector of the first clock cycle, the next row describes the vector of the second clock cycle, and so on.

When the input value of each clock cycle is determined,
Then, by performing a logical operation, each internal signal value of the circuit in each clock cycle is determined. By comparing the signal value of each clock cycle with the value of the previous cycle, it is determined whether or not the signal has changed, so that the signal transition probability can be calculated. Since the internal signal includes the input signal of the sub-circuit, the signal transition probability of the input of the sub-circuit can be obtained.

In order to accurately evaluate the signal transition probability by the method based on the logic simulation, it is necessary to prepare an appropriate test vector that accurately reflects a situation actually used.

To give a concrete example, when a simple sum of two numerical values is obtained, it is almost impossible that both numerical values are close to the limit of the computing power of the computer as a practical problem. For example, in a daily calculator, the user uses only addition of five or six digits at most, and the display and calculation ability of higher digits are mostly idle.

Regarding the video signal, no matter what compression method or transmission method is used, the actual red, green, blue (R,
G, B) are unlikely to be all full brightness.
That is, the digital value does not become full.

In the case of an acoustic signal, what is normally transmitted and received, and the main processing target of the circuit is a frequency used by a person in daily conversation.

Further, especially in the case of a digital video signal, the value of each pixel of one screen and the next screen after 1/30 second are the same in many cases, and the upper, lower, left and right sides of one screen are adjacent to each other. The same applies to the pixel values. Specifically, when the announcer's face appears in a television news program, only the area around the mouth moves on the screen.

As a practical matter, not many new devices and logic circuits appear. To be clear,
In an actual design, basically, most of the improvements of the previous ones and similar ones, the addition of a few components, and the like, or even the other case, the experience and data can be used.

For this reason, in the case of a device in which the PLL circuit of the present invention is actually used, the logic simulation is performed in consideration of the characteristics of the device, for example, an arithmetic circuit or an arithmetic unit. It is possible to easily collect an appropriate model vector based on the actual situation or experience such as that only the numerical value often changes. Of course, in the case of a circuit whose use is not specified, sampling is performed based on experience with a general-purpose circuit.

(Step 6) The input signal groups are ordered based on the signal transition probability of each input evaluated in Step 5. Here, the average value of the signal transition probabilities is calculated for each input signal group, and the order is performed in descending order of the value. FIG. 8 shows the result of such ordering.

(Step 7) Within each input signal group, ordering is performed in descending order of signal transition probability. FIG. 9 shows the result of first performing large ordering in units of input signal groups and then performing detailed ordering within the input signal groups. In this figure, the lower the digit, the higher the probability of signal transition.

(Step 8) The logic circuit generated in step 2 is subjected to Shannon expansion in the order determined in step 7 to generate a binary decision diagram (BDD).

Here, the Shannon expansion of the logical function f using the input variable p is a logical function in which the input p in f is fixed to 1 is f [P = 1], and a logical function in which the input p in f is fixed to 0. Is represented by f [P = 0], the left side is converted to the right side by utilizing the fact that the equation shown in the following Expression 3 holds. The logic on the left side is f = f if p is 1.
[P = 1], and if p is 0, it is understood that the alternative logic is f = f [P = 0].

The logic circuit generated in step 2 corresponds to the logic function of the following equation (4). According to the order, y3
Is Shannon-expanded by a0, and becomes Equations 5 and 6, and is expanded as Equation 7. f = p & f [P = 1] | ＾ p & f [P = 0] (Equation 3) Here, the symbol “&” represents a logical product as described above, “|” represents a logical sum, and “＾” represents a logical inversion. Represents

Y3 = ((a0 & b0 & (a1 | b1) | (a1 & b1)) & b2 | (a0 & b0 & (a1 | b1) | (a1 & b1) | b2) & a2) ＠ a3 ＠ b3 (Formula 4) y3 [a0 = 1] = ((B0 & (a1 | b1) | (a1 & b1)) & b2 | (b0 & (a1 | b1) | (a1 & b1) | b2) & a2) ＠ a3 ＠ b3 (Equation 5) y3 [a0 = 0] = ((a1 & b1 & b2) ) | ((A1 & b1) | b2) & a 2) ＠ a3 ＠ b3 (Equation 6) y3 = a0 & y3 [a0 = 1] | ＾ a0 & y3 [a0 = 0] (Equation 7) Further, when Shannon expansion is performed with b0, It becomes 8.

On the other hand, since y3 [a0 = 0] does not include b0, there is no need for Shannon expansion. Therefore, it is developed as Expression 9. y3 [a0 = 1] [b0 = 1] = ((a1 | b1 | (a1 & b1)) & b2 | (a1 | b1 | (a1 & b1) | b2) & a2) ＠ a3 ＠ b3 y3 [a0 = 1] [b0 = 0] = ((a1 & b1 & b2) | ((a1 & b1) | b2) & a2) ＠ a3 ＠ b3 (Equation 8) y3 = a0 & b0 & y3 [a0 = 1] [b0 = 1] | a0 & ＾ b0 & y3 [a0 = 1] [b0 = 0] | ＾ a0 & y3 [a0 = 0] (Equation 9) Further, a1, b1, a2, b2, a3, b
Execute Shannon expansion for No. 3.

FIG. 10 shows the BDD generated in this manner.
Is shown. A non-terminal node (round node) of the BDD corresponds to one logical function Shannon-expanded by an input variable described in the node. The edge extending upward from each node is an output edge, which transmits the logical function represented by that node to the upper node. On the other hand, edges extending downward from each node include those written as 1 (1 edge) and those written as 0 (0 edge). The former is connected to a node corresponding to a logical function with an input variable fixed to 1 in the Shannon expansion, and the latter is connected to a node corresponding to a logical function with an input variable fixed to 0.

That is, the uppermost node 31 corresponds to the output y3 of the logic circuit. The node 32 corresponds to a logical function in which the input variable a0 is fixed to 1 in the logical function of y3. There are terminal nodes (square nodes) described as 1 and nodes described as 0, which correspond to logical constants 1 and 0, respectively.

More specifically, for example, in the node 35 described as b3 inside the circle, since the 0 edge is connected to the constant 1 and the 1 edge is connected to the constant 0, the corresponding logical function Is found to be the following Expression 10. Similarly, node 36 corresponds to logic function b3. The logical function corresponding to the node 33 is given by the following equation (11).
It is. b3 & 0 | ＾ b3 & 1 = ＾ b3 (Formula 10) a3 & ＾ b3 | ＾ a3 & b3 = a3 ＠ b3 (Formula 11) (Step 9) The BDD generated in Step 8 is converted into a pass transistor logic circuit. BDD as described above
Is a binary logic, while the pass transistor logic is configured based on a two-input selector. By applying the conversion shown in FIG. 11 to each node of the BDD, the corresponding pass transistor circuit Can be obtained. In this drawing, the lower part of each of the left and right transistors is an input, and the upper part is an output. A horizontal line above a0 indicates the inversion of the input signal a0.

FIG. 12 shows a pass transistor logic circuit converted from the BDD of FIG. As shown in FIG. 12, the input such as a0 or b0 having a higher signal transition probability has a smaller number of pass transistor stages up to the output y3. It can be seen that the power consumption has been reduced.

In practice, it is often difficult to connect a large number of pass transistors in series as shown in FIG. 12, and it is necessary to insert a buffer for restoring potential and amplifying current at an appropriate place. However, it is not a technology independent logic design step according to the present invention, but rather a subsequent technology dependent logic design step. Therefore, the description thereof is omitted.

For this reason, the final number of pass transistor stages between input and output and the number of transitions of internal signals per unit time in the final pass transistor logic circuit cannot be estimated at this stage. Distance is preserved in the final circuit.

(Second Embodiment) In the present embodiment, a delay time constraint is taken into consideration.

FIG. 13 is a diagram showing a flow of processing in the second embodiment of the present invention.

The logic specification 1 of this embodiment, a step 2 for generating a logic circuit using normal gates, a step 3 for calculating the appearance frequency of an input pair entering the same gate of the logic circuit, and a step for grouping input signals 4 is the first
Since it is the same as that of the embodiment, the description will not be repeated.

(Step 13) In designing a logic circuit, usually, not only a given logic specification is satisfied, but also a delay time constraint to be satisfied by the circuit is often given. In the combinational circuit design of the present embodiment, this delay time constraint is given by the maximum delay value from input to output as shown in FIG.

Here, it is described that the delay from the input a0 to the output y3 must be 2.0 ns or less, and the delay from the input b0 to the output y3 must be 1.5 ns or less. However, no delay constraint is imposed on inputs other than a0 and b0.

As an example in which the delay time differs depending on the input signal as described above, for example, one input signal b0 is a signal which has been subjected to some processing with respect to the original signal. There is a case where a delay of 0.5 ns has already occurred at the stage of input to the input.

The delay time itself depends on the type of signal to be processed, such as video and audio, and there are various types of delay restrictions. For example, in the actual design, a specific input signal is often given a delay constraint, for example, because a specific input signal lags behind another input signal. However, since these details are not the gist of the present invention, further description is omitted.

(Step 14) Based on the given delay time constraint, the number of pass transistor stages between input and output is calculated. For this purpose, it is necessary to previously determine the average delay time per pass transistor stage by some method. Usually, these values fluctuate depending on the characteristics of the circuit to be designed. Therefore, it is important to obtain a highly reliable value by collecting statistics on as many circuits as possible. However, instead of simply taking statistics, the average delay time per stage is analyzed from various parameters such as the type of transistor used, the use of the circuit, and the scale determined by the signal to be processed, and a highly reliable value is obtained. Of course, in the case of an improved product, it is estimated from the results of the old type. Also, the design apparatus may be equipped with a dictionary of these parameters and delay time, or may input these parameters at the time of design to calculate the approximate delay time. However, since these matters are not difficult for a person skilled in the art in the field of pass transistor logic, a detailed description thereof will be omitted.

In this embodiment, for simplicity of calculation, it is assumed that the delay value is an average of 0.4 ns per pass transistor stage. In this case, there is a restriction that a0 to y3 is within 5 stages of the pasta transistor and b0 to y3 is within 3 stages of the pasta transistor.

(Step 11) The distance from each input to the output of the logic circuit (FIG. 4) generated in step 2 is calculated. Here, the distance is defined by the number of gate stages of the shortest path (the path with the smallest number of gate stages) among all the paths from each input to the output. However, an inverter (logical inversion) is not included in the number of gate stages in order to eliminate fluctuations in distance estimation by a logical expression as much as possible. For the same reason, a composite gate such as EXOR (exclusive OR) is not divided into one stage, but is divided into basic gates and counted as two stages.

FIG. 15 shows the result calculated in this step.

In FIG. 4, for example, the shortest path from the input a0 to the output y3 is the gate 302, the gate 306,
Since the path passes through the gate 307, the gate 308, and the gate 305, the distance can be calculated as 6 by counting the last EXOR gate 305 as two stages. Therefore, in FIG. 15, the distance of the input a0 is 6.

Various other methods may be used to define the distance in this step, such as using an average value of the number of gate stages of all paths. Of course, these methods may be adopted depending on the case. It is.

(Step 12) The distance to the output is calculated for each input group (FIG. 6) determined in step 4. Here, the distance from the input group to the output is defined by the average value of the distances (calculated in step 11) to the output of all the input signals belonging to each input group. FIG. 16 shows the calculation results. In addition to the method of defining the distance in this step, in addition to the method described here, for example, the minimum value of the distance to the output of all the input signals belonging to the input group is used, and conversely, the maximum value is used. Various methods are conceivable depending on the target signal, the use of the circuit, and the like, and it goes without saying that these may be adopted depending on the case. Specifically, in the screen processing of a video signal, the quality of the processing result of a very small number of pixels does not cause any discomfort to the viewer, but the numerical calculation does not. For this reason, the former uses an average value, and the latter uses a maximum value.

(Step 15) The input variables are ordered in consideration of the pass transistor stage number constraint of each input obtained as a result of Step 14 and information such as the distance from each input group to the output calculated in Step 12.

In this embodiment, the highest priority is given to the restriction on the number of stages of the pass transistors of each input. The pass transistor logic circuit design method of the present invention has a feature that the structure of the BDD generated as the intermediate data is reflected in the structure of the final circuit, and thus is generated in the order of the input variables in the Shannon expansion. It is possible to adjust the number of stages between the input and output of the circuit.

Therefore, the input a0 is within the fifth, and the input b
It is necessary to observe the constraint that 0 is within the third. Since no delay constraint is given to inputs other than a0 and b0,
For them, the number of stages is not considered.

First, from the distance between the input and output of each input group shown in FIG.
2. An approximate order is determined, such as G1. Next, the stage number constraint is considered. The inputs a0 and b0 both belong to the input group G1, and the more restrictive of both is b0
Is within the third. The input / output distance is the same between input signals belonging to each input group.

FIG. 17 shows the input variable order determined from the above information.

(Step 8) As in step 8 in the first embodiment, the logic circuit of FIG. 4 is Shannon-expanded according to the order determined in step 15 to generate a BDD. FIG. 18 shows the generated BDD.

(Step 9) Similar to step 9 in the first embodiment, the BDD generated in step 16
Into a pass transistor logic circuit. FIG. 19 shows the generated pass transistor logic circuit 18.

From this figure, it can be seen that the number of pass transistor stages from the input a0 to the output y3 is four, and the number of pass transistor stages from the input b0 to the output y3 is three.

The actual circuit delay cannot be accurately evaluated until after the layout design is completed through the technology-independent logic design step and the technology-dependent logic design step of the present invention. However, this requires that an appropriate design margin (for example, 7%) be incorporated in the step 14 of calculating the number of pass transistor logic stages from a given delay time constraint based on estimation, experience, and the like from the old type. Thus, it is possible to satisfy the given delay time constraint.

On the other hand, in the case of FIG. 20 where the input variable order of Shannon expansion is determined without considering the delay constraint, the generated BDD is as shown in FIG. 21, and the pass transistor circuit converted therefrom is shown in FIG. become that way.
In this circuit, although the number of nodes is reduced, the number of pass transistor stages from the inputs a0 and b0 to the output y3 is seven, and the average delay time per stage is 0.
Considering that the delay time is 4 ns, the delay constraint is not satisfied, and although it depends on the type of signal to be originally processed, there is a high possibility that the circuit cannot be actually used. (Third Embodiment) In the present embodiment, the order is changed between input groups.

FIG. 23 is a processing flow chart showing a processing flow in the third embodiment of the present invention.

Logic specification 1 of this embodiment, step 2 for generating a logic circuit using normal gates, step 3 for calculating the appearance frequency of input pairs entering the same gate of the logic circuit,
Step 4 for grouping the input signals is the same as that in the first embodiment, and thus the description is omitted here.

Step 11 for calculating the distance from each input to the output of the logic circuit and step 12 for calculating the distance from each input group to the output are the same as those in the second embodiment. Therefore, the description is omitted here.

(Step 21) From the distance between the input and output of each input group shown in FIG.
The general order is determined as 3, G2, G1.

(Step 22) From the input-output distance for each input signal shown in FIG. 15, each input signal is ordered so that the distance becomes smaller in each input group. In the circuit example here, the distance between input and output is the same between input signals belonging to each input group.

The order of the input variables determined by the method described above is as shown in FIG.

The basis for such ordering is as follows.
On the point.

First, input signals belonging to the same input group are frequently input to the same gate, so that there are many calculations related to inputs in the same group and matters related to the calculation. That is, it is considered that the so-called local computing property is high. It has been empirically known that the size of the generated BDD can be reduced by continuously performing Shannon expansion of inputs having high local computational properties. Also,
The reason for this intuition is that the same digit is used for summation, the same color is used for video signal processing, the same frequency is used for audio signals, and similar digits are used even if they are not the same. That is, the continuous processing at that digit or a nearby digit can be performed quickly as a whole. For this reason, in the case of an operation between tens of digits, in the lower layer, the operation is performed by dividing the number in units of ten digits,
Further, the output of each unit is adjusted in the upper layer to obtain a final value.

Second, as a matter of course, it is considered that an input signal having a smaller distance between input and output in the original logic circuit has a stronger ability to control the output. Specifically, in addition or digital video signal processing, the signal of the highest digit of a digital value such as a numerical value or color is more likely to affect an output signal. It is also empirically known that by performing Shannon expansion first on an input signal having a strong output control power, the size of the generated BDD can be reduced in principle, depending on the signal to be processed and the content of the processing. ing.

Next, as described above, in the method of performing Shannon expansion by ordering input signals using the structure of the original logic circuit, the redundancy of the logic circuit is increased in order to increase the accuracy in extracting the logic structure. It is effective to perform an optimizing process for removing. That is, for example, there are a plurality of methods for calculating the average value of three numerical values a, b, and c, such as first obtaining the sum of each numerical value, and then dividing the sum by 3, or first dividing each numerical value by 3, and then adding them. In many cases, various forms may be used to implement a certain logic. However, in the design of a pass transistor logic circuit, if there are a plurality of forms for the same logic, it is good to select the simplest one in principle. Which form is the simplest and consequently best? It is better to reduce the number of multiplications and divisions even if the number of additions and subtractions is slightly increased. The best criterion is appropriately selected according to the contents and the like. Also, of course, empirical rules are referred to.

(Step 23) In accordance with the input signal order determined in step 22, the logic circuit is Shannon-expanded and first converted to a temporary BDD. Since this step is basically the same as the processing of step 8 in the first embodiment, the description is omitted here. The generated BDD is the same as that shown in FIG.

(Step 25) The total number of temporary or first BDD nodes generated as a result of step 23 is calculated. For example, in the BDD shown in FIG. 12, the total number of nodes is 19. (Constant nodes are not included.) In this embodiment, the total number of nodes is simply used to evaluate BDD, but this is merely an example, and various other evaluation indices are used. be able to.

For example, each node of the BDD corresponds to a certain input signal. However, depending on devices such as televisions and radios, importance of input signals such as video, audio, VBI, processing speed and the like are different. For example, after weighting each input signal, Σ (weight) × (number of nodes) can be used as an evaluation index for all input variables.

The weight here can reflect the transition probability of the signal and the distance between input and output.

Further, it is also possible to use (coefficient 1) × (index 1) + (coefficient 2) × (index 2) obtained by combining a plurality of indices.

(Step 24) With respect to the input signal order calculated in step 22, a new input signal order is created by changing the order for each input group.

(Step 23) Returning to step 23 several times depending on the case again, Shannon-expanding the logic circuit again in this new input signal order to generate a new, ie, second, BDD.

(Step 25) The new BDD is evaluated to compare its superiority with the previous BDD. As a result, if it is better than the previous one, the new BDD is left; otherwise, the old BDD is left.

In some cases, this routine is repeated for the permutations of all the input groups, and the generated BD
The best one among D is selected as the final result.

(Step 9) BD finally selected
Although D is converted into a pass transistor logic circuit, it is basically the same as step 9 in the first embodiment, and thus the description is omitted.

In the present embodiment, the input signal order is changed for each input group, but the input signal order within the input group is not changed (of course, it may be changed). Therefore, although the pass transistor circuit generated according to the present invention may not be strictly mathematically and logically optimal, input signals included in the same input group have high local computability. Taking this into account, a solution that is optimal or close to this can be obtained in many cases.

On the other hand, the strict optimization method that tries all permutations of the input signal order takes too much time for processing, and therefore cannot handle a circuit exceeding about 17 inputs as described above. On the other hand, using the method of the present invention makes it possible to handle even a much larger circuit than the strict optimization method.

However, in the method of trying the permutation of all the input groups as shown in the present embodiment, there is still a limit to the circuit scale that can be handled. Thus, for larger circuits, for example, in step 25, a predetermined number of times that the BDD corresponding to the new input signal sequence was not improved compared to the best results obtained previously was followed. In such a case, it is necessary to take measures such as terminating the search for the optimal solution.

In addition, as a new input signal order adopted in the repetitive calculation, only a group or an input signal having a certain reference value close to the reference value may be replaced. That is, favorable results are less likely to be obtained in an undesired order of certain reference values.

It is needless to say that such a method is also included in the present invention.

The present invention has been described with reference to some embodiments,
In addition, although a small circuit has been described as an example in order to make it easy to understand the contents of the invention, it goes without saying that the present invention is not limited to these circuit scales, technical contents such as processing, and the like. That is, for example, the following is performed.

1) One step of the present invention is combined to perform processing in parallel, or several small steps are performed so that a person can appropriately perform necessary processing.

2) The logic circuit is not only a multi-input and multi-output logic, but is conceptually a logic circuit with a small number of inputs and a multi-output as in a search.

3) The invention of each claim is integrated.

4) General-purpose CPUs and personal computers have developed,
Nowadays, discs and the like are standardized, and are in the form of a disc or the like in which the program of the present invention is stored.

5) Other elements such as the circuit area are also taken into consideration.

[0146]

As can be seen from the above description, according to the present invention, when a pass transistor circuit is generated from given logical specifications, a pass transistor circuit having the following features can be synthesized. It becomes possible. (1) An input having a higher signal transition probability has a smaller number of pass transistor stages with respect to an output, so that a signal having a higher transition probability does not propagate for a longer time, and the sum of transition probabilities is smaller as a whole circuit, resulting in lower power consumption. (2) The number of pass transistor stages between inputs and outputs to which a delay time constraint is applied is limited based on the delay constraint value. More specifically, the operation of the circuit is performed by giving a delay constraint between the input and output that become a critical path. Is fast. (3) Even a logic circuit having a large number of inputs, which has been difficult to optimize with the conventional design method, has a small scale.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing procedure of a pass transistor logic circuit designing method according to a first embodiment of the present invention.

FIG. 2 is a functional description for explaining the embodiment,
It is a figure showing y = a + b.

FIG. 3 is a diagram showing a logical expression of the function description.

FIG. 4 is a diagram of a logic circuit generated from the logic expression of the embodiment.

FIG. 5 is a diagram illustrating appearance frequencies of input signal pairs entering the same gate in the logic circuit in the above embodiment.

FIG. 6 is a diagram showing a result of grouping input signals in the embodiment.

FIG. 7 is a diagram showing an example of a test vector required for evaluating a signal transition probability in the above embodiment.

FIG. 8 is a diagram showing an average signal transition probability and a Shannon expansion order of each input group in the embodiment.

FIG. 9 is a diagram showing a result of ordering inputs based on signal transition probabilities in the embodiment.

FIG. 10 is a diagram of a BDD generated from a logic circuit in the embodiment.

FIG. 11 is a diagram showing conversion from (elements of) a BDD to (elements of) a pass transistor logic circuit in the above embodiment.

FIG. 12 is a diagram showing a pass transistor logic circuit converted from BDD in the embodiment.

FIG. 13 is a diagram showing a processing procedure of a pass transistor logic circuit designing method according to the second embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a delay constraint in the embodiment.

FIG. 15 is a diagram illustrating a distance to an output of each input signal of the logical value circuit in the embodiment.

FIG. 16 is a diagram showing a distance to an output of each input group in the embodiment.

FIG. 17 is a diagram illustrating a result obtained by ordering inputs in consideration of a restriction on the number of stages of pass transistors in the embodiment.

FIG. 18 is a diagram illustrating a BDD generated from a logic circuit in the above embodiment.

FIG. 19 is a diagram showing a pass transistor logic circuit converted from BDD in the above embodiment.

FIG. 20 is a diagram showing a result of ordering inputs without considering delay constraints between input and output in the embodiment.

FIG. 21 is a diagram illustrating a BDD generated from a logic circuit in an input order determined without considering a delay constraint between input and output in the embodiment.

FIG. 22 is a diagram showing a pass transistor logic circuit converted from a BDD generated from a logic circuit in an input order determined without considering a delay constraint between input and output in the above embodiment.

FIG. 23 is a diagram showing a processing procedure of a pass transistor logic circuit designing method according to the third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic specification 2 Logic circuit generation step 3 Input pair appearance frequency calculation step 4 Input signal grouping step 5 Input signal transition probability evaluation step 6 Input group ordering step 7 Input signal ordering step 8 BDD generation step 9 Pass transistor logic circuit conversion step Reference Signs List 10 pass transistor logic circuit 11 input / output distance calculation step 12 each group input / output distance calculation step 13 delay time determination step 14 stage number constraint calculation step 15 input ordering step 21 distance corresponding input group ordering step 22 distance corresponding group input signal Ordering step 23 Shannon expansion temporary BDD generation step 24 Input group order conversion step 25 Shannon expansion BDD evaluation and comparison step

Claims (10)

[Claims] 1. Based on a logical specification of a given circuit,
A method for designing a pass transistor logic circuit, comprising: a logic circuit generation step of generating a logic circuit composed of normal logic gates from the logic specification; and a pair of input signals entering the same gate of the generated logic circuit. A pair appearance frequency calculating step of calculating the appearance frequency of each pair in a predetermined procedure; a grouping step of grouping input signals in a predetermined procedure based on the calculation result of the appearance frequency of each pair; In each signal, an optimal order determination step for each group that determines an optimal order for Shannon expansion based on a predetermined signal transition probability in each group; and a signal transition in the same input group in which the optimal order is determined. An intra-group optimal input signal order determination scheme for determining an optimal input signal order for Shannon expansion within the group based on the probability. And applying the Shannon expansion to the generated logic circuit in the order of the input signals determined in the group-based optimum order determination step and the intra-group optimum input signal order determination step to correspond to the logic circuit. A binary decision diagram generating step for generating a binary decision diagram; and a two-input generating technology-independent pass transistor logic circuit by replacing each node of the generated binary decision diagram with a two-input selector circuit using pass transistors. And a selector circuit replacement step. 2. Based on the logic specification of a given circuit,
A method for designing a pass transistor logic circuit, comprising: a logic circuit generation step of generating a logic circuit composed of normal logic gates from the logic specification; and a pair of input signals entering the same gate of the generated logic circuit. A pair appearance frequency calculating step of calculating the appearance frequency of each pair in a predetermined procedure; a grouping step of grouping input signals in a predetermined procedure based on the calculation result of the appearance frequency of each pair; For each input signal having at least a delay constraint or related thereto, a distance calculation step of calculating a distance from an input terminal to an output terminal in a predetermined procedure, based on the distance calculation result, For each input group having a delay constraint or each input signal related thereto, a distance calculation for each group for calculating a distance from now to an output. From the step and the predetermined delay time constraint between input and output signals for each signal of the given circuit and the predetermined delay time at each stage of the pass transistor circuit, each input signal having or related to the delay constraint For each of them, a constraint stage number calculating step of calculating a pass transistor stage number constraint corresponding to the delay time constraint; first, the pass transistor stage number constraint between the calculated input / output signals is set, and inputs in the same group are input. The second is to make it continuous, and the third is to consider the information on the distance calculated for each input group, and the optimal input signal order for Shannon expansion is set for each input group and within the same group. An optimal input signal order determining step for each input signal; and, for the generated logic circuit, Shannon Applying a development to generate a binary decision graph corresponding to the logic circuit; and replacing each node of the generated binary decision graph with a two-input selector circuit using pass transistors. A two-input selector circuit replacement step of generating a technology-independent pass transistor logic circuit. 3. Based on the logic specification of a given circuit,
A method for designing a pass transistor logic circuit, comprising: a logic circuit generating step of generating a logic circuit composed of normal logic gates from the logic specification; and an appearance of an input pair entering the same gate of the generated logic circuit. An appearance frequency calculation step for each pair for calculating a frequency in a predetermined procedure; an input signal grouping step for grouping input signals in a predetermined procedure based on the calculation result of the appearance frequency for each pair; For each input signal of the circuit, a distance calculating step of calculating a distance from an input terminal to an output terminal in a predetermined procedure; and for each input group, for each group, calculating a distance from now on to an output based on the distance calculation result. A distance calculation step, and a predetermined procedure based on the calculated distance for each group in the grouped input signal units. A group-based optimal order determining step of determining an optimal order for Shannon expansion in the same input group in which the optimum order is determined, and performing Shannon expansion in a predetermined procedure based on the calculated distance. Determining the optimal input signal sequence for the group, and determining the optimal input signal sequence in the group for the generated logic circuit in the group-specific optimal sequence determination step and the intra-group optimal input signal sequence determination step. Generating a first binary decision graph corresponding to the logic circuit by applying Shannon expansion in the order of the input signals, and generating a new binary decision diagram corresponding to the logic circuit. A second binary decision diagram generating step of applying a Shannon expansion process to the logic circuit in signal order to generate a second binary decision diagram; A comparing step of comparing the superiority of the first binary decision diagram and the second binary decision diagram; and an excellent 2 which newly determines the superior binary decision diagram as the first binary decision diagram as a result of the comparison. A step of determining a minute decision graph; and a step of repeatedly generating the second step of determining a binary decision chart and the step of determining an excellent step of determining a binary decision according to a predetermined procedure to determine a step of determining the state of the best binary decision. A decision graph decision step, and a technology-independent pass transistor logic circuit is generated by replacing each node of the best binary decision graph determined by the best binary decision diagram with a two-input selector circuit using pass transistors. A pass transistor logic circuit designing method, comprising a two-input selector circuit replacement step. 4. Based on a given circuit logic specification,
A method for designing a pass transistor logic circuit, comprising: a logic circuit generating step of generating a logic circuit composed of normal logic gates from the logic specification; and an appearance of an input pair entering the same gate of the generated logic circuit. An appearance frequency calculation step for each pair for calculating a frequency in a predetermined procedure; an input signal grouping step for grouping input signals in a predetermined procedure based on the calculation result of the appearance frequency for each pair; For each input signal, an optimal order determination step for each group that determines an optimal order for Shannon expansion based on a predetermined signal transition probability in each group, and in the same input group where the optimal order is determined, Determine the optimal input signal sequence for the Shannon expansion within the group based on the transition probability And applying the Shannon expansion to the generated logic circuit in the order of the input signals determined in the group-specific optimum order determination step and the intra-group optimum input signal order determination step. A first binary decision diagram generating step of generating a binary decision diagram of No. 1 and a second binary signal applying Shannon expansion processing to the logic circuit in a new input signal order in which the input group order is changed in a predetermined procedure. A second binary decision diagram generation step for generating a binary decision diagram; a comparison step for comparing the superiority of the first binary decision diagram with the second binary decision diagram; An excellent binary decision diagram determining step for newly setting the binary decision diagram as a first binary decision diagram; a second binary decision diagram generating step according to a predetermined procedure; An iterative best binary decision graph determining step of determining the best binary decision graph by repeating the minute decision graph determining step; and each node of the above best binary decision graph is converted to a two-input selector circuit using pass transistors. A two-input selector circuit replacement step of generating a technology-independent pass transistor logic circuit by replacement. 5. The method according to claim 5, wherein the step of determining the order of the optimal input signals is the first step of limiting the number of stages of pass transistors between input and output signals, the second of making the inputs in the same group continuous, and the signal transition of each input signal. A signal transition probability reflecting optimum input signal order determining step of determining an optimum input signal order for Shannon expansion for each input group and for each input signal within the same group by considering the probability thirdly is provided. 3. The method for designing a pass transistor logic circuit according to claim 2, wherein: 6. A method according to claim 1, further comprising: determining a delay constraint between input and output signals for each signal of a given circuit and a predetermined delay time at each stage of the pass transistor circuit. Each of the input signals further includes a constraint stage number calculation step of calculating a pass transistor stage number constraint corresponding to the delay time constraint for each of the input signals. A step of determining an optimal order for each of the number-of-stages distance reflecting groups in which the constraint on the number of transistor stages is considered first and the information on the distance between the input and output is secondly considered; Determining the optimal input signal order reflecting the number of stages, which first considers the constraint on the number of stages of the pass transistors and secondly considers information on the distance between input and output. Pass-transistor logic circuit design method according to claim 3, wherein there. 7. A method according to claim 1, further comprising a delay constraint between the input and output signals of each signal of the given circuit and a predetermined delay time at each stage of the pass transistor circuit. Each of the input signals further includes a constraint stage number calculation step of calculating a pass transistor stage number constraint corresponding to the delay time constraint for each of the input signals. A stage number signal transition probability reflecting group considering the transistor stage number constraint first and a predetermined signal transition probability of each input signal as a second group, and the optimal input signal order determining step includes: Optimal reflection of the number of stages in which the number of stages of pass transistors between input and output signals is considered first and the predetermined signal transition probability of each input signal is considered second. Pass-transistor logic circuit design method according to claim 4, characterized in that the force signal sequence determining step. 8. The method according to claim 1, wherein the second binary decision diagram generating step is a continuous input group exchange type second binary decision diagram generating step for changing the order of continuous input groups as a predetermined procedure. 8. The pass transistor logic circuit design method according to claim 3, wherein the pass transistor logic circuit is designed. 9. The step of generating a second binary decision diagram includes, as a predetermined procedure, a stage number constraint reflection type second binary stage in which an input signal order is exchanged so as to satisfy a pass transistor stage number constraint between input and output signals. 8. The method for designing a pass transistor logic circuit according to claim 6, wherein the method is a decision graph generation step. 10. The logic circuit generating step according to claim 1, wherein the logic circuit generating step includes a logic optimizing small step of deleting a redundant part of the logic in a predetermined procedure. 10. The pass transistor logic circuit designing method according to claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9.