JP2001102967A - Frequency hopping transmitter and frequency hopping receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency hopping transmitter and a frequency hopping receiver which makes delay detection and synchronous detection possible on a reception side even when a total hopping number is increased. SOLUTION: A modulating circuit 1 modulates data to be transmitted, a hopping pattern generating circuit 2 prepares a plurality of hopping patterns equal to symbol cycles, uses the same hopping pattern among the hopping patterns in the same slot, and switches the hopping patterns by slots, a digital synthesizer 3 switches the frequency according to the output of the hopping pattern generating circuit 2 and a mixer circuit 4 converts the output of the modulating circuit 1 to an RF signal with the output of the digital synthesizer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency hopping transmitter and a frequency hopping receiver for hopping a frequency in a cycle shorter than a symbol cycle.

[0002]

2. Description of the Related Art In recent years, with the development of the information-oriented society, the need for mobile communication capable of communicating anywhere has been increasing. In mobile communication, the reception level fluctuates, but when a reflected wave with a large delay time is added, frequency-selective fading in which the level is attenuated according to the frequency occurs, and the reception sensitivity is greatly degraded. Has become. As a countermeasure against frequency selective fading, a frequency hopping method in which a frequency is switched (hopped) and transmitted is known. In the frequency hopping method, the reception sensitivity can be improved by the frequency diversity effect as long as a frequency that does not drop even when a frequency whose level drops due to frequency selective fading is used.

FIG. 7 is a pattern diagram showing a frequency hopping pattern in a conventional frequency hopping transmitter that hops a frequency in a cycle shorter than a symbol cycle. In this frequency hopping pattern, the number of hops per symbol is 4 hops, and the total number of hops is 4n. As the total number of hops 4n increases, the reception sensitivity can be improved.
By making a plurality of hops per symbol, the effect of frequency diversity can be obtained, and good reception characteristics can be obtained with respect to frequency selective fading and interference.

[0004]

However, a conventional frequency hopping transmitter using a frequency hopping pattern as shown in FIG. 7 can realize frequency detection of FSK. However, when PSK or the like is used, f ₁ is used. ~f _4n is for using different frequencies, can not be delayed detection for the frequency after one symbol differs not maintain phase continuity.
In addition, when synchronous detection is used, a carrier recovery circuit is required for each frequency. If the total number of hops increases, the circuit becomes complicated and carrier recovery becomes difficult.

The frequency hopping transmitter and the frequency hopping receiver are required to be able to perform delay detection and synchronous detection even when the total number of hops is increased.

In order to satisfy this demand, the present invention provides a frequency hopping transmitter capable of performing delay detection and synchronous detection on the receiving side even if the total number of hops is increased, and a delay detection and transmission system capable of increasing the total number of hops. An object of the present invention is to provide a frequency hopping receiver capable of performing synchronous detection.

[0007]

In order to solve the above-mentioned problems, a frequency hopping transmitter according to the present invention prepares a modulator for modulating data to be transmitted and a plurality of hopping patterns equal to a symbol period. The same hopping pattern is used in the same slot among the patterns, a hopping pattern generation circuit that switches the hopping pattern for each slot, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, and a modulator that uses the output of the digital synthesizer. And a mixer circuit for frequency-converting the output of the above to an RF signal.

Thus, a frequency hopping transmitter capable of performing delay detection or synchronous detection on the receiving side even when the total number of hops is increased is obtained.

In order to solve the above problem, a frequency hopping receiver according to the present invention prepares a plurality of hopping patterns equal to a symbol period, uses the same hopping pattern in the same slot among a plurality of hopping patterns, and A hopping pattern generation circuit for switching a hopping pattern, a digital synthesizer for switching a frequency in accordance with an output of the hopping pattern generation circuit, an RF circuit for converting a received signal into an IF signal by an output of the digital synthesizer, and an output of the hopping pattern generation circuit A buffer memory or a sample-and-hold circuit for holding the output of the RF circuit at the switching timing, a synchronous detection circuit for synchronously detecting the output of the buffer memory or the sample-and-hold circuit, and hopping to each of the outputs of the synchronous detection circuit A weighting circuit to weight according to the RSSI value is a level of a received signal for each turn,
The configuration includes a combining circuit that combines the outputs of the weighting circuits and a data determination circuit that determines the output of the combining circuit based on a predetermined threshold.

Thus, a frequency hopping receiver capable of performing delay detection and synchronous detection even when the total number of hops is increased is obtained.

[0011]

DETAILED DESCRIPTION OF THE INVENTION A frequency hopping transmitter according to a first aspect of the present invention prepares a modulator for modulating data to be transmitted and a plurality of hopping patterns equal to a symbol period. In the same slot, the same hopping pattern is used, and a hopping pattern generation circuit that switches the hopping pattern for each slot, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, and an output of the digital synthesizer are used to output the modulator. And a mixer circuit for converting the frequency into an RF signal.

With this configuration, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that the receiving side can perform delay detection and synchronous detection.

A frequency hopping receiver according to a second aspect prepares a plurality of hopping patterns equal to the symbol period, uses the same hopping pattern in the same slot among the plurality of hopping patterns, and switches the hopping pattern for each slot. A hopping pattern generation circuit, a digital synthesizer for switching a frequency according to the output of the hopping pattern generation circuit, an RF circuit for converting a received signal into an IF signal by an output of the digital synthesizer, and an RF for switching the output of the hopping pattern generation circuit A buffer memory or a sample and hold circuit for holding the output of the circuit, a synchronous detection circuit for synchronously detecting the output of the buffer memory or the sample and hold circuit, and reception of each hopping pattern for each of the outputs of the synchronous detection circuit A weighting circuit that weights according to an RSSI value that is a signal level, a combining circuit that combines the outputs of the weighting circuits, and a data determination circuit that determines the output of the combining circuit based on a predetermined threshold value. It is what it was.

With this configuration, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that synchronous detection can be realized, and maximum ratio combining diversity using synchronous detection with excellent reception characteristics. 1 received
It has the effect that one antenna and a receiving circuit can be used.

According to a third aspect of the present invention, the frequency hopping receiver prepares a plurality of hopping patterns equal to the symbol period, uses the same hopping pattern in the same slot among the plurality of hopping patterns, and switches the hopping pattern for each slot. A hopping pattern generation circuit, a digital synthesizer for switching the frequency according to the output of the hopping pattern generation circuit, and a R with a limiter amplifier for converting the received signal into an IF signal from the output of the digital synthesizer and limiting the IF signal
An F circuit, a delay circuit for delaying the output of the RF circuit with a limiter amplifier by one symbol, a delay detection circuit for obtaining a change between the output of the RF circuit with a limiter amplifier and the output of the delay circuit, and hopping the output of the delay detection circuit A buffer memory or a sample-and-hold circuit that holds the output of the pattern generation circuit at the switching timing, and a weighting circuit that weights each of the outputs of the buffer memory or the sample-and-hold circuit in accordance with the RSSI value that is the level of the received signal for each hopping pattern And a combining circuit that combines the outputs of the weighting circuits, and a data determination circuit that determines the output of the combining circuit based on a predetermined threshold.

With this configuration, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that delayed detection can be realized, and the receiving sensitivity is slightly inferior to synchronous detection, but the circuit configuration is simple. Has the effect that delay detection can be realized.

According to a fourth aspect of the present invention, the frequency hopping receiver prepares a plurality of hopping patterns equal to the symbol period, uses the same hopping pattern in the same slot among the plurality of hopping patterns, and switches the hopping pattern for each slot. A hopping pattern generation circuit, a digital synthesizer for switching a frequency according to the output of the hopping pattern generation circuit, and an RF with an AGC amplifier for converting a received signal into an IF signal from the output of the digital synthesizer and for keeping the amplitude of the IF signal constant
Circuit, a delay circuit for delaying the output of the RF circuit with an AGC amplifier by one symbol, a delay detection circuit for obtaining a change between the output of the RF circuit with an AGC amplifier and the output of the delay circuit, and a hopping pattern generation of the output of the delay detection circuit A buffer memory or a sample-and-hold circuit that holds the circuit output at the switching timing; a combining circuit that combines each of the buffer memory or the sample-and-hold circuit output; and a data determination circuit that determines the output of the combining circuit based on a predetermined threshold value. It was decided to have.

With this configuration, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that it is possible to realize differential detection, and a multiplication process is performed in the differential detection unit. This has the effect that the subsequent processing becomes extremely simple.

A frequency hopping receiver according to a fifth aspect prepares a plurality of hopping patterns equal to a symbol period, uses the same hopping pattern in the same slot among the plurality of hopping patterns, and switches the hopping pattern for each slot. A hopping pattern generation circuit, a digital synthesizer for switching a frequency according to the output of the hopping pattern generation circuit, an RF circuit for converting a received signal into an IF signal by an output of the digital synthesizer, and an RF for switching the output of the hopping pattern generation circuit A buffer memory or a sample and hold circuit for holding an output of the circuit, a weighting circuit for weighting the output of the buffer memory or the sample and hold circuit, a combining circuit for combining each of the outputs of the weighting circuit, and a combining circuit. A data determination circuit for determining a force by a predetermined threshold value, and an error between a training signal and an output of a synthesis circuit when a training signal portion is used, and reception data output from the data determination circuit otherwise. An error detection circuit for obtaining an error from an output of the synthesis circuit;
And a weight setting circuit for obtaining a weight for minimizing the error.

With this configuration, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that maximum ratio combining that minimizes the error can be performed. The maximum ratio combining diversity operation using synchronous detection has an effect that an adaptive array operation for canceling interference when there is interference can be realized with one antenna and a receiving circuit.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram showing a frequency hopping transmitter according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a frequency hopping transmitter according to Embodiment 1 of the present invention, and FIG. FIG. 15 is a pattern diagram showing a frequency hopping pattern in a frequency hopping receiver according to Embodiments 2, 3, 4, and 5;

In FIG. 1, 1 modulates transmission data.
Modulation circuit 2, hopping pattern equal to symbol period
Multiple hopping patterns, and the same among multiple hopping patterns
Use the same hopping pattern in the slot and
Hopping pattern that switches hopping patterns for each unit
The turn generation circuit 3 and the hopping pattern generation circuit 2
Digital synthesizer that switches frequency according to output
(DDS, Direct-ct Digital Synt
hesizer), 4 is the output of digital synthesizer 3
The frequency of the output of the modulation circuit 1 into an RF signal
It is a mixer circuit. For example, TDMA (Time D
Ivision Multiple Access)
Is the same hopping pattern within one slot as shown in FIG.
Turn f ₁~ F_FourAnd in the next slot f_Five~ F₈For
Switch the hopping pattern for each slot
And send it. The number of hops in the slot is the same as before
Clock frequency of the digital synthesizer.
The total hopping number can be increased without increasing the wave number.

The operation of the thus configured frequency hopping transmitter will be described.

In FIG. 1, a modulation circuit 1 modulates input transmission data and outputs its output to a mixer circuit 4. The mixer circuit 4 converts the frequency of the output of the modulation circuit 1 into an RF signal by the output of the digital synthesizer 3 whose frequency is switched according to the output of the hopping pattern generation circuit 2, and transmits the RF signal from the transmission antenna 4a.

As described above, in the present embodiment, a modulation circuit 1 for modulating data to be transmitted and a plurality of hopping patterns equal to the symbol period are prepared, and the same hopping pattern in the same slot among a plurality of hopping patterns is prepared. , A hopping pattern generation circuit 2 for switching a hopping pattern for each slot, a digital synthesizer 3 for switching a frequency according to the output of the hopping pattern generation circuit 2, and an output of the modulation circuit 1 to an RF signal by an output of the digital synthesizer 3. By providing the mixer circuit 4 for frequency conversion, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that it is possible to perform delay detection and synchronous detection on the receiving side.

(Embodiment 2) FIG. 3 is a block diagram showing a frequency hopping receiver according to Embodiment 2 of the present invention. The frequency hopping pattern used in the present embodiment is the pattern shown in FIG. 2 as in the case of the first embodiment.

In FIG. 3, reference numeral 5 denotes a hopping pattern generating circuit for preparing a plurality of hopping patterns equal to the symbol period, using the same hopping pattern in the same slot among a plurality of hopping patterns, and switching the hopping pattern for each slot; Is a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit 5. The digital synthesizer 6 uses a frequency hopping pattern of a symbol period as shown in FIG. 2 and switches the frequency hopping pattern for each slot. Reference numeral 7 denotes an RF circuit for converting a received signal into an IF signal based on the output of the digital synthesizer 6, reference numeral 7a denotes a receiving antenna, and reference numeral 8 denotes a buffer memory for holding the output of the RF circuit 7 at the timing of switching the output of the hopping pattern generation circuit 5. . The buffer memory 8 holds the output of the RF circuit 7 and adjusts the timing so that signals transmitted at four frequencies per symbol can be processed at the same time. Chip 1 of output signal of buffer memory 8
チ ッ プ to chip 4 (chip 1 to chip 4) correspond to each of the signals sent at four frequencies per symbol.
Reference numerals 9 and 10 denote synchronous detection circuits for synchronously detecting the output of the buffer memory 8, respectively. Reference numerals 11 and 12 denote the output of the synchronous detection circuits 9 and 10 in accordance with the RSSI value of the output of the hopping pattern generation circuit 5 for each hopping pattern. A weighting circuit 13 for weighting is a combining circuit for combining the outputs of the weighting circuits 11 and 12. The combining circuit 13 can obtain a frequency diversity effect by adding and combining each of the signals transmitted at four frequencies per symbol.
Reference numeral 14 denotes a data determination circuit that determines the output voltage of the combining circuit 13 based on a predetermined threshold.

The operation of the thus configured frequency hopping receiver will be described.

A radio signal having a frequency hopping pattern as shown in FIG. 2 is received by the receiving antenna 7a and output to the RF circuit 7 as a received signal. The RF circuit 7 converts the received signal into an IF signal based on the output of the digital synthesizer 6 that switches the frequency according to the pattern output from the hopping pattern generation circuit 5. The buffer memory 8 holds the output of the RF circuit 7 and adjusts the timing so that signals transmitted at four frequencies per symbol can be processed at the same time. Buffer memory 8
Output signals of chips 1 to 4 (chips 1 to 4)
p4) corresponds to each of the signals sent at four frequencies per symbol. The output of the buffer memory 8 is synchronously detected by synchronous detection circuits 9 and 10, respectively. Outputs of the synchronous detection circuits 9 and 10 are supplied to weighting circuits 11 and 12, respectively.
Weighting is performed by weights W1 to W4 according to the RSSI value for each frequency hopping pattern. Weighting circuit 11,
The output of the synthesizing circuit 13 is synthesized by the synthesizing circuit 13, and the content of the output of the synthesizing circuit 13 is judged by the data judging circuit 14.

In the present embodiment, the buffer memory 8 is shown as holding the output of the RF circuit 7.
The present invention is not limited to this, and a sample and hold circuit may be used instead of the buffer memory. This is the same in the following third to fifth embodiments.

As described above, in the present embodiment, the frequency hopping receiver switches the frequency hopping pattern for each slot in the hopping pattern generation circuit 5, so that the carrier recovery circuit does not increase even if the total number of hops is increased. Therefore, the frequency can be ideally switched. That is, even if the total number of hops is increased, the number of hops in one slot does not increase, so that a synchronous circuit can be realized. Also, by performing weighting synthesis on the signals synchronously detected by the synchronous detection circuits 9 and 10 in accordance with the RSSI value in each frequency hopping pattern, maximum ratio combining diversity reception using synchronous detection having excellent reception characteristics can be performed by one antenna. And a receiving circuit.

(Embodiment 3) FIG.4 is a block diagram showing a frequency hopping receiver according to Embodiment 3 of the present invention. The frequency hopping pattern used in the present embodiment is the pattern shown in FIG. 2 as in the case of the first embodiment.

In FIG. 4, reference numeral 15 denotes a hopping pattern generating circuit for preparing a plurality of hopping patterns equal to the symbol period, using the same hopping pattern in the same slot among a plurality of hopping patterns, and switching the hopping pattern for each slot; Is a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit 15. The digital synthesizer 16 uses a hopping pattern of a symbol period as shown in FIG. 2 and switches the hopping pattern for each slot. Reference numeral 17 denotes an RF circuit with a limiter amplifier that has a limiter amplifier that limits the received signal, and that converts the received signal into an IF signal by the digital synthesizer 16.
17a is a receiving antenna, 18 is a delay circuit for delaying the output of the RF circuit 17 with limiter amplifier by one symbol, 19 is a delay detection circuit for examining a change between the output of the RF circuit 17 with limiter amplifier and the output of the delay circuit 18, 20 A buffer memory holds the output of the delay detection circuit 19 at the timing of switching the output of the hopping pattern generation circuit 15. The buffer memory 20 holds the output of the delay detection circuit 19 and adjusts the timing so that signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 of output signal of buffer memory 20
Chip 4 (chip1 to chip4) corresponds to each of the signals sent at four frequencies per symbol. 2
Reference numerals 1 and 22 denote weighting circuits for weighting the output of the hopping pattern generation circuit 15 in accordance with the RSSI value for each frequency hopping pattern, and reference numeral 23 denotes a combining circuit for combining the outputs of the weighting circuits 21 and 22. The combining circuit 23 can obtain a frequency diversity effect by adding and combining each of the signals transmitted at four frequencies per symbol. Reference numeral 24 denotes a data determination circuit that determines the output of the synthesis circuit 23 based on a predetermined threshold.

The operation of the thus configured frequency hopping receiver will be described.

A radio signal having a frequency hopping pattern as shown in FIG. 2 is received by the receiving antenna 17a and output to the RF circuit 17 with a limiter amplifier as a received signal. The RF circuit 17 with a limiter amplifier limits the received signal and generates the hopping pattern
The received signal is changed based on the output of the digital synthesizer 16 that switches the frequency according to the pattern output from the
Convert to F signal. This IF signal is detected by a delay detection section comprising a delay circuit 18 and a delay detection circuit 19, and a detection signal as an output of the delay detection circuit 19 is held in a buffer memory 20. The buffer memory 20 holds the output of the delay detection circuit 19 and adjusts the timing so that signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 to chip 4 (chip 1 to chip 4) of the output signal of the buffer memory 20 correspond to each of the signals transmitted at four frequencies per symbol. The outputs of the buffer memory 20 are output to the weighting circuits 21 and 22 for each frequency hopping pattern.
Weighting is performed by weights W1 to W4 according to the SSI value. The outputs of the weighting circuits 21 and 22 are combined by a combining circuit 23, and the contents of the output of the combining circuit 23 are determined by a data determination circuit 24.

As described above, in the present embodiment, the frequency hopping receiver switches the hopping pattern for each slot in the hopping pattern generation circuit 15 so that the carrier reproduction circuit does not increase even if the total number of hops is increased. The frequency can be ideally switched. That is, even if the total number of hops is increased,
Since the number of hops in one slot does not increase, differential detection can be realized. In addition, R with limiter amplifier
The output signal of the F circuit 17 is delayed by one symbol by the one-symbol delay circuit 18, and the change between the output signal of the RF circuit 17 with limiter amplifier 17 and the output signal of the one-symbol delay circuit 18 is obtained by the delay detection circuit 19. Although the receiving sensitivity is slightly inferior to the synchronous detection, the delay detection unit 1 has a simple circuit configuration.
8, 19 can be configured.

(Embodiment 4) FIG. 5 is a block diagram showing a frequency hopping receiver according to Embodiment 4 of the present invention. The frequency hopping pattern used in the present embodiment is the pattern shown in FIG. 2 as in the case of the first embodiment.

In FIG. 5, reference numeral 25 denotes a hopping pattern generating circuit for preparing a plurality of hopping patterns equal to the symbol period, using the same hopping pattern in the same slot among a plurality of hopping patterns, and switching the hopping pattern for each slot; Is a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit 25. The digital synthesizer 26 uses a frequency hopping pattern of a symbol period as shown in FIG. 2, and switches the frequency hopping pattern for each slot. Reference numeral 27 denotes an RF with an AGC amplifier which has an AGC amplifier for making the amplitude of the received signal constant, and converts the received signal into an IF signal by the digital synthesizer
Circuit, 27a is a receiving antenna, 28 is R with AGC amplifier
A delay circuit for delaying the output of the F circuit 27 by one symbol,
9 is an output of the RF circuit 27 with the AGC amplifier and the delay circuit 28
A delay detection circuit 30 for examining a change from the output of the hopping pattern generation circuit 25 is a buffer memory for holding the output of the delay detection circuit 29 at the switching timing of the output of the hopping pattern generation circuit 25. The buffer memory 30 holds the output of the delay detection circuit 29 and adjusts the timing so that signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 to chip 4 (chip 1 to chip 4) of the output signal of the buffer memory 30 correspond to each of the signals transmitted at four frequencies per symbol. Reference numeral 31 denotes a combining circuit that combines the outputs of the buffer memory 30. The combining circuit 31 can obtain a frequency diversity effect by adding and combining each of the signals transmitted at four frequencies per symbol. 32 is a combining circuit 31
Is a data judgment circuit for judging an output of the data by a predetermined threshold value.

The operation of the thus configured frequency hopping receiver will be described.

A radio signal having a frequency hopping pattern as shown in FIG. 2 is received by the receiving antenna 27a, and is output to the RF circuit with AGC amplifier 27 as a received signal.
The RF circuit 27 with an AGC amplifier converts the received signal to an IF signal based on the output of the digital synthesizer 16 that keeps the amplitude of the received signal constant and switches the frequency according to the pattern output from the hopping pattern generation circuit 15. This IF signal is detected by a delay detection section including a delay circuit 28 and a delay detection circuit 29, and a detection signal as an output of the delay detection circuit 29 is held in a buffer memory 30. In the buffer memory 30, the delay detection circuit 19
And the timing is adjusted so that each of the signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 of output signal of buffer memory 20
チ ッ プ to chip 4 (chip 1 to chip 4) correspond to each of the signals sent at four frequencies per symbol. The output of the buffer memory 20 is synthesized by the synthesizing circuit 23, and the content of the output of the synthesizing circuit 23 is judged by the data judging circuit 24.

As described above, in the present embodiment, the frequency hopping receiver switches the hopping pattern for each slot in the hopping pattern generation circuit 25, so that the carrier reproduction circuit does not increase even if the total number of hops is increased. The frequency can be ideally switched. That is, even if the total number of hops is increased,
Since the number of hops in one slot does not increase, differential detection can be realized. In addition, RF with AGC amplifier
The output signal of the circuit 27 is delayed by one symbol by the one-symbol delay circuit, and the difference between the output signal of the RF circuit with AGC amplifier 27 and the output signal of the one-symbol delay circuit is obtained by the delay detection circuit 29, whereby the delay is obtained. Detector 28, 2
9 can be configured. The reception characteristics are the same as in the third embodiment, and the delay detection is a multiplication process. However, since the delay detection circuit 29 is equivalent to weighting at the signal level, the weighting circuits 21 and 22 in FIG. , Makes the process easier.

(Embodiment 5) FIG. 6 is a block diagram showing a frequency hopping receiver according to Embodiment 5 of the present invention. The frequency hopping pattern used in the present embodiment is the pattern shown in FIG. 2 as in the case of the first embodiment.

In FIG. 6, reference numeral 33 denotes a hopping pattern generating circuit for preparing a plurality of hopping patterns equal to the symbol period, using the same hopping pattern in the same slot among a plurality of hopping patterns, and switching the hopping pattern for each slot. Is a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit 33. The digital synthesizer 34 uses a frequency hopping pattern of a symbol period as shown in FIG. 2 and switches the frequency hopping pattern for each slot. 35 is a digital synthesizer 3
Reference numeral 35a denotes a receiving antenna, and reference numeral 36 denotes a buffer memory that holds the output of the RF circuit 35 at the timing of switching the output of the hopping pattern generation circuit 33 at the timing of switching the output of the hopping pattern generation circuit 33. The buffer memory 36 holds the output of the RF circuit 35 and adjusts the timing so that each of the signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 to chip 4 (chip 1) of the output signal of the buffer memory 36
Ｃｈchip4) correspond to each of the signals sent at four frequencies per symbol. 37 and 38 are weighting circuits for weighting the output of the hopping pattern generation circuit 33 for each frequency hopping pattern, and 39 is a weighting circuit 3
This is a synthesis circuit that synthesizes the outputs of 7 and 38. Synthesis circuit 3
In No. 9, a frequency diversity effect can be obtained by adding and combining each of the signals transmitted at four frequencies per symbol. Reference numeral 40 denotes a data determination circuit that determines the output of the synthesis circuit 39 based on a predetermined threshold value. Reference numeral 41 denotes a case where a training signal unit 43 described later is used (when a training signal is received). Of the data judgment circuit 4
An error detection circuit for obtaining an error between the received data output from 0 and the output of the synthesis circuit. A weighting circuit 42 minimizes the output of the error detection circuit 41 by an adaptive algorithm such as an LMS (Least Mean Squares) algorithm. A weight setting circuit for setting the weights of 37 and 38, and 43 is a training signal section for generating a training signal.

The operation of the thus configured frequency hopping receiver will be described.

A radio signal having a frequency hopping pattern as shown in FIG. 2 is received by the receiving antenna 35a and output to the RF circuit 35 as a received signal. RF circuit 35
Converts the received signal into an IF signal based on the output of the digital synthesizer 34 that switches the frequency according to the pattern output from the hopping pattern generation circuit 33. The buffer memory 36 holds the output of the RF circuit 35 and adjusts the timing so that each of the signals transmitted at four frequencies per symbol can be processed in the same time. Chip 1 to chip 4 (chip 1 to chip 4) of the output signal of the buffer memory 36 correspond to each of the signals transmitted at four frequencies per symbol. The outputs of the buffer memory 36 are weighted by weighting circuits 37 and 38 for each frequency hopping pattern of the output of the hopping pattern generation circuit 33. The weights of the weighting circuits 37 and 38 are set so as to minimize the output of the error detection circuit 41. The outputs of the weighting circuits 37 and 38 are combined by a combining circuit 39, and the output of the combining circuit 39 is
The data determination circuit 14 determines the content. The error detection circuit 41 detects an error between the training signal and the output of the synthesis circuit when the training signal unit 43 that generates the training signal is used, and otherwise uses the data determination circuit 4.
An error between the received data output from 0 and the output of the combining circuit is determined, and the weight setting circuit 42 determines the weight W1 of the weighting circuits 37 and 38 so as to minimize the output of the error detection circuit 41.
To W4.

As described above, in the present embodiment, the frequency hopping receiver switches the frequency hopping pattern for each slot in the hopping pattern generation circuit 35, so that even if the total number of hops is increased, the number of carrier recovery circuits is increased. Without switching, the frequency can be ideally switched. That is, even if the total number of hops is increased, the number of hops in one slot does not increase, so that the maximum ratio combining that minimizes the error can be performed, and when there is no interference, the synchronous detection is used. The maximum ratio combining diversity receiving operation and the adaptive array operation for canceling the interference when there is interference can be realized with one antenna and a receiving circuit.

[0048]

As described above, according to the frequency hopping transmitter according to the first aspect of the present invention, a modulator for modulating data to be transmitted and a plurality of hopping patterns equal to the symbol period are prepared. Of the hopping patterns, the same hopping pattern is used in the same slot, and the hopping pattern generation circuit that switches the hopping pattern for each slot, the digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, and the output of the digital synthesizer By having a mixer circuit that converts the output of the modulator to an RF signal, the number of hops in the same slot does not increase even if the total number of hops is increased, so that it is possible to perform delay detection or synchronous detection on the receiving side. The advantageous effect that it can be obtained is obtained.

According to the frequency hopping receiver of the second aspect, a plurality of hopping patterns equal to the symbol period are prepared, and the same hopping pattern is used in the same slot among the plurality of hopping patterns, and the hopping pattern is set for each slot. Switching circuit, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, an RF circuit that converts a received signal into an IF signal by the output of the digital synthesizer, and a switching timing of the output of the hopping pattern generation circuit A buffer memory or a sample-and-hold circuit for holding the output of the RF circuit, a synchronous detection circuit for synchronously detecting the output of the buffer memory or the sample-and-hold circuit, and a hopping pattern for each of the outputs of the synchronous detection circuit. It has a weighting circuit that weights according to the RSSI value that is the level of the received signal, a combining circuit that combines each of the outputs of the weighting circuit, and a data determination circuit that determines the output of the combining circuit by a predetermined threshold value Thus, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that synchronous detection can be realized, and maximum ratio combining diversity reception using synchronous detection having excellent reception characteristics is one. An advantageous effect can be obtained that can be realized by an antenna and a receiving circuit.

According to the frequency hopping receiver of the third aspect, a plurality of hopping patterns equal to the symbol period are prepared, the same hopping pattern is used in the same slot among the plurality of hopping patterns, and the hopping pattern is set for each slot. A hopping pattern generation circuit for switching the frequency, a digital synthesizer for switching the frequency according to the output of the hopping pattern generation circuit, and an RF circuit with a limiter amplifier for converting the reception signal into an IF signal from the output of the digital synthesizer and limiting the IF signal. The output of the RF circuit with limiter amplifier is 1
Delay circuit for symbol delay and RF with limiter amplifier
A delay detection circuit for obtaining a change between a circuit output and a delay circuit output; a buffer memory or a sample and hold circuit for holding the output of the delay detection circuit at a switching timing of an output of a hopping pattern generation circuit; a buffer memory or a sample and hold circuit A weighting circuit that weights each of the outputs of the circuit according to the RSSI value that is the level of the received signal for each hopping pattern; a combining circuit that combines each of the outputs of the weighting circuit; and a predetermined threshold for the output of the combining circuit. By having a data determination circuit that determines based on the value, even if the total number of hops is increased, the number of hops in the same slot does not increase, so that delayed detection can be realized, and the receiving sensitivity is slightly higher than that of synchronous detection. The advantage is that it is possible to realize delayed detection, which is inferior but has a simple circuit configuration. It is.

According to the frequency hopping receiver according to the fourth aspect, a plurality of hopping patterns equal to the symbol period are prepared, the same hopping pattern is used in the same slot among the plurality of hopping patterns, and the hopping pattern is set for each slot. With a hopping pattern generation circuit that switches the frequency, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, and an AGC amplifier that converts the received signal to an IF signal from the output of the digital synthesizer and keeps the amplitude of the IF signal constant An RF circuit, a delay circuit for delaying the output of the RF circuit with an AGC amplifier by one symbol, a delay detection circuit for calculating a change between the output of the RF circuit with an AGC amplifier and the output of the delay circuit, and a hopping pattern for the output of the delay detection circuit Generator circuit output switching tie A buffer memory or a sample-and-hold circuit that holds the data in the memory, a combining circuit that combines each of the outputs of the buffer memory or the sample-and-hold circuit, and a data determination circuit that determines the output of the combining circuit with a predetermined threshold. Even if the total number of hops is increased, the number of hops in the same slot does not increase, so that it is possible to realize delay detection, and a multiplication process is performed in the delay detection unit. The advantageous effect of being able to simplify is obtained.

According to the frequency hopping receiver according to the fifth aspect, a plurality of hopping patterns equal to the symbol period are prepared, the same hopping pattern is used in the same slot among the plurality of hopping patterns, and the hopping pattern is set for each slot. Switching circuit, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, an RF circuit that converts a received signal into an IF signal by the output of the digital synthesizer, and a switching timing of the output of the hopping pattern generation circuit A buffer memory or a sample-and-hold circuit that holds the output of the RF circuit, a weighting circuit that weights the output of the buffer memory or the sample-and-hold circuit, a combining circuit that combines each of the outputs of the weighting circuit, A data judgment circuit for judging the output of the road by a predetermined threshold value, and an error between the training signal and the output of the synthesis circuit when a training signal portion is used, and a reception error output from the data judgment circuit otherwise. By having an error detection circuit that calculates an error between the data and the output of the synthesis circuit, and a weight setting circuit that calculates a weight that minimizes the error, even if the total hopping number is increased,
Since the number of hoppings in the same slot does not increase, maximum ratio combining that minimizes errors can be performed.If there is no interference, maximum ratio combining operation using synchronous detection is performed. Has an advantageous effect that an adaptive array operation for canceling interference can be realized with one antenna and a receiving circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a frequency hopping transmitter according to a first embodiment of the present invention.

FIG. 2 is a pattern diagram showing a frequency hopping pattern in a frequency hopping transmitter according to Embodiment 1 of the present invention and a frequency hopping receiver according to Embodiments 2, 3, 4, and 5 of the present invention.

FIG. 3 is a block diagram illustrating a frequency hopping receiver according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a frequency hopping receiver according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a frequency hopping receiver according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram illustrating a frequency hopping receiver according to a fifth embodiment of the present invention.

FIG. 7 is a pattern diagram showing a frequency hopping pattern in a conventional frequency hopping transmitter that hops a frequency in a cycle shorter than a symbol cycle.

[Explanation of symbols]

1 Modulation circuit 2, 5, 15, 25, 33 Hopping pattern generation circuit 3, 6, 16, 26, 34 Digital synthesizer 4 Mixer circuit 4a Transmission antenna 7, 35 RF circuit 7a, 17a, 27a, 35a Receiving antenna 8, 20 , 30, 36 Buffer memory 9, 10 Synchronous detection circuit 11, 12, 21, 22, 37, 38 Weighting circuit 13, 23, 31, 39 Synthesis circuit 14, 24, 32, 40 Data determination circuit 17 RF circuit with limiter amplifier 18, 28 delay circuit 19, 29 delay detection circuit 27 RF circuit with AGC amplifier 41 error detection circuit 42 weight setting circuit

Claims (5)

[Claims] 1. A modulator for modulating data to be transmitted and a plurality of hopping patterns equal to a symbol period are prepared.
The same hopping pattern in the same slot among the plurality of hopping patterns, using the same hopping pattern, a hopping pattern generation circuit that switches the hopping pattern for each slot, a digital synthesizer that switches the frequency according to the output of the hopping pattern generation circuit, A mixer circuit for frequency-converting the output of the modulator to an RF signal by the output of a digital synthesizer. 2. A hopping pattern generating circuit for preparing a plurality of hopping patterns equal to a symbol period, using the same hopping pattern in the same slot among the plurality of hopping patterns, and switching the hopping pattern for each slot, A digital synthesizer for switching a frequency according to the output of the pattern generation circuit, an RF circuit for converting a received signal into an IF signal by an output of the digital synthesizer, and an R circuit for switching the output of the hopping pattern generation circuit
A buffer memory or a sample and hold circuit for holding an output of the F circuit, a synchronous detection circuit for synchronously detecting the output of the buffer memory or the sample and hold circuit,
A weighting circuit that weights each of the outputs of the synchronous detection circuit in accordance with an RSSI value that is a level of the received signal for each of the hopping patterns; a combining circuit that combines each of the outputs of the weighting circuit; And a data determination circuit for determining an output of the frequency hopping signal based on a predetermined threshold value. 3. A hopping pattern generating circuit for preparing a plurality of hopping patterns equal to a symbol period, using the same hopping pattern in the same slot among the plurality of hopping patterns, and switching the hopping pattern for each slot; A digital synthesizer for switching a frequency according to an output of the pattern generation circuit, an RF circuit with a limiter amplifier for converting a received signal into an IF signal from the output of the digital synthesizer and limiting the IF signal, and an RF circuit with the limiter amplifier A delay circuit that delays the output of the delay circuit by one symbol, a delay detection circuit that calculates a change between the output of the RF circuit with limiter amplifier and the output of the delay circuit, and an output of the hopping pattern generation circuit that outputs the output of the delay detection circuit. Switchover A buffer memory or a sample hold circuit for holding at a timing, at the level of the buffer memory or the received signal for each of the hopping pattern in each of the output of said sample-hold circuit RSSI
A weighting circuit that weights according to a value, a combining circuit that combines each of the outputs of the weighting circuit, and a data determination circuit that determines the output of the combining circuit with a predetermined threshold value. Frequency hopping receiver. 4. A hopping pattern generation circuit for preparing a plurality of hopping patterns equal to a symbol period, using the same hopping pattern in the same slot among the plurality of hopping patterns, and switching the hopping pattern for each slot; A digital synthesizer for switching a frequency according to an output of a pattern generation circuit, an RF circuit with an AGC amplifier for converting a received signal into an IF signal from the output of the digital synthesizer and for keeping the amplitude of the IF signal constant, and the AGC amplifier A delay circuit that delays the output of the RF circuit with one symbol by one symbol; a delay detection circuit that calculates a change between the output of the RF circuit with an AGC amplifier and the output of the delay circuit; and a hopping pattern generation circuit that outputs the output of the delay detection circuit. At the output switching timing A buffer memory or a sample hold circuit for lifting and a combining circuit for combining each of said buffer memory or the sample-and-hold circuit output,
A frequency hopping receiver comprising: a data determination circuit that determines an output of the synthesis circuit based on a predetermined threshold value. 5. A hopping pattern generation circuit for preparing a plurality of hopping patterns equal to a symbol period, using the same hopping pattern in the same slot among the plurality of hopping patterns, and switching the hopping pattern for each slot; A digital synthesizer for switching a frequency according to the output of the pattern generation circuit, an RF circuit for converting a received signal into an IF signal by an output of the digital synthesizer, and an R circuit for switching the output of the hopping pattern generation circuit
A buffer memory or a sample and hold circuit for holding an output of the F circuit, a weighting circuit for weighting an output of the buffer memory or the sample and hold circuit,
A combining circuit that combines each of the outputs of the weighting circuit;
A data determination circuit that determines the output of the synthesis circuit based on a predetermined threshold, and an error between the training signal and the output of the synthesis circuit when a training signal unit is used,
In addition to the above, an error detection circuit for obtaining an error between the received data output from the data determination circuit and the output of the synthesis circuit, and a weight setting circuit for obtaining the weight for minimizing the error are provided. Frequency hopping receiver.