JP2001102579A - Semiconductor device having trench gate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having trench gates, where the increase in its channel density and the promotion of its conductivity modulation are made compatible with each other. SOLUTION: An IGBT has a p-type emitter layer 17, and a p-type base layer 12 between which an n-type base layer 11 is disposed. In the IGBT, each main trench 25 and each transverse trench 26 are so formed that they pass through the p-type base layer 12 to reach the n-type base layer 11. Columns 27 so comprises columns 27a having the formed transverse trenches 26 and columns 27b having no transverse trench 26 that the columns 27a, 27b are mixed with each other and are provided alternately as interposing each main trench 25 between the respective adjacent columns 27a, 27b. In the surface of each portion of the p-type base layer 12 which is surrounded by each main trench 25 and each transverse trench 26, each n-type emitter layer 15 is so formed, that each central exposed portion 12a of the p-type base layer 12 is left in each layer 15. Each emitter electrode 19 is so disposed as to be contacted with each n-type emitter layer 15 and each central exposed portion 12a of the p-type base layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor (IGBT).
tor)) and the like.

[0002]

2. Description of the Related Art In an insulated gate semiconductor device such as an IGBT, conduction loss can be reduced by a buried trench gate. This is because the channel density can be increased by forming the trench gate finely, and the conductivity modulation can be promoted by forming the deep trench gate.

FIG. 9 shows a conventional IGBT with a trench gate.
FIG. 10 is a sectional view showing a section taken along line XX of FIG.

In this IGBT, the n-type base layer 1
The p-type base layer 102 is formed on the substrate 01. A plurality of trenches 103 are formed in a stripe shape so as to penetrate the p-type base layer 102 and reach the n-type base layer 101. A gate electrode 104 is buried in the trench 103 via a gate insulating film 111 formed on the side wall and the bottom surface. An n-type emitter layer 105 is formed in the p-type base layer 102 so as to be in contact with the trench 103.

The p-type base layer 102 and the n-type emitter layer 10
5. An interlayer insulating film 108 is selectively formed on the trench 103. On the interlayer insulating film 108, the emitter electrode 1
09 is provided and contacts the n-type emitter layer 105 and the p-type base layer 102 via the contact holes.
On the surface on the opposite side of the n-type base layer 101, a p-type emitter layer 107 is formed, and further, a collector electrode 110 is provided so as to be in contact with the p-type emitter layer.

To operate the IGBT, a positive bias is applied to the gate electrode 104 with a positive bias applied between the collector electrode 110 and the emitter electrode 109. Thus, an n-type inversion layer is formed in the p-type base layer 102 along the surface of the gate insulating film 111, and n
Electrons are injected from n-type emitter layer 105 into n-type base layer 101. On the other hand, holes are injected from the p-type emitter layer 107 into the n-type base layer 101 in accordance with the amount of injected electrons, and the n-type base layer 101 is filled with carriers to cause conductivity modulation. For this reason, the resistance of the n-type base layer 101 decreases, and the device is turned on.

[0007]

One factor that determines the conduction loss in the ON state of the entire device is the gate electrode 10.
4 is the resistance of the channel induced by. The resistance of the channel can be reduced by increasing the area of the region where the channel is induced, ie increasing the density of the channel region.

Another factor that determines the conduction loss in the ON state is the resistance of the n-type base layer 101 when the conductivity modulation occurs. The resistance of the n-type base layer 101 depends on the total amount of the filled carriers, and the total amount of the carriers is determined by the ratio between the electron current flowing from the n-type base layer 101 to the emitter electrode 109 and the hole current. When the distance between the trenches 103 is reduced, the resistance when holes are discharged to the emitter electrode 109 via the p-type base layer 102 increases, so that the amount of carriers filling the n-type base layer 101 increases. As a result, the conduction loss is reduced.

However, when the distance between the trenches 103 is determined, in the conventional structure, the density of the p-type base layer 102 increases as the channel density increases. That is, there is a trade-off relationship between the reduction of the channel resistance and the promotion of the conductivity modulation, and there is a limit to the reduction of the conduction loss. In addition, since a high current capacity is required for a high withstand voltage element, it is common to use the elements connected in parallel. However, in the conventional structure, the gate electrode and the main electrode (collector electrode,
(Electrode electrode). The capacitance causes a delay or non-uniformity in the switching operation, or causes a parasitic oscillation.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to reduce the conduction loss (increase the channel density and promote the conductivity modulation) exceeding the limit of the conventional device, and to facilitate the parallel connection of the trench. It is an object to provide a semiconductor device with a gate.

[0011]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
A semiconductor device with a trench gate, comprising: a first semiconductor layer of a first conductivity type; and a second semiconductor layer provided in the first semiconductor layer such that carriers of a second conductivity type can be injected into the first semiconductor layer. A second semiconductor layer of a conductivity type and a second semiconductor layer disposed on the first semiconductor layer so that carriers of the second conductivity type in the first semiconductor layer can be discharged out of the first semiconductor layer. A conductive third semiconductor layer, extending in a first direction along a surface of the third semiconductor layer, and penetrating the third semiconductor layer in a depth direction to reach the first semiconductor layer. A plurality of formed main trenches, and extending in a second direction substantially perpendicular to the first direction along a surface of the third semiconductor layer in a row between the main trenches, and Formed so as to penetrate the third semiconductor layer in the direction and reach the first semiconductor layer A plurality of transverse trenches,
A row between the main trenches, a row in which a horizontal trench is formed, and a row in which a horizontal trench is not formed are provided. A first conductivity type carrier can be injected into the first semiconductor layer through a gate electrode disposed in the first semiconductor layer and a channel induced in the third semiconductor layer by the gate electrode, thereby causing conductivity modulation. The third region surrounded by the main and transverse trenches;
A first conductive type fourth semiconductor layer formed along the main and transverse trenches so as to leave a central exposed portion of the third semiconductor layer on a surface of each portion of the semiconductor layer;
A first main electrode arranged to contact the semiconductor layer, and a second main electrode arranged to contact the center exposed portion of the third semiconductor layer and the fourth semiconductor layer. It is characterized by having.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a main dummy trench having substantially the same shape and extending in the same direction as the main trench is provided between the main trenches. A conductor is buried in the main dummy trench via an insulating film.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the conductor in the main dummy trench is connected to the second main electrode.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and repeated description will be made only when necessary.

FIG. 1 is a plan view showing a main part of an IGBT which is a semiconductor device with a trench gate according to an embodiment of the present invention. FIGS. 2 and 3 are respectively a II-II line of FIG.
FIG. 3 is a cross-sectional view showing a cross section taken along line III-III.

In this IGBT, the n-type base layer 1
A p-type base layer 12 is formed on 1. p-type base layer 1
2 through the p-type base layer 12 and the n-type base layer 11
, A main trench 25 and a transverse trench 26 are formed. The gate electrode 14 is buried in the trenches 25 and 26 via the gate insulating film 21 formed on the side wall and the bottom surface. In the p-type base layer 12,
The n-type emitter layer 15 is in contact with the trenches 25 and 26.
Is formed.

The p-type base layer 12, the n-type emitter layer 15,
On the trenches 25 and 26, an interlayer insulating film 18 is selectively formed. An emitter electrode 19 is provided on the interlayer insulating film 18, and the n-type emitter layer 1 is provided through a contact hole.
5 and the p-type base layer 12. On the surface opposite to the n-type base layer 11, a p-type emitter layer 17 is formed, and a collector electrode 20 is provided so as to be in contact with the p-type emitter layer.

As shown in FIG. 1, in a plan view of the device,
The main trench 25 has a plurality of rows extending in the Y direction, while the transverse trenches 26 have a plurality of rows extending in the X direction orthogonal to the Y direction in a row 27 between the main trenches 25. Rows 27 between main trenches 25 are provided every other transverse trench 2
The row 27a in which 6 is formed and the row 27b in which the transverse trench 26 is not formed are mixed. Therefore, in the plan view of the device, the main trench 25 and the transverse trench 26 form a layout in which a plurality of ladder-like trenches are arranged at intervals.

The n-type emitter layer 15 has a central exposed portion 12a of the p-type base layer 12 on the surface of each portion of the p-type base layer 12 surrounded by the main and transverse trenches 25 and 26.
Are formed along the main and transverse trenches 25, 26. The contact hole of the interlayer insulating film 18 is formed in the p-type base layer 1 surrounded by the main and transverse trenches 25 and 26.
2 is formed so as to correspond to each part. Therefore, the emitter electrode 19 contacts the exposed surface of the rectangular ring-shaped n-type emitter layer 15 and the central exposed portion 12a of the p-type base layer 12 surrounded by the contact hole through the contact hole.

To operate the IGBT, a positive bias is applied to the gate electrode 14 with a positive bias applied between the collector electrode 20 and the emitter electrode 19. Thereby, an n-type inversion layer is formed in the p-type base layer 12 along the surface of the gate insulating film 21, and electrons are injected from the n-type emitter layer 15 into the n-type base layer 11.
On the other hand, holes are injected from the p-type emitter layer 17 into the n-type base layer 11 according to the amount of injected electrons, and the n-type base layer 11 is filled with carriers, thereby causing conductivity modulation. For this reason, the resistance of the n-type base layer 11 decreases, and the device is turned on.

In the IGBT shown in FIGS. 1 to 3,
The trenches 25 and 26 are formed in a ladder shape, that is,
Are arranged like a ladder, so that the channel density can be increased. Further, the area of the p-type base layer 12 surrounded by the ladder-shaped trenches 25 and 26 for contacting the emitter electrode 19 is reduced. This makes it difficult for holes injected from the collector electrode 20 to flow out of the n-type base layer 11, and large conductivity modulation can be obtained in the n-type base layer 11. Therefore, both the channel resistance and the resistance of the n-type base layer are reduced, and the conduction loss of the entire device can be reduced.

FIG. 4 is a plan view showing a main part of an IGBT which is a semiconductor device with a trench gate according to another embodiment of the present invention. FIG. 5 is a sectional view showing a section taken along line VV of FIG.

The IGBT shown in FIGS. 4 and 5 is characterized in that two main dummy trenches 31 having substantially the same shape and extending in the same direction as the main trench 25 are provided between the main trenches 25. , And the IGBT shown in FIGS. In other words, it can be said that the trench used to form the ladder-shaped gate electrode 14 in the main trench 25 shown in FIG. A transverse dummy trench 32 is provided between the two main dummy trenches 31 by a transverse trench 26.
It is formed in the same manner as described above.

In the present invention, the channel density associated with one ladder-like gate electrode 14 is larger than that of two conventional stripe-like gate electrodes 104 (see FIG. 9). Therefore, the number of gate electrode stripes can be reduced without increasing the channel resistance as compared with the conventional structure.

In the dummy trenches 31 and 32, a conductor 33 provided in the same step as that of the gate electrode 14 is buried via an insulating film.
Connected to The conductor 33 is not necessarily the emitter electrode 19
However, the connection stabilizes the potential and stabilizes the operation of the device.

The region surrounded by the dummy trenches 31 and 32 is covered with the interlayer insulating film 18, so that the p-type base layer 12 does not contact the emitter electrode between the dummy trenches 31 and 32. For this reason, the contact area between the emitter electrode 19 and the p-type base layer 12 is further reduced, and higher conductivity modulation can be realized.

The adjacent ladder-like trenches 25
Increasing the distance between the gate electrodes 26 reduces the parasitic capacitance between the gate electrode 14 and the main electrodes (collector electrode 20 and emitter electrode 19), and reduces non-uniform operation and oscillation between elements connected in parallel. Will be suppressed. In particular, by forming both the gate electrode 14 and the conductor 33 of the dummy trench in a ladder shape instead of a mesh shape, the conductor 33 of the dummy trench can be formed not in the gate electrode 14 but in the emitter electrode 1.
9 can be easily connected.

As shown in FIG. 6, the main dummy trench 31 may have a stripe shape similar to a conventional trench of this type without providing the transverse dummy trench 32 between the main dummy trenches 31.

Further, a central exposed portion 12a of the p-type base layer 12 for contacting the emitter electrode 19 is formed on the surface of all the portions of the p-type base layer 12 surrounded by the main and transverse trenches 25 and 26. No need.
For example, as shown in FIG. 7, the center exposed portion 12a may be formed every other one of the transverse trenches 26. Furthermore, the shape of the area surrounded by the main and transverse trenches 25, 26 can be rectangular rather than square.

In addition, within the scope of the concept of the present invention, those skilled in the art can come up with various modified examples and modified examples, and these modified examples and modified examples fall within the scope of the present invention. I understand.

[0031]

According to the present invention, by employing a ladder-shaped trench gate, it is possible to provide a semiconductor device with a trench gate capable of simultaneously increasing channel density and promoting conductivity modulation. Further, by providing this effect, the distance between the two ladder-shaped gate electrodes can be increased, and the parasitic capacitance between the gate electrode and the main electrode can be reduced, thereby providing a semiconductor device with a trench gate that can be easily connected in parallel. Can be.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main part of an IGBT which is a semiconductor device with a trench gate according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a section taken along line II-II of FIG. 1;

FIG. 3 is a sectional view showing a section taken along line III-III in FIG. 1;

FIG. 4 is a plan view showing a main part of an IGBT which is a semiconductor device with a trench gate according to another embodiment of the present invention.

FIG. 5 is a sectional view showing a section taken along line VV of FIG. 4;

FIG. 6 is a plan view showing a modification of the embodiment shown in FIG. 4;

FIG. 7 is a plan view showing another modification of the embodiment shown in FIG. 4;

FIG. 8 is a plan view showing a modification of the embodiment shown in FIG. 1;

FIG. 9 is a plan view showing a conventional IGBT with a trench gate.

FIG. 10 is a sectional view showing a section taken along line XX of FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... n-type base layer 12 ... p-type base layer 14 ... gate electrode 15 ... n-type emitter layer 17 ... p-type emitter layer 18 ... interlayer insulating film 19 ... emitter electrode 20 ... collector electrode 21 ... gate insulating film 25 ... main trench 26 crossing trench 27 row between main trenches 31 main dummy trench 32 crossing dummy trench 33 conductor

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tomoki Inoue 1 Koga Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Research and Development Center Co., Ltd. No. 1 town Toshiba R & D Center

Claims (3)

[Claims] A first conductive type first semiconductor layer; and a second conductive type first semiconductor layer provided in the first semiconductor layer so that carriers of the second conductive type can be injected into the first semiconductor layer. 2 semiconductor layers, and the second conductivity type carriers in the first semiconductor layer
A third semiconductor layer of a second conductivity type disposed on the first semiconductor layer so as to be able to be discharged outside the semiconductor layer; and a third semiconductor layer extending in a first direction along a surface of the third semiconductor layer. A plurality of main trenches formed so as to penetrate the third semiconductor layer in the depth direction and reach the first semiconductor layer; and in a row between the main trenches, a surface of the third semiconductor layer. A plurality of traverses extending in a second direction substantially perpendicular to the first direction and extending through the third semiconductor layer in the depth direction to reach the first semiconductor layer. A trench between the main trenches, wherein a row in which a transverse trench is formed and a row in which a transverse trench is not formed; Gate disposed via gate insulating film A pole, and the main and traverse so that conductivity modulation can be caused by injecting carriers of the first conductivity type into the first semiconductor layer through a channel induced in the third semiconductor layer by the gate electrode. A first conductivity type fourth semiconductor layer formed along the main and transverse trenches at a surface of each portion of the third semiconductor layer surrounded by the trench so as to leave a central exposed portion of the third semiconductor layer. A first main electrode disposed to contact the second semiconductor layer; a second main electrode disposed to contact the central exposed portion of the third semiconductor layer and the fourth semiconductor layer. A main electrode;
A semiconductor device with a trench gate, comprising: 2. A main dummy trench having substantially the same shape and extending in the same direction as the main trench is provided between the main trenches, and a conductor is provided in the main dummy trench via an insulating film. The semiconductor device with a trench gate according to claim 1, wherein the semiconductor device is embedded. 3. The conductor in the main dummy trench,
3. The semiconductor device according to claim 2, wherein the second main electrode is connected to the second main electrode.
4. The semiconductor device with a trench gate according to claim 1.