JP2001102449A - Dual damascene etching method and manufacturing method of semiconductor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an etching method wherein a dual damascene structure is formed at an insulating film of low permittivity at high precision and good yield. SOLUTION: A dual damascene structure where a hole 106b is integrated with a channel 210a is formed at an insulating layer comprising a first organic SOG 203 of low permittivity and, through an intermediate insulating layer 204, a second organic SOG 208 of low permittivity, using a UHF band ECR plasma etching device of flat antenna type. Here, in the process where these etching layers are etched, the ratio between the etching gas flow rate and an oxygen gas flow rate which is supplied to the plasma etching device is 0.7-1.3. After the channel 210a is formed at the insulating film 108 with the intermediate insulating layer 204 as an etching stopper, the hole 206b is formed at the insulating film 203 with the intermediate insulating layer 204 as a mask. A gas comprising at least one kind of element among carbon, fluorine, and hydrogen is used as an etching gas, and a gas which supplies oxygen through dissociation in the plasma may be used instead of oxygen gas.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching an insulating film in the manufacture of a semiconductor device and a method for manufacturing a semiconductor device using the same. The present invention also relates to a method of etching an insulating film suitable for forming a dual damascene structure including a groove and a hole for forming conduction between wirings and layers by etching, and a method of manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high-speed operation of ULSIs, it has been a challenge to further increase the number of layers and the degree of integration. As the wiring width and the wiring interval required for improving the degree of integration are reduced, wiring capacitance and wiring resistance are increased, and the wiring delay (increase in time constant) due to these becomes a factor that hinders high-speed operation of the device. Is expected.

In order to reduce wiring delay, it is important to reduce wiring resistance and wiring capacitance. Regarding the reduction of wiring resistance, development of a dual damascene process using Cu as a wiring material (Cu dual damascene) is in progress. That is, in this dual damascene process, an insulating film is etched to form a pattern in which a wiring groove and an interlayer conduction hole (contact hole) are integrally formed, and a wiring material is filled in these grooves and holes. It is a method of embedding. In other words, it is called a dual damascene because it includes both a damascene process for forming a wiring by forming a groove in an insulating film and burying a conductor and a damascene process for forming a hole for interlayer conduction and then burying a conductor. .

On the other hand, since the wiring capacitance is proportional to the square root of the relative dielectric constant of the interlayer insulating film, to reduce the wiring capacitance, studies are being made on a low dielectric constant insulating film type. Examples of the low dielectric constant film include SiOF, inorganic hydrogen-containing SOG and organic SO.
There is G. These SOGs (Spin on Glass) are all S
An insulating coating film containing i and O as main components,
G further contains a C component.

The organic SOG mainly treated in the present invention is -O
It has a structure in which an organic group (mainly a methyl group CH ₃ ) is bonded to a side chain with respect to the main chain of —Si—O—. This kind of organic SOG
For example, a product having a relative dielectric constant ε = 2.8 is commercially available from Company H.

Conventional etching of an interlayer insulating film such as p-TEOS (an insulating film mainly composed of SiO _{2 formed} by plasma CVD using TEOS as a source gas: relative dielectric constant ε = 4.0), specifically, In oxide film etching such as formation of a contact hole, etching is performed mainly using an organic gas containing fluorine (CHF ₃ or C ₄ F ₈ ) as an etching gas.

In the case of a fine pattern, a process of adding a few ml / min of oxygen to such an organic etching gas containing fluorine has been constructed in order to ensure the removability of the pattern bottom. However, in most cases, the insulating film to be etched is a single type of SiO ₂ .

[0008] Also, as a literature on conventional etching of a low dielectric constant film, for example, a lecture in the electronic journal 16th Technical Symposium "Thorough verification of low-k / low dielectric constant interlayer insulating film-coating film vs. CVD film-" There are 59 pages of proceedings.
In this document, an organic polymer-based low dielectric constant film is taken up.

[0009]

As described above, in order to reduce the wiring delay, it is effective to employ a Cu dual damascene using a low-resistance Cu as a wiring material and using a low dielectric constant interlayer insulating film. However, when forming a dual damascene wiring, a Cu film or a CMP (Chemical Mechanical) is formed.
l There are many issues in the whole process such as uniformity of polishing. In this type of process, a wiring material such as Cu is buried in a groove or a hole of an insulating film, and then unnecessary wiring material formed on the insulating film by CMP is removed.

A shape suitable for embedding is also used in an etching (dual damascene etching) for forming a dual damascene structure having two damascene structures of a groove for embedding a wiring material and a hole for interlayer conduction for making contact with a lower wiring. There are issues such as processing and realization of high in-plane uniformity and high selectivity.

It is necessary to simultaneously perform the step of forming the groove for embedding the wiring material and the step of forming the hole for making contact with the lower-layer wiring or stepwise.

[0012] The etched area is largely different between the groove and the hole, the aspect ratio is largely different between the groove and the hole, and the presence or absence of an intermediate layer (for example, Si ₃ N ₄ ) as an etching stopper, the insulating property in the groove processing. Due to the fact that sub-trench (a deep groove is formed at the periphery of the etching bottom) or bowing (a barrel-shaped cross-sectional shape with an enlarged central portion) is likely to occur in the organic SOG forming the film.
It is very difficult to select etching conditions and the like.

[0013] In particular, organic SOG is an insulating film like an oxide film, but when the film composition changes, the etching characteristics change as soon as the film composition changes, and the optimum etching can be performed under conditions that are significantly different from the conventional oxide film etching process conditions. In many cases, it was possible.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems and to provide an insulating film having a low dielectric constant, in particular, a laminated structure composed of an organic SOG-based insulating film and SiO ₂ (for example, p-TEOS). In order to form a dual damascene structure by etching at a high etching rate with a good shape and, if there is an intermediate layer (for example, Si ₃ N ₄ ), a process capable of obtaining a high selectivity with the intermediate layer is established. To provide a method for etching an insulating film (dual damascene etching method) and a method for manufacturing a semiconductor device using the same.

[0015]

The above objects of the present invention can be achieved by a dual damascene etching method for an insulating film having the following two features (1) and (2).

(1) Using a UHF band ECR plasma etching apparatus of a flat antenna type, a dual insulating film having holes and grooves in an insulating layer having a first insulating film and a second insulating film via an intermediate insulating layer. An etching method for forming a damascene structure, wherein in the step of etching the first insulating film and the second insulating film, a ratio of an etching gas flow rate to an oxygen gas flow rate supplied to the plasma etching apparatus is 0.7 to 1.3.

(2) An etching method using a UHF band ECR plasma etching apparatus of a flat antenna type to form a dual damascene structure including holes and grooves in at least the first insulating layer without an intermediate insulating layer. The ratio of the etching gas flow rate to the oxygen gas flow rate supplied to the plasma etching apparatus is 1.0 to 1.3 in the groove etching step, 0.7 to 1.0 in the hole etching step, and The feature is that the flow rate ratio in the groove etching step is larger than that in the hole etching step.

In the case of having the intermediate insulating layer of the above (1),
The reason why the ratio of the etching gas flow rate to the oxygen gas flow rate supplied to the plasma etching apparatus is set to 0.7 to 1.3 will be described. This flow rate ratio directly affects the etching accuracy and the etching rate. If it is smaller than 0.7, side etching by oxygen becomes large and bowing (the center portion expands into a barrel shape) occurs, and the vertical etching wall surface is formed. Can not be obtained.

On the other hand, if it is larger than 1.3, the etching rate is sharply reduced, and even if the etching time is the same, a large difference in the etching depth occurs due to the size of the groove width and the hole diameter. The problem that the selection ratio becomes small occurs. For this reason, the ratio of the flow rate of the etching gas to the flow rate of the oxygen gas is set to 0.1.
7 to 1.3.

In the case of (1), since the intermediate insulating layer has a function as an etching stopper when etching the groove and has a function as a mask when etching the hole, the step of etching the groove and the hole is specified here. With the same gas flow rate ratio, there is a feature that processing can be performed continuously in one etching step.

The pressure of the gas in the etching chamber 101 is preferably 3 Pa or less, more preferably 0.75 to 3 Pa. If it is smaller than 0.75 Pa, bowing is likely to occur, and if it is larger than 3 Pa, the etching rate tends to decrease.

When the intermediate insulating layer is not provided in (2), the ratio of the flow rate of the etching gas to the flow rate of the oxygen gas supplied to the plasma etching apparatus is set to 1.0 to 1.3 in the etching step for forming the groove. The reason why the flow rate ratio in the etching step for forming a hole is set to 0.7 to 1.0 in the etching step for forming a hole and the etching step for forming a groove is larger than that in the etching step for forming a hole will be described.

Also in this case, the reasons for limiting the upper and lower limits of the flow rate ratio are the same as in the case of the above (1). However, in the case of (2), it is necessary to set the flow rate ratio in the groove etching step larger than that in the hole etching step. Then, in this case, unlike the case of (1), since there is no intermediate insulating layer, after forming a hole first,
A groove is formed over the hole. Since the etching rate is determined by the set etching conditions, the depth of the groove can be accurately controlled by controlling the etching time.

In this case, the pressure of the gas supplied to the plasma etching apparatus is desirably 3 Pa or less in the etching step for forming a groove and 1.5 Pa or less in the etching step for forming a hole.

This dual damascene etching method is
When applied to an etching process of an interlayer insulating film of a semiconductor device, a high-precision dual damascene structure can be obtained, so that a wiring structure that eliminates the problem of wiring delay can be easily realized, and an excellent method of manufacturing a semiconductor device is provided. can do.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The dual damascene etching method of the present invention can be performed using a flat antenna type UHF band ECR plasma etching apparatus. FIG. 1 schematically shows a configuration example of this plasma etching apparatus.

That is, FIG. 1 is a schematic sectional view of the apparatus. In this etching apparatus, an etching gas is introduced from a Si shower plate 103 on the surface of an upper antenna 102 into an evacuated etching chamber 101, and a frequency is supplied from the upper antenna 102. An electromagnetic wave in the UHF band of 300 to 1000 MHz is radiated and coupled with the magnetic field generated by the coil 104 to form ECR plasma.

For example, a uniform magnetic field region having a magnetic field strength of about 160 Gauss, which resonates at 450 MHz, is located in the space between the antenna and the lower electrode 105 at the center of the antenna.
A bowl-like shape that crosses the antenna around the periphery is most suitable.

The sample 106 is held on the lower electrode 105 by electrostatic attraction, and the sample temperature can be controlled at the lower electrode set temperature by performing heat exchange with, for example, He flow from the back surface. An RF bias of, for example, 800 kHz is applied to the lower electrode, ions in the plasma are drawn into the sample, and the insulating film is etched.

The antenna 102 has 13.56M.
Hz on the antenna surface by applying a radio frequency (RF) of
And the composition of the active species in the plasma can be changed.

An antenna 102 constituting a flat antenna type
The distance between the sample and the sample 106 is generally 50 to 90 mm, preferably 70 to 90 mm.

The supply path of the etching gas and the oxygen gas into the etching chamber 101 is supplied from the back surface of the disk-shaped antenna 102 provided with the gas passage holes, and is also provided on the Si shower plate provided with the gas passage holes. 103
, So as to be uniformly ejected into the etching chamber 101.

A semiconductor element is formed on a semiconductor substrate in advance, and an electrode is formed on the surface of the underlayer serving as the sample 106. The periphery of the electrode is covered with an insulating layer and flattened. use. A sample in which an interlayer insulating film is formed on this underlayer is used as a sample.

As an interlayer insulating film to be subjected to the dual damascene etching, an insulating film having a low dielectric constant is applied. At present, for example, at least a methyl group (CH ₃₎ is present on the side chain with respect to the main chain of —O—Si—O—. An organic SOG having the following formula (2) is a preferable example. However, the organic SOG having a relative dielectric constant of ≤2.8 is not limited to the organic SOG, and may be an inorganic SOG, for example, SiO ₂ , or Si ₃ N ₄ .

As an etching gas, a gas containing at least one element of carbon, fluorine and hydrogen is used.

The gas which can supply oxygen by dissociation in plasma, for example, C ₃ F ₆ O or C
₂ F ₆ O of such ether fluorine-containing compound and _C 2 F ₄
At least one of carbonyl fluorine-containing compounds such as O
Seed gas can be used.

Further, it is desirable that the etching gas and the oxygen gas or the gas substituted for the oxygen gas supplied to the plasma etching apparatus be diluted with Ar. This Ar dilution is related to the selectivity of the resist, and the flow rate is 200 ml / m2.
If in or more, the selection ratio becomes large, which is preferable.

The total flow rate of the gas used is 200 ml / min or more including the case where there is no Ar dilution.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <Example 1> (1) Schematic description of an apparatus used for dual damascene etching: This is performed using a flat antenna type UHF band ECR plasma etching apparatus shown in FIG. In this etching apparatus, an etching gas is introduced into a vacuum evacuated etching chamber 101 from a Si shower plate 103 on the surface of an upper antenna 102, and a frequency of 4
A 50 MHz UHF band electromagnetic wave is radiated, and the coil 104 is radiated.
And an ECR plasma is formed.

ECR resonance, magnetic field strength of about 160 Gau
The ss isomagnetic field region is located in the space between the antenna and the lower electrode 105 at the center of the antenna, and a bowl-shaped shape that crosses the antenna around the periphery is most preferable.

The sample 106 is held on the lower electrode 105 by electrostatic attraction, and heat exchange is performed by a He flow from the back surface to control the sample temperature at the lower electrode set temperature. An RF bias of 800 kHz is applied to the lower electrode, ions in the plasma are drawn into the sample, and the insulating film is etched.

The antenna 102 has 13.56 M
The apparatus has a configuration in which F is consumed on the antenna surface by applying a high frequency of Hz to change the composition of active species in the plasma.

(2) Outline of the etching process for forming a dual damascene structure: FIG. 2 shows a process flow for forming a dual damascene structure having an intermediate insulating layer. In this case, a self-alignment method in which a pattern for forming a hole is formed in advance on the intermediate insulating layer will be described.

First, as shown in FIG.
A 50 nm-thick Si ₃ N ₄ 202 film is formed on a flattened underlayer 201 made of a semiconductor substrate to be 6 (Chemic).
al Vapor Deposition). On top of that, thickness 4
An organic SOG 203 serving as a first insulating film is applied to a thickness of 50 nm, and a Si ₃ N ₄ 204 having a thickness of 50 nm is formed. A resist 205 having a thickness of 300 nm is formed thereon. It will be understood from the following description that this Si ₃ N ₄ 204 will be an intermediate insulating layer. A fine hole pattern 206 is formed on the resist 205 by a well-known photolithography process.

As shown in FIG. 2B, this resist 2
Using the mask 05 as a mask, first, Si ₃ N ₄
204 is etched to form a hole pattern 206a.

After the resist 205 is removed as shown in FIG. 2C, the thickness of the resist is again reduced to 45 as shown in FIG.
An organic SOG layer 207 serving as a second insulating film having a thickness of 0 nm and a p-TEOS layer (substantially SiO ₂ layer) 20 having a thickness of 50 nm
8 are formed.

As shown in FIG. 2E, a resist 209 having a thickness of 600 nm is formed on the p-TEOS layer 208. A groove pattern 210 is formed in the resist 209 and used as an etching mask.

Next, as shown in FIG. 2F, etching is performed to etch the p-TEOS layer 208 and the organic SOG layer 207 to form a groove pattern 210a. During the etching of the groove, the intermediate insulating layer Si ₃ N ₄ 204 serves as an etching stopper.

As described above, the etching is performed on the Si ₃ N ₄ 204
Then, as shown in FIG. 2 (g), the organic SOG 203 is etched using the intermediate insulating layer Si ₃ N ₄ 204 as a mask to form a hole 206b.

Next, as shown in FIG. 2 (h), Si ₃ N ₄
The resist 202 is etched to remove the resist, thereby forming a dual damascene structure including the groove 210a and the hole 206b, as shown in FIG.

(3) Features of the dual damascene etching step in the present embodiment: The etching process of the present invention includes the step of FIG. 2 (f) and the step of FIG.
Applied to the process. The etching performance required in these two steps is (1) that the selectivity to resist is high,
(2) The difference in etching rate between the p-TEOS 208 and the organic SOG 207 is small, (3) The selectivity of the intermediate insulating layer Si ₃ N ₄ 204 is high, and (4) No bowing or sub-trench occurs. The present invention satisfies the above etching performance.

In this embodiment, Ar, C ₄ F ₈ and O ₂ were used as the gas supplied to the etching apparatus shown in FIG. The flow rate is Ar 370 ml / min, C ₄ F ₈ 15 ml / mi.
n and O _{2 were} 15 ml / min, but the ratio of the O ₂ flow rate to the etching gas C ₄ F ₈ flow rate was centered on 1;
Within the range of 0.7 to 1.3, it can be appropriately adjusted while balancing the processing shape and the etching rate. Ar flow rate is also 20
It was adjusted appropriately at 0 ml / min or more.

The gas pressure in the etching chamber 101 is 0.7
The antenna 102 and the sample 1 were adjusted within the range of 5 to 3 Pa.
The interval between 06 was 70 mm.

The UHF frequency is 450 MHz and the power is 1200 W; the RF frequency of the lower electrode 105 is 800
kHz, power 1200 W; RF frequency supplied to the antenna 102 is 13.56 MHz, power 400
W, antenna temperature 30 ° C, lower electrode temperature -20 ° C
And

Under these conditions, the etching rates of the organic SOGs 203 and 207 and the p-TEOS 208 are 500 nm / min.
As described above, the selectivity with the intermediate insulating layer Si ₃ N ₄ (stopper layer) 204 was 10 to 15, and the selectivity with respect to the resist was 3 to 4.

The UHF power and the RF power can be appropriately adjusted as long as the etching rate can be maintained. Note that A
Increasing the flow rate of r or bringing the active species to a low-pressure region shortens the residence time of each active species, and tends to improve the releasability of the fine pattern.

According to this embodiment, an organic SO is used as an interlayer insulating film.
A dual damascene structure using G can be formed by etching grooves and holes at once.

In the step of FIG. 2, self-aligned batch etching was performed. However, in the step of FIG. 2B, the hole forming pattern 206 was not formed in the intermediate insulating layer Si ₃ N ₄ 204, and FIG. In (f), the second organic SOG 207 is once selectively etched by using the intermediate insulating layer Si ₃ N ₄ 204 as a stopper to form a groove 210a, and then,
A hole pattern 206a is formed on the intermediate insulating layer Si ₃ N ₄ 204.
Is formed, and using this as a mask, the first organic SOG 203 is formed.
Alternatively, two-step etching may be performed such that selective etching is performed to form the hole 206b.

Embodiment 2 A dual damascene structure is formed in basically the same steps as in Embodiment 1. In this embodiment, the intermediate insulating layer Si ₃ N ₄ 204 of Embodiment 1 is formed by p-TEOS.
It was replaced.

Ar, CHF ₃ and O ₂ were used as gases supplied to the etching apparatus of FIG. The flow rate is Ar1
00 ml / min, CHF ₃ 70 ml / min, O ₂ 20
ml / min. In this case, the etching gas CHF
The ratio of the O ₂ flow rate to the flow rate ₃ was 0.3, and the gas pressure in the etching chamber 101 was 4 Pa.

The etching rate is 400 to 500 nm / m
in, resist selectivity is at least 3, organic SOG and p
The result of the selectivity with -TEOS was at least 3. As in Example 1, a favorable dual damascene structure could be obtained without occurrence of bowing or subtrench.

In the present invention, for example, N ₂ can be used instead of O _{2. In} this embodiment, for example, the flow rate can be set to 200 ml / min.

In the case of the p-TEOS intermediate layer, there is a method in which a hole pattern is not formed in the intermediate layer in advance. In this case, a hole pattern 206 is formed on the outermost surface using a resist, and the p-TEOS 204 and the organic SOG 203 are collectively subjected to hole etching. Thereafter, the resist is removed, holes are buried with, for example, an anti-reflection film (organic film) or the like.
Is formed, and groove etching is performed using p-TEOS as a stopper. Thereafter, the dual damascene structure may be formed by removing the antireflection film and the resist. That is, in this case, a hole is formed first, and a groove is formed later.

<Embodiment 3> Next, FIG. 3 shows a process flow in the case of forming a dual damascene structure having no intermediate insulating layer differently from Embodiment 1.

(1) Outline of Dual Damascene Structure Formation: As shown in FIG. 3A, first, a 50 nm-thick Si ₃ N ₄ 302 film is formed on a flattened underlayer 301. An organic SOG layer 303 having a thickness of 800 nm and a p-TEOS 304 layer having a thickness of 50 nm are formed thereon. A resist 305 having a thickness of 700 nm is formed thereon. On the resist 305, a fine hole pattern 306 is formed.

Using this as a mask, as shown in FIG. 3B, first, the p-TEOS 304 and the organic SOG 303 are etched to form a hole 306a.

Next, as shown in FIG. 3C, after the resist 305 is removed, as shown in FIG.
A resist 307 having a thickness of 500 nm is formed. A fine groove pattern 308 is formed on the resist 307,
Used as an etching mask for forming grooves.

Next, as shown in FIG. 3E, the p-TEOS layer 304 and the organic SOG layer 303 are etched to form a groove 308a. In this etching step, since there is no intermediate insulating layer corresponding to the stopper 204 of the first embodiment, the etching time is controlled and the organic SOG layer 30 is controlled.
The groove formation is stopped at a substantially intermediate point of the thickness of 3. Here, the etching time was 30 seconds.

Next, as shown in FIG. 3F, after removing the resist 307, as shown in FIG.
The dual damascene structure is formed by etching the Si ₃ N ₄ 302 under conditions having a high selectivity with respect to the OS 304 and the organic SOG 303.

(2) Detailed description of the present embodiment: The etching process of the present embodiment is the same as the above-described step of FIG. 3B and FIG.
Applied to the process. The etching performance required in these two steps includes (1) a high selectivity to resist, (2) a small difference in etching rate between p-TEOS 304 and organic SOG 303, and (3) S etching in hole etching.
High selectivity of i ₃ N ₄ 302 (4) No bowing or sub-trench occurs, (5) Microetching is small in groove etching (etching depth is constant regardless of groove width) And high in-plane uniformity. This embodiment satisfies the above etching performance.

In this embodiment, Ar, C ₄ F ₈ ,
The O ₂ was used. In the case of the hole etching in the step of FIG. 3B, the flow rate is Ar 370 ml / min, C ₄ F ₈ 12 m
1 / min and O ₂ 18 ml / min.

The ratio of the flow rate of O _{2 to the} flow rate of the etching gas C ₄ F ₈ can be appropriately adjusted within a range of 0.7 to 1.0 while balancing the processing shape and the etching rate. Ar
The flow rate was appropriately adjusted at 200 ml / min or more.

The pressure was adjusted within the range of 0.75 to 1.5 Pa. In the case of the groove etching in the step of FIG. 3E, the flow rate is 370 ml / min for Ar and 15 ml / mi for C ₄ F _8.
n and O _{2 were} 15 ml / min, but the ratio of the O ₂ flow rate to the C ₄ F ₈ flow rate was appropriately adjusted within a range of 1.0 to 1.3 while balancing the processing shape and the etching rate. it can.

The flow rate of Ar was appropriately adjusted at 200 ml / min or more. The pressure was adjusted within the range of 1.5 to 3 Pa.

The distance between the antenna 102 and the sample 106 is 7
It was 0 mm. UHF frequency is 450MHz, power is 1200W; RF frequency of lower electrode is 800k
Hz, power is 1200W; RF supplied to antenna
The frequency is 13.56 MHz and the power of the electromagnetic wave is 400 W
The antenna temperature was set to 30 ° C. and the lower electrode temperature was set to −20 ° C.

Under these conditions, organic SOG 303 and p-TEOS3
04 has an etching rate of 500 nm / min or more and Si
₃ N ₄ selectivity between the stopper layer 10 above, selectivity to the resist is 3 or more. The UHF power and the RF power can be appropriately adjusted within a range where the etching rate can be maintained.

According to the present embodiment, a dual damascene structure using organic SOG can be formed by two-step etching of the hole 306a and the groove 308a.

In the flow of FIG. 3, the hole etching is performed in the step of FIG. 3 (a), and then the groove etching is performed in the step of FIG. 3 (e). Etching may be performed.

The gas used is C ₂ instead of O _2.
A gas such as O or C ₃ F ₆ O which supplies oxygen by dissociating in plasma may be used, or may be supplied together with O ₂ . However, in this case, it goes without saying that a suitable flow rate ratio with the etching gas changes. As the etching gas itself, a gas such as CHF ₃ or C ₅ F ₈ can be appropriately used.

<Embodiment 4> As shown in FIG. 4A, a semiconductor element (not shown) is previously formed on a semiconductor substrate in a base layer 201 serving as the sample 106 of Embodiment 1, and An electrode 400 is formed on the surface, and the periphery of the electrode is covered with an insulating layer 401 and flattened.
A sample in which an interlayer insulating film is formed on this underlayer is used as a sample.

A groove 210a and a hole 206b were integrally formed on the sample 106 by the dual damascene etching method of the first embodiment.

Next, as shown in FIG. 4B, a wiring circuit was formed by embedding Cu as the conductor layer 402 in the groove 210a and the hole 206b to manufacture a semiconductor device.

[0083]

As described in detail above, according to the present invention, a dual damascene structure using a low dielectric constant organic SOG film can be easily formed. Thus, it is possible to easily manufacture a semiconductor device having a highly reliable high-density wiring structure.

[Brief description of the drawings]

FIG. 1 shows a flat antenna type UH used in an embodiment of the present invention.
FIG. 1 is a schematic diagram of an F-band ECR plasma etching apparatus.

FIG. 2 is an etching process diagram for forming a dual damascene structure when an insulating layer has an intermediate insulating layer according to one embodiment of the present invention.

FIG. 3 is an etching process diagram for forming a dual damascene structure in the case where the insulating layer according to one embodiment of the present invention has no intermediate insulating layer.

FIG. 4 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

101: etching chamber, 102: antenna, 103: Si shower plate, 104: coil, 105: lower electrode, 106:
Sample, 201: Underlayer, 202:
Si ₃ N ₄ , 203 ... organic SOG, 20
_{4 ... Si 3 N 4, 205} ... resist,
206: hole pattern, 207: organic SOG,
208: Si ₃ N ₄ , 209: resist,
210: groove pattern, 210a: groove,
206 b ... hole, 301 ... base _{layer, 302 ... Si 3 N 4,} 303 ...
Organic SOG, 304 ... Si ₃ N ₄ , 30
5 ... resist, 306 ... hole pattern, 307 ... resist, 308 ...
Groove pattern, 306a ... hole, 3
08a ... groove.

Continuing from the front page (72) Inventor Kazunori Tsujimoto 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 4M104 CC01 DD08 DD16 DD20 EE18 HH14 5F004 BA14 BA20 BB11 BB13 BB18 BB22 BB23 BB25 BB26 BB28 CA02 CA06 DA00 DA23 DA26 DB03 DB07 DB24 EA07 EA15 EA23 EA33 EB02 5F033 MM02 QQ15 QQ25 QQ28 QQ30 QQ37 RR04 RR06 RR09 RR25 SS04 SS11 SS21 TT04 WW05 WW06 XX03

Claims (11)

[Claims] 1. A dual damascene comprising holes and grooves in an insulating layer having a first insulating film and a second insulating film via an intermediate insulating layer, using a flat antenna type UHF band ECR plasma etching apparatus. An etching method for forming a structure, wherein in the step of etching the first insulating film and the second insulating film, a ratio of an etching gas flow rate to an oxygen gas flow rate supplied to the plasma etching apparatus is 0.7 to 1; .3, wherein a groove is formed in the second insulating film using the intermediate insulating layer as an etching stopper, and then a hole is formed in the first insulating film using the intermediate insulating layer as a mask. Etching method. 2. The method according to claim 1, wherein a UHF band ECR plasma etching apparatus of a flat antenna type is used.
An etching method for forming a dual damascene structure including holes and grooves in the insulating layer, wherein the ratio of the etching gas flow rate to the oxygen gas flow rate supplied to the plasma etching apparatus is set to 1.
0 to 1.3, 0.7 in the hole etching step
A dual damascene etching method, wherein the flow rate ratio in the groove etching step is larger than that in the hole etching step. 3. The dual damascene etching method according to claim 1, wherein a gas containing at least one element of carbon, fluorine and hydrogen is used as an etching gas supplied to said plasma etching apparatus. 4. A gas comprising at least one of an ether-based fluorinated compound and a carbonyl-based fluorinated compound capable of supplying oxygen by dissociation in plasma is used as a gas replacing the oxygen gas supplied to the plasma etching apparatus. 3. The dual damascene etching method according to claim 1, wherein: 5. The dual damascene etching method according to claim 1, wherein an etching gas supplied to the plasma etching apparatus and an oxygen gas or a gas substituted for the oxygen gas are diluted with Ar. 6. The method according to claim 1, wherein the pressure of the gas supplied to the plasma etching apparatus is 3 Pa or less.
The described dual damascene etching method. 7. The pressure of a gas supplied to the plasma etching apparatus is set to 3 in the etching step for forming a groove.
3. The dual damascene etching method according to claim 2, wherein the pressure is set to be equal to or less than Pa and the etching step for forming the holes is set to be equal to or less than 1.5 Pa. 8. An insulating layer having said first insulating film and a second insulating film with an intermediate insulating layer interposed therebetween is formed of Si ₃ N ₄ or Si ₃ N _4.
2. The dual damascene etching method according to claim 1, wherein a laminated structure of an intermediate insulating layer made of O ₂ and first and second insulating films made of organic SOG is used. 9. The method according to claim 1, wherein the dual damascene structure is an organic SOG.
The first insulating layer and dual damascene etching method according to claim 2, characterized in that is constituted by a laminated structure of SiO ₂ formed thereon composed of. 10. The organic SOG is a low-permittivity organic SOG having at least a methyl group in a side chain and a relative dielectric constant of 2.8 or less with respect to the main chain of —O—Si—O—. 10. The dual damascene etching method according to claim 8, wherein: 11. A step of forming an interlayer insulating film on a semiconductor substrate on which a semiconductor element is formed and an electrode is exposed on the surface, and forming a wiring groove and a contact hole in said interlayer insulating film by a dual damascene etching method. 11. A method for manufacturing a semiconductor device, comprising: forming a wiring structure; and embedding a conductive layer in the wiring groove and the contact hole to form a wiring structure, wherein the dual damascene etching method is performed. A method for manufacturing a semiconductor device, comprising the dual damascene etching method according to any one of the above.