JP2001102410A - Mounting structure for semiconductor device - Google Patents
Mounting structure for semiconductor deviceInfo
- Publication number
- JP2001102410A JP2001102410A JP27487299A JP27487299A JP2001102410A JP 2001102410 A JP2001102410 A JP 2001102410A JP 27487299 A JP27487299 A JP 27487299A JP 27487299 A JP27487299 A JP 27487299A JP 2001102410 A JP2001102410 A JP 2001102410A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- anisotropic conductive
- conductive film
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置を異方
性導電膜を用い基板に実装する半導体装置の実装構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure for mounting a semiconductor device on a substrate using an anisotropic conductive film.
【０００２】[0002]
【従来の技術】従来からの公知の技術として、半導体装
置の電極上に設けられた突起状の電極であるバンプと、
基板上に配置されたパターンとを電気機械的に接続する
構造として、異方性導電膜を利用する構造が知られてい
る。この実装構造の従来技術を実装工程順に図５を用い
て説明する。2. Description of the Related Art As a conventionally known technique, a bump which is a protruding electrode provided on an electrode of a semiconductor device,
As a structure for electromechanically connecting a pattern arranged on a substrate, a structure using an anisotropic conductive film is known. The prior art of this mounting structure will be described with reference to FIG.
【０００３】図５は、従来技術を示す断面図である。図
５（ａ）において半導体装置であるところのベアチップ
ＩＣ１が実装される基板２の部品実装面３には複数の配
線パターン４が導電材料にて形成されており、各配線パ
ターン４の先端の表面には金メッキがなさた電極５が形
成されている。また、各配線パターン４には、電極５の
部分を除いてソルダーレジスト６で覆われている。FIG. 5 is a sectional view showing the prior art. In FIG. 5A, a plurality of wiring patterns 4 are formed of a conductive material on a component mounting surface 3 of a substrate 2 on which a bare chip IC 1, which is a semiconductor device, is mounted. Is formed with a gold-plated electrode 5. Each wiring pattern 4 is covered with a solder resist 6 except for a part of the electrode 5.
【０００４】ベアチップＩＣ1は、所定の面７にアルミ
等の導電材料で形成された複数の電極が基板の電極に対
応させて配置され、各電極の表面にはバンプ８が形成さ
れている。バンプ８はＡｕ又はＳｎ−Ｐｂ合金等の金属
材料で形成されている。The bare chip IC1 has a plurality of electrodes formed of a conductive material such as aluminum on a predetermined surface 7 corresponding to the electrodes of a substrate, and bumps 8 are formed on the surface of each electrode. The bump 8 is formed of a metal material such as Au or a Sn-Pb alloy.
【０００５】図５（ｂ）は、異方性導電膜を仮圧着する
工程の断面図を示す。ベアチップＩＣ1の実装のために
用いられる異方性導電膜２０は絶縁性樹脂２１に導電粒
子２２を分散させて形成されている。この異方性導電膜
２０はベアチップＩＣ1の所定の面７の幅よりも大きな
幅を有するテープ状に形成され、保護用テープで覆われ
た状態でリールに巻かれている。FIG. 5B is a sectional view showing a step of temporarily compressing the anisotropic conductive film. The anisotropic conductive film 20 used for mounting the bare chip IC1 is formed by dispersing conductive particles 22 in an insulating resin 21. This anisotropic conductive film 20 is formed in a tape shape having a width larger than the width of the predetermined surface 7 of the bare chip IC1, and is wound around a reel while being covered with a protective tape.
【０００６】ベアチップＩＣ1の実装に際しては、まず
リールに巻かれた異方性導電膜２０を保護用テープ２３
と共に必要な長さに切断し、基板２の部品実装面３に載
せる。次に異方性導電膜２０を保護用テープ２３側から
加熱、加圧ツール２４で加熱（８０度Ｃ、２秒程度）、
加圧して異方性導電膜２０の仮圧着を行う。この場合
に、異方性導電膜２０は基板２の配線パターン４や電極
５を覆うようにしてベアチップＩＣ1実装箇所に接着さ
れるが、基板２に対する異方性導電膜２０の位置ズレ等
を考慮し、異方性導電膜２０の面積はベアチップＩＣ1
の所定の面７の面積より大きめにするのが望ましい。ま
た、異方性導電膜２０の厚みは、バンプ８の高さより１
０μｍ程度厚いものを用いるのが望ましい。In mounting the bare chip IC1, first, the anisotropic conductive film 20 wound on a reel is
At the same time, it is cut to a required length and mounted on the component mounting surface 3 of the substrate 2. Next, the anisotropic conductive film 20 is heated from the protective tape 23 side, and heated by the pressing tool 24 (80 ° C., about 2 seconds),
The anisotropic conductive film 20 is temporarily pressed by applying pressure. In this case, the anisotropic conductive film 20 is adhered to the mounting position of the bare chip IC 1 so as to cover the wiring patterns 4 and the electrodes 5 of the substrate 2. The area of the anisotropic conductive film 20 is the bare chip IC1.
It is desirable that the area be larger than the area of the predetermined surface 7. In addition, the thickness of the anisotropic conductive film 20 is one more than the height of the bump 8.
It is desirable to use one having a thickness of about 0 μm.
【０００７】次に、図５（ｃ）は半導体装置を実装して
いる断面図を示す。基板２に接着された異方性導電膜２
０の保護用テープ２３を剥がし、ベアチップＩＣ1の所
定の面７が異方性導電膜２０に向くように設定して異方
性導電膜２０上にベアＩＣチップ１を載せ、ベアチップ
ＩＣ1を介し異方性導電膜２０を加圧（１８０度Ｃ、２
０秒程度）、加熱してベアチップＩＣ1の実装を行う。
加熱することにより、異方性導電膜２０の絶縁性樹脂２
１が軟化し、加圧することにより押し広げられ、ベアチ
ップＩＣ1の所定の面７と基板２の部品実装面３の間を
充填する。また、余った絶縁性樹脂２１は、矢印ａ方向
に押し出され、ベアチップＩＣ1の側面を充填し保護す
る。この状態を図５（ｄ）に示す。Next, FIG. 5C shows a cross-sectional view in which the semiconductor device is mounted. Anisotropic conductive film 2 bonded to substrate 2
The bare IC chip 1 is placed on the anisotropic conductive film 20 by setting the predetermined surface 7 of the bare chip IC1 so as to face the anisotropic conductive film 20, and removing the protective tape 23 via the bare chip IC1. The anisotropic conductive film 20 is pressurized (180 ° C., 2
(Approximately 0 seconds), and the bare chip IC1 is mounted by heating.
By heating, the insulating resin 2 of the anisotropic conductive film 20 is formed.
1 is softened and expanded by applying pressure to fill the space between the predetermined surface 7 of the bare chip IC 1 and the component mounting surface 3 of the substrate 2. The surplus insulating resin 21 is extruded in the direction of arrow a to fill and protect the side surface of the bare chip IC1. This state is shown in FIG.
【０００８】これで、基板２の部品実装面３とベアチッ
プＩＣ1の所定の面７とは異方性導電膜２０の絶縁性樹
脂２１を介して接合される。また、異方性導電膜２０に
混在する導電粒子２２はバンプ８により基板２の電極５
に押圧されるので基板２とベアチップＩＣ1とは電気的
にも接続される。[0008] Thus, the component mounting surface 3 of the substrate 2 and the predetermined surface 7 of the bare chip IC 1 are joined via the insulating resin 21 of the anisotropic conductive film 20. In addition, the conductive particles 22 mixed in the anisotropic conductive film 20 are bumped by the bumps 8 so that
The substrate 2 and the bare chip IC1 are also electrically connected.
【０００９】[0009]
【発明が解決しようとする課題】電子機器の多機能化に
伴い、複数の半導体装置を１枚の基板に高密度に実装す
る、マルチチップモジュールが多く用いられているが、
下記欠点を有していた。With the increase in the functions of electronic devices, multi-chip modules for mounting a plurality of semiconductor devices on a single substrate at a high density have been widely used.
It had the following disadvantages.
【００１０】複数の半導体装置を１枚の基板に実装する
場合、それぞれの半導体装置の実装される部分に異方性
導電膜を半導体装置の数だけ貼りつけなくてはならず、
生産性が著しく悪くなっていた。また、生産設備も複雑
で大掛かりなものが必要となっていた。When a plurality of semiconductor devices are mounted on a single substrate, anisotropic conductive films must be attached to portions where the respective semiconductor devices are mounted, by the number of semiconductor devices.
Productivity was significantly worse. Also, the production equipment required complicated and large-scale equipment.
【００１１】一方、簡略化の為に、異方性導電膜を各半
導体装置の実装部分に、それぞれ貼るのではなく、一括
して異方性導電膜を貼る構造もある。この場合、複数の
半導体装置の間隔が充分に離れていれば問題はないが、
コンパクト化、高密度化が要求される場合は、前記半導
体装置を隣接して配置せざるをえない。On the other hand, for the sake of simplicity, there is also a structure in which an anisotropic conductive film is collectively attached to a mounting portion of each semiconductor device, instead of being attached to each mounting portion of each semiconductor device. In this case, there is no problem if a plurality of semiconductor devices are sufficiently separated from each other.
When compactness and high density are required, the semiconductor devices must be arranged adjacent to each other.
【００１２】この場合、まず一方の半導体装置を加熱・
加圧して実装する。この時、実装時の熱が基板や基板表
面に配置した配線パターンを伝導し、他方の半導体装置
をこれから実装する部分に既に仮圧着されている異方性
導電膜を構成する絶縁性樹脂の熱硬化を進めてしまい、
他方の半導体装置を実装する際に、加熱・加圧しても絶
縁性樹脂が充分軟化せず、基板と半導体装置の保持が不
十分となり、バンプと基板の電極との電気的導通が確保
できなくなるという、電子機器としては致命的な欠陥と
なるという問題がある。In this case, first, one semiconductor device is heated and
Press and mount. At this time, heat at the time of mounting conducts through the substrate and the wiring pattern arranged on the surface of the substrate, and heat of the insulating resin constituting the anisotropic conductive film that has been temporarily crimped to a portion where the other semiconductor device is to be mounted. Hardening,
When mounting the other semiconductor device, the insulating resin does not sufficiently soften even when heated and pressed, and the holding of the substrate and the semiconductor device becomes insufficient, and electrical conduction between the bump and the electrode of the substrate cannot be secured. That is, there is a problem that a fatal defect occurs as an electronic device.
【００１３】そこで、一方の半導体装置を実装する際の
加熱・加圧により絶縁性樹脂の熱硬化が進まない距離ま
でそれぞれの半導体装置を離さなくてはならず、高密度
実装化の大きな妨げになっていた。Therefore, each semiconductor device must be separated by a distance such that heat hardening of the insulating resin does not proceed by heating and pressing when mounting one of the semiconductor devices, which greatly hinders high-density mounting. Had become.
【００１４】もちろん、複数の半導体装置ごとに異方性
導電膜を個別に貼りつける方法もある。つまり、まず一
方の半導体装置を実装するための異方性導電膜を貼りつ
けた後、半導体装置を実装する。その後、他方の半導体
装置を実装するための異方性導電膜を貼りつけ他方の半
導体装置を実装する。この場合は、全く熱硬化の心配は
ないが、同一工程を繰り返すことになり、生産性が著し
く損なわれることが容易に考えられる。Of course, there is also a method of individually attaching an anisotropic conductive film to each of a plurality of semiconductor devices. That is, an anisotropic conductive film for mounting one semiconductor device is first attached, and then the semiconductor device is mounted. After that, an anisotropic conductive film for mounting the other semiconductor device is attached, and the other semiconductor device is mounted. In this case, there is no concern about heat curing, but the same process is repeated, and it is easily considered that productivity is significantly impaired.
【００１５】つまり、異方性導電膜を一括して貼りつ
け、しかも複数の半導体装置を短間隔で配置できる実装
構造が求められている。That is, there is a demand for a mounting structure in which anisotropic conductive films can be attached together and a plurality of semiconductor devices can be arranged at short intervals.
【００１６】[0016]
【課題を解決するための手段】以上のような問題を解決
するために、本発明の半導体装置の実装構造では、複数
の半導体装置の間の基板にスリットを設けたことを特徴
とする。In order to solve the above problems, a semiconductor device mounting structure according to the present invention is characterized in that a slit is provided in a substrate between a plurality of semiconductor devices.
【００１７】[0017]
【発明の実施の形態】（１）第一実施形態 以下図面により本発明の実施形態を詳述する。図１は本
発明の複数の半導体装置を１枚の基板に高密度に実装す
る、マルチチップモジュールの図面を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a drawing of a multichip module in which a plurality of semiconductor devices of the present invention are mounted on a single substrate at a high density.
【００１８】図１（ａ）は、基板に異方性導電膜が仮圧
着され、一方の半導体装置を実装する直前の状態を示す
断面図である。FIG. 1A is a cross-sectional view showing a state in which an anisotropic conductive film is temporarily pressed on a substrate and immediately before one semiconductor device is mounted.
【００１９】図１（ｂ）は、異方性胴電膜を除いた状態
の、図１（ａ）の平面図である。FIG. 1B is a plan view of FIG. 1A with the anisotropic conductive film removed.
【００２０】図１（ｃ）は、一方の半導体装置を実装し
た状態を示す断面図である。FIG. 1C is a sectional view showing a state where one semiconductor device is mounted.
【００２１】図１（ｄ）は、他方の半導体装置も実装し
た状態を示す断面図である。FIG. 1D is a sectional view showing a state where the other semiconductor device is also mounted.
【００２２】図１（ａ）において、基板２の部品実装面
３上に、異方性導電膜２０が仮圧着され、保護用テープ
は既にはがされている状態を示す。２５及び２７は半導
体装置を示す。ここで、図中のｈ１，ｈ２は各々の半導
体装置のパンプ高さを示している。異方性導電膜２０の
厚みは、ベアチップＩＣ２５の所定の面２６と基板２の
部品実装面３との間の充填性を考慮し、バンプ高さｈ１
より１０μｍ程度厚いものを用いる。２９は、ベアチッ
プＩＣ２５とベアチップＩＣ２７の間の設けられた、基
板のスリット部を示す。FIG. 1A shows a state in which an anisotropic conductive film 20 has been temporarily pressed on the component mounting surface 3 of the substrate 2 and the protective tape has already been removed. Reference numerals 25 and 27 denote semiconductor devices. Here, h1 and h2 in the figure indicate the pump height of each semiconductor device. The thickness of the anisotropic conductive film 20 is determined in consideration of the filling property between the predetermined surface 26 of the bare chip IC 25 and the component mounting surface 3 of the substrate 2 and the bump height h1.
A layer about 10 μm thicker is used. Reference numeral 29 denotes a slit portion of the substrate provided between the bare chip IC 25 and the bare chip IC 27.
【００２３】まず、図１（ａ）において、ベアチップＩ
Ｃ２５を加熱・加圧して異方性導電膜を介し実装する。
図１（ｂ）はベアチップＩＣ２５が実装される直前の状
態を示す平面図である。本図では、基板２に設けたスリ
ット部２９が分かり易いよう、異方性導電膜２０を除い
た状態の平面図である。図１（ｃ）において、加熱・加
圧ツール２４がベアチップＩＣ２５を実装することによ
り実装時の熱が異方性導電膜２０、配線パターン４、基
板２を介し矢印ａ，矢印ｂ方向に伝導する。しかし、も
っとも熱容量が大きな基板２にスリット２９が設けられ
ているため、熱の大部分は矢印ａ方向に伝わり、ベアチ
ップＩＣ２７が実装される部分の異方性導電膜に熱は伝
導せず、熱硬化は進まない。First, in FIG.
C25 is heated and pressurized and mounted via an anisotropic conductive film.
FIG. 1B is a plan view showing a state immediately before the bare chip IC 25 is mounted. FIG. 3 is a plan view showing a state in which the anisotropic conductive film 20 is removed so that the slit portion 29 provided in the substrate 2 can be easily understood. In FIG. 1C, when the heating / pressing tool 24 mounts the bare chip IC 25, heat at the time of mounting is conducted in the directions of the arrows a and b through the anisotropic conductive film 20, the wiring pattern 4 and the substrate 2. . However, since the slit 29 is provided in the substrate 2 having the largest heat capacity, most of the heat is transmitted in the direction of arrow a, and the heat is not conducted to the anisotropic conductive film in the portion where the bare chip IC 27 is mounted. Curing does not proceed.
【００２４】つまり、ベアチップＩＣ２５とベアチップ
ＩＣ２７の間の基板２にスリット２９を設けることによ
り、ベアチップＩＣ間隔を短くでき、より高密度な実装
が可能な構造を実現できる。That is, by providing the slit 29 in the substrate 2 between the bare chip IC 25 and the bare chip IC 27, the interval between the bare chip ICs can be shortened, and a structure capable of higher density mounting can be realized.
【００２５】本実施形態では、一枚の基板に二個の半導
体装置が実装される例を述べたが、更に多くの半導体装
置が実装される場合では、より多くの効果が得られるの
は言うまでもない。In this embodiment, an example in which two semiconductor devices are mounted on one substrate has been described. However, when more semiconductor devices are mounted, it goes without saying that more effects can be obtained. No.
【００２６】(2)第二実施形態 本実施形態は、第一実施形態の変形例である。本変形例
は、複数の半導体装置の間の基板に設けるスリットを、
基板表面と裏面に配置された配線パターンの電気的導通
を確保する為のスルーホールで代用したことを特徴とす
る。(2) Second Embodiment This embodiment is a modification of the first embodiment. In this modification, a slit provided on a substrate between a plurality of semiconductor devices is provided.
It is characterized in that through holes for ensuring electrical continuity between the wiring patterns arranged on the front surface and the back surface of the substrate are substituted.
【００２７】図２は、基板２のベアチップＩＣ２５とベ
アチップＩＣ２７が実装される部分の間に、基板２の表
面の配線パターンと裏面の配線パターンの電気的導通を
行うための、スルーホール３１がほぼ直線状に設けられ
ている様子を示す平面図である。本実施形態は第一実施
形態に比較するとベアチップＩＣ２５の実装時の熱は多
く伝わるものの、前記スルーホール３１の間に配線パタ
ーン４を配置でき、基板設計の自由度が大きくなる。FIG. 2 shows that a through hole 31 for electrically connecting the wiring pattern on the front surface and the wiring pattern on the rear surface of the substrate 2 is formed between the bare chip IC 25 and the bare chip IC 27 of the substrate 2. It is a top view showing signs that it is provided in the shape of a straight line. In this embodiment, compared to the first embodiment, although more heat is transferred during mounting of the bare chip IC 25, the wiring pattern 4 can be arranged between the through holes 31, and the degree of freedom in board design is increased.
【００２８】(3)第三実施形態 本実施形態は、第二実施形態の変形例である。本実施形
態では、基板２のベアチップＩＣ２５とベアチップＩＣ
２７が実装される部分の間に、設けられたスルーホール
３１の内部を熱伝導の低い物質で充填させた例である。(3) Third Embodiment This embodiment is a modification of the second embodiment. In this embodiment, the bare chip IC 25 and the bare chip IC
This is an example in which the inside of the provided through hole 31 is filled with a material having low thermal conductivity between the portions where the semiconductor device 27 is mounted.
【００２９】図３は、本実施形態を示す断面図である。FIG. 3 is a sectional view showing the present embodiment.
【００３０】前記スルーホール３１内には、基板２の材
質である例えばガラスエポキシの熱伝導率に対し熱伝導
率が低い炭素３２を充填している。このことにより、ベ
アチップＩＣ２５実装時の熱は、ベアチップＩＣ２７の
実装する部分の異方性導電膜への熱伝導は大幅に削減さ
れ、安定した実装品質を得ることができる。The through holes 31 are filled with carbon 32 having a lower thermal conductivity than the thermal conductivity of the material of the substrate 2, for example, glass epoxy. As a result, the heat at the time of mounting the bare chip IC 25, the heat conduction to the anisotropic conductive film in the portion where the bare chip IC 27 is mounted is greatly reduced, and stable mounting quality can be obtained.
【００３１】(4)第四実施形態 本実施形態は、第一実施形態の変形例である。本実施形
態では、基板２のベアチップＩＣ２５とベアチップＩＣ
２７が実装される部分の間のスリットを基板に設けるの
ではなく、異方性導電膜２０に設けたことを特徴として
いる。(4) Fourth Embodiment This embodiment is a modification of the first embodiment. In this embodiment, the bare chip IC 25 and the bare chip IC
The slit is provided in the anisotropic conductive film 20 instead of providing the slit between the parts where the 27 is mounted on the substrate.
【００３２】図面４（ａ）は、本実施形態の断面図を示
し、図面４（ｂ）は平面図を示す。FIG. 4A is a sectional view of the present embodiment, and FIG. 4B is a plan view.
【００３３】図面４（ｂ）において、３０は異方性導電
膜２０に設けられたスリット部を示す。図面４（ａ）に
おいて、スリット部３０の直下の基板２には、何もスリ
ットや穴を設けていないため、配線パターン４を自由に
配置でき、設計上の配線自由度を全く損なわずに、熱伝
導を防止することができる。In FIG. 4B, reference numeral 30 denotes a slit provided in the anisotropic conductive film 20. In FIG. 4 (a), since no slits or holes are provided on the substrate 2 immediately below the slit portion 30, the wiring pattern 4 can be arranged freely, without impairing the degree of freedom of wiring in design at all. Heat conduction can be prevented.
【００３４】[0034]
【発明の効果】請求項１記載の発明によれば、複数のベ
アチップＩＣを一枚の基板に実装するいわゆるマルチチ
ップモジュールの場合、一方のベアチップＩＣを実装す
る際の熱が基板を伝わり、他方のベアチップＩＣを実装
する為にあらかじめ貼られている異方性導電膜に伝わ
り、熱硬化を進めてしまい、安定した実装品質を得られ
なくなってしまう。According to the first aspect of the present invention, in the case of a so-called multi-chip module in which a plurality of bare chip ICs are mounted on a single substrate, heat when one of the bare chip ICs is mounted is transmitted to the substrate and the other is mounted on the other. This is transmitted to the anisotropic conductive film that has been pasted in order to mount the bare chip IC, and heat curing proceeds, so that stable mounting quality cannot be obtained.
【００３５】一方のベアチップＩＣと他方のベアチップ
ＩＣの間の基板の部分にスリットを設けることにより、
熱硬化を防ぎ複数のベアチップＩＣを近接して配置する
ことが可能となり、小型でコンパクトな実装構造を得る
ことができる。By providing a slit in the portion of the substrate between one bare chip IC and the other bare chip IC,
A plurality of bare chip ICs can be arranged close to each other while preventing heat curing, and a small and compact mounting structure can be obtained.
【００３６】請求項２記載の発明によれば、一方のベア
チップＩＣと他方のベアチップＩＣの間の基板の部分に
スルーホールを配置することにより、一方のベアチップ
ＩＣを実装する際の熱が基板を伝わり、他方のベアチッ
プＩＣを実装する為にあらかじめ貼られている異方性導
電膜に伝わり、熱硬化を進めることを防ぐと同時に、各
スルーホール間に配線パターンを配置でき、より配線設
計の自由度をも向上させた実装構造が実現できる。According to the second aspect of the present invention, by disposing the through holes in the portion of the substrate between the one bare chip IC and the other bare chip IC, the heat generated when the one bare chip IC is mounted can transfer the heat to the substrate. It is transmitted to the anisotropic conductive film that has been pasted to mount the other bare chip IC, preventing heat curing, and at the same time, allowing a wiring pattern to be placed between each through hole, allowing more freedom in wiring design. A mounting structure with an improved degree can be realized.
【００３７】請求項３記載の発明によれば、熱伝導を防
ぐ為に配置されたスルーホールの内部に熱伝導の低い物
質を充填させることにより、さらに熱伝導を下げること
が可能となり、より複数のベアチップＩＣを近接して配
置が可能となる。According to the third aspect of the present invention, the heat conduction can be further reduced by filling the inside of the through hole arranged to prevent heat conduction with a substance having low heat conduction. Can be arranged close to each other.
【００３８】請求項４記載の発明によれば、一括して貼
りつけられた異方性導電膜の、複数のベアチップＩＣを
実装する間の部分の前記異方性導電膜にスリットを設け
ることにより、熱硬化を防ぎ、基板には何もスリットや
スルーホールを配置しないため、配線自由度が最も高く
することが可能となる。According to the fourth aspect of the present invention, the slit is provided in a portion of the anisotropic conductive film which is collectively attached to the portion between the mounting of a plurality of bare chip ICs. In addition, since heat curing is prevented and no slits or through holes are arranged on the substrate, the degree of freedom in wiring can be maximized.
【図１】本発明の第一実施形態を示す実装構造の断面図
を示す。FIG. 1 is a sectional view of a mounting structure showing a first embodiment of the present invention.
【図２】本発明の第二実施形態を示す実装構造の平面図
を示す。FIG. 2 is a plan view of a mounting structure according to a second embodiment of the present invention.
【図３】本発明の第三実施形態を示す実装構造の断面図
を示す。FIG. 3 is a sectional view of a mounting structure showing a third embodiment of the present invention.
【図４】本発明の第四実施形態を示す実装構造の図面を
示す。FIG. 4 is a drawing of a mounting structure showing a fourth embodiment of the present invention.
【図５】本発明の従来例を示す実装構造を示す。FIG. 5 shows a mounting structure showing a conventional example of the present invention.
１、２５，２７…ベアチップＩＣ ２…基板 ３…部品実装面 ４…配線パターン ５…電極 ６…ソルダーレジスト ７、２６、２８…所定の面 ８…バンプ ２０…異方性導電膜 ２１…絶縁性樹脂 ２２…導電粒子 ２３…保護用テープ ２４…加熱、加圧ツール ２９…基板のスリット部 ３０…異方性導電膜のスリット部 ３１…スルーホール ３２…炭素 1, 25, 27 ... bare chip IC 2 ... substrate 3 ... component mounting surface 4 ... wiring pattern 5 ... electrode 6 ... solder resist 7, 26, 28 ... predetermined surface 8 ... bump 20 ... anisotropic conductive film 21 ... insulating property Resin 22 ... Conductive particles 23 ... Protective tape 24 ... Heating and pressing tool 29 ... Slit part of substrate 30 ... Slit part of anisotropic conductive film 31 ... Through hole 32 ... Carbon
Claims (5)
方性導電膜を介在させた状態で、半導体装置の所定の面
を基板の部品実装面に加熱下で圧着することにより、前
記半導体装置の所定の面と前記基板の部品実装面とを前
記絶縁性樹脂で接合すると共に、前記半導体装置の所定
の面に形成されたバンプと、このバンプに対向する前記
基板の部品実装面に形成の電極とを、前記導電粒子を介
して電気的に接続する半導体装置の実装構造において、 複数の半導体装置を実装するために、異方性導電膜を一
括して基板の部品実装面に貼りつけ、 複数の半導体装置の間の基板にスリットを設けたことを
特徴とする、半導体装置の実装構造。In a state in which an anisotropic conductive film in which conductive particles are dispersed in an insulating resin is interposed, a predetermined surface of a semiconductor device is pressure-bonded to a component mounting surface of a substrate under heating to thereby form the semiconductor device. A predetermined surface of the semiconductor device and a component mounting surface of the substrate are joined with the insulating resin, and a bump formed on the predetermined surface of the semiconductor device and a component mounting surface of the substrate facing the bump are provided. In a semiconductor device mounting structure in which electrodes for formation are electrically connected via the conductive particles, an anisotropic conductive film is collectively attached to the component mounting surface of the substrate in order to mount a plurality of semiconductor devices. A mounting structure of a semiconductor device, wherein a slit is provided in a substrate between a plurality of semiconductor devices.
間の基板に、基板表面の配線パターンと裏面の配線パタ
ーンとの電気的導通を行うための、スルーホールをほぼ
直線状に設けたことを特徴とする半導体装置の実装構
造。2. A through-hole according to claim 1, wherein a through-hole for providing electrical continuity between a wiring pattern on the front surface of the substrate and a wiring pattern on the back surface is provided in the substrate between the plurality of semiconductor devices. A semiconductor device mounting structure characterized by the above-mentioned.
めの、スルーホール内に基板より熱伝導の低い物質を充
填したことを特徴とする半導体装置の実装構造。3. The mounting structure of a semiconductor device according to claim 2, wherein a substance having lower heat conductivity than the substrate is filled in the through hole for electrical conduction.
方性導電膜を介在させた状態で半導体装置の所定の面を
基板の部品実装面に加熱下で圧着することにより、前記
半導体装置の所定の面と前記基板の部品実装面とを前記
絶縁性樹脂で接合すると共に、前記半導体装置の所定の
面に形成されたバンプと、このバンプに対向する前記基
板の部品実装面に形成の電極とを、前記導電粒子を介し
て電気的に接続する半導体装置の実装構造において、 複数の半導体装置を実装するために、一括して基板の部
品実装面に貼りつけられた異方性導電膜の、 複数の半導体装置が実装される部分の異方性導電膜に、
スリットを設けたことを特徴とする、半導体装置の実装
構造。4. A semiconductor device according to claim 1, wherein a predetermined surface of the semiconductor device is press-bonded to a component mounting surface of the substrate under heating with an anisotropic conductive film in which conductive particles are dispersed in an insulating resin. A predetermined surface of the device and a component mounting surface of the substrate are joined with the insulating resin, and a bump formed on a predetermined surface of the semiconductor device and a bump formed on the component mounting surface of the substrate facing the bump. In the semiconductor device mounting structure in which the electrodes are electrically connected via the conductive particles, the anisotropic conductive material attached to the component mounting surface of the substrate at once to mount a plurality of semiconductor devices. The anisotropic conductive film in the portion of the film where a plurality of semiconductor devices are mounted,
A mounting structure of a semiconductor device, wherein a slit is provided.
徴とする、半導体装置の実装構造。5. A mounting structure of a semiconductor device according to claim 1 or claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27487299A JP3578011B2 (en) | 1999-09-28 | 1999-09-28 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27487299A JP3578011B2 (en) | 1999-09-28 | 1999-09-28 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001102410A true JP2001102410A (en) | 2001-04-13 |
| JP3578011B2 JP3578011B2 (en) | 2004-10-20 |
Family
ID=17547745
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27487299A Expired - Fee Related JP3578011B2 (en) | 1999-09-28 | 1999-09-28 | Semiconductor device mounting structure |
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| Country | Link |
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| JP (1) | JP3578011B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005244219A (en) * | 2004-02-23 | 2005-09-08 | Samsung Techwin Co Ltd | Lead frame for semiconductor package and manufacturing method for same |
| WO2006112383A1 (en) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device and method for manufacturing same |
-
1999
- 1999-09-28 JP JP27487299A patent/JP3578011B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005244219A (en) * | 2004-02-23 | 2005-09-08 | Samsung Techwin Co Ltd | Lead frame for semiconductor package and manufacturing method for same |
| JP4601449B2 (en) * | 2004-02-23 | 2010-12-22 | 三星テクウィン株式会社 | Manufacturing method of lead frame for semiconductor package |
| WO2006112383A1 (en) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device and method for manufacturing same |
| JPWO2006112383A1 (en) * | 2005-04-14 | 2008-12-11 | 松下電器産業株式会社 | Electronic circuit device and manufacturing method thereof |
| US7935892B2 (en) | 2005-04-14 | 2011-05-03 | Panasonic Corporation | Electronic circuit device and method for manufacturing same |
| JP4692544B2 (en) * | 2005-04-14 | 2011-06-01 | パナソニック株式会社 | Electronic circuit device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3578011B2 (en) | 2004-10-20 |
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