JP2001102402A - Electronic circuit and semiconductor element and manufacturing method of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit and a semiconductor element using solder materials with Sn as main components for preventing generation of protrusions and a method for manufacturing the semiconductor element. SOLUTION: Sn-Ag based solder paste 34 filled in dents 32 of a dimple plate 30 is allowed to reflow so that a solder ball 36 can be formed, and an electrode layer including at least an Au layer is formed on the electrode layer of a semiconductor element 10, and a solder bump 16 made of alloy including Sn and Ag is formed on the electrode layer, and Au is diffused from the electrode layer to the solder 16 so that a solder bump made of alloy including Sn and Ag and Au can be formed. The semiconductor element 10 is positioned at the element loading position of a circuit board 20, and the solder bump 16 on an electrode layer 14 of the semiconductor element 10 is soldered with an electrode layer 22 of a circuit board 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit in which a bare chip semiconductor element is solder-connected to a circuit board, a semiconductor element having solder bumps for solder connection, and a method for manufacturing a semiconductor element.

[0002]

2. Description of the Related Art In recent years, with the increasing density of electronic component mounting,
The number of input / output terminals of electronic components has increased, and the demand for finer pitches between terminals has increased. For this reason, as a method of joining an electronic component to a circuit board, a semiconductor element of a bare chip is compared with a joining method of joining a semiconductor chip and an electrode by wire bonding to form a semiconductor element and connecting the semiconductor element to the circuit board. A flip chip bonding method in which solder bumps are formed on a circuit board and directly bonded to a circuit board at once is becoming mainstream.

In flip chip bonding, solder bumps are formed on bare chip electrodes, and the solder bumps are bonded to electrodes on a circuit board. As a material for the solder bump, a Pb-Sn based solder alloy has been widely used so far.

[0004] However, Pb has a plurality of isotopes, and these isotopes are uranium (U) and thorium (Th).
Is an intermediate product or end product in the decay series of, with α decay releasing He atoms in the decay process. For this reason, it has been reported that α rays are generated from Pb in a solder alloy, and the α rays reach a semiconductor element, for example, a CMOS element, and cause a soft error. Further, it is known that Pb melts out due to acid rain when it flows into the soil, which affects the environment. Therefore, there is a strong demand for a solder material that does not use Pb from the viewpoint of environmental protection.

[0005] Therefore, instead of the Pb-Sn-based solder material, a solder alloy containing Sn as a main component having a relatively small amount of radioactive impurities has begun to be used.

[0006]

SUMMARY OF THE INVENTION The present inventors have focused on Sn-Ag alloys as a solder material containing Sn as a main component. In particular, Sn-3.5 wt% Ag eutectic solder has a melting point of 221 ° C., which is relatively close to 183 ° C., which is the melting point of Sn-Pb eutectic solder which has been generally used so far. I'm paying attention. Since this solder material has a high reaction rate with the electrode material Ni or Cu and is easily diffused into the electrode material, the electrode of a normal semiconductor element or circuit board tends to cause defects such as chipping of bumps due to diffusion. Despite the problems, reliable solder bonding has been realized by devising the configuration, film thickness, film forming conditions, and the like of the electrode film.

However, the inventor of the present application has proposed that the above-mentioned Sn
It has been found that when the -3.5 wt% Ag eutectic solder is used, a protrusion as shown in FIG. 1 is generated on the solder bump. FIG. 1A is a plan view of the semiconductor chip 100 as viewed from above, and FIG. 1B is a cross-sectional view.

On the solder bump 104 formed on the electrode 102 of the semiconductor chip 100, a projection 106 having a length of about twice the diameter of the bump is formed. This protrusion 106
Can reach up to 200-300 μm. For this reason, when the pitch of the electrode 102 of the semiconductor chip 100 is 200 μm or less, the protrusion 106 contacts the adjacent solder bump 104 or the protrusion 1
06 causes ion migration or the like, and causes a defect such as an electric short circuit, thereby deteriorating the reliability.

An object of the present invention is to provide an electronic circuit, a semiconductor element, and a method of manufacturing a semiconductor element using a solder material containing Sn as a main component and not generating the above-mentioned protrusions.

[0010]

Means for Solving the Problems The present inventor has conducted intensive studies to solve the above-mentioned problems, elucidated the mechanism of formation of protrusions, and as a result, has found that an appropriate amount of Au can be added to the Sn-Ag alloy. It was found that the use of a solder alloy containing Sn, Ag, and Au can prevent the formation of protrusions.

FIG. 2 shows a phase diagram of the Sn-Ag alloy.
As shown in FIG. 2, when the Sn-Ag-based alloy contains Sn as a main component, particularly near Sn-3.5 wt% Ag, it is composed of two phases of Sn and Ag ₃ Sn in a molten state. X
It is clear from the results of analysis such as line diffraction that the protrusion is Ag ₃ Sn. Therefore, assuming from the state diagram of FIG. 2, when the weight ratio of Ag is more than 3.5 wt%, when the solder alloy changes from a liquid phase to a solid phase, Ag ₃ Sn gradually precipitates, and the It is presumed that Ag ₃ Sn projections are generated by the growth of the crystal. This is the mechanism by which protrusions are generated.

The formation of protrusions when Au is added to a Sn-Ag alloy is prevented by the following mechanism. When Au is melted into the solder containing Sn as a main component, it is combined with Sn during cooling to generate an Au-Sn compound. This Au-Sn compound has a property of being easily distributed on the solder surface.

When the Au—Sn compound is formed on the surface of the solder bump, Ag ₃ Sn crystal does not grow on the surface of the bump during cooling of the solder alloy, but remains in the solder in a fine crystalline state.

Further, as in the case of an Ag—Sn alloy,
It is also conceivable that the Ag ₃ Sn crystal formed in the solder bump grows and breaks through the outermost surface layer of the bump to become a projection. However, the outermost surface layer of the bump is Au-
When it is a Sn compound, the mechanical properties of the Au—Sn compound,
Since mainly the Young's modulus and the tensile strength are larger than those of the Ag ₃ Sn compound, the Ag ₃ Sn crystal is retained in the solder bump without breaking through the outermost surface layer of the Au—Sn compound.

By such a mechanism, Sn-Ag
By adding an appropriate amount of Au to the system alloy and using a solder alloy containing Sn, Ag, and Au, it is possible to prevent the formation of projections.

When the weight ratio of Sn is 90 wt% or more,
In the case of a Sn—Ag alloy having a weight ratio of Ag of 2 wt% or more, it is desirable that the weight ratio of Au be in the range of 0.1 to 5 wt%. By laminating an Au layer on the electrode, Au
Is supplied, the above range corresponds to a range of 0.05 to 2 μm as the thickness of the Au layer. Such a range is desirable for the following reasons.

If the weight ratio of Au is less than 0.1% by weight, the Au—Sn compound cannot be formed sufficiently,
The crystal growth of ₃ Sn cannot be completely suppressed.

Conversely, if the weight ratio of Au is larger than 5 wt%, the amount of the Au—Sn compound is too large, and the mechanical properties of the solder itself deteriorate, and the reliability of the solder joint such as fatigue life is reduced. It is because it falls. In addition, when the Au content increases, the melting point of the solder material increases, the temperature difference between the liquidus line and the solidus line becomes 20 ° C. or more, and the time during which the solder bumps are present in the liquid becomes longer, resulting in displacement. This is because the reliability of the soldering process is reduced.

Therefore, the above-mentioned object is to provide Sn, Ag and A
The present invention is achieved by an electronic circuit in which a semiconductor element is solder-connected to a circuit board by a solder alloy containing u.

In the above-mentioned electronic circuit, the solder alloy has a weight ratio of Sn of at least 90 wt%, a weight ratio of Ag of at least 2 wt%, and a weight ratio of Au within a range of 0.1 to 5 wt%. It is desirable to include

The above object is achieved by a semiconductor device characterized in that a solder bump made of a solder alloy containing Sn, Ag and Au is formed.

In the above-mentioned semiconductor device, the solder alloy has a weight ratio of Sn of at least 90 wt%, a weight ratio of Ag of at least 2 wt%, and a weight ratio of Au within a range of 0.1 to 5 wt%. It is desirable to include

The object is to form an electrode layer including at least an Au layer on an electrode, form a solder bump made of a solder alloy containing Sn and Ag on the electrode layer, and remove Au from the electrode layer. This is achieved by a method for manufacturing a semiconductor device, characterized in that a solder bump made of a solder alloy containing Sn, Ag and Au is diffused into a bump to form a solder bump.

The object of the present invention is to form an Au layer on the inner surface of a depression of a substrate for bump formation, fill the depression with a solder paste containing Sn and Ag, and diffuse Au from the Au layer on the inner surface of the depression into the solder paste. Then, a solder ball made of a solder alloy containing Sn, Ag, and Au is formed, and the solder ball is transferred onto an electrode of a semiconductor element to form a solder bump made of a solder alloy containing Sn, Ag, and Au. This is achieved by a method of manufacturing a semiconductor device, which is characterized by being formed.

[0025] The above object is to provide a method for forming a recess in a substrate for forming a bump.
Filling a solder paste containing Sn, Ag, and Au, forming a solder ball made of a solder alloy containing Sn, Ag, and Au in the depression, and transferring the solder ball onto an electrode of a semiconductor element, This is achieved by a method of manufacturing a semiconductor device, wherein a solder bump made of a solder alloy containing Sn, Ag, and Au is formed.

In the method of manufacturing a semiconductor device described above,
Preferably, the Au layer has a thickness of 0.05 to 2 μm.

In the above-described method for manufacturing a semiconductor device,
The solder alloy has a weight ratio of Sn of 90 wt% or more,
g is 2 wt% or more, and Au is 0.1 to 5 wt%.
It is desirable to include a solder material that is in the range of wt%.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to one embodiment of the present invention will be described with reference to FIG. In the semiconductor element 10 of this embodiment, solder bumps 16 are formed on the electrode layers 14 of the bare chip 12. Approximately 1 on bare chip 12
00 nm thick Al layer 14a and about 100 nm thick Ti layer 1
An electrode layer 14 made of a Ni layer 4b and a Ni layer 14c having a thickness of about 4 μm is formed. A bump 16 is formed. In the solder alloy of the present embodiment, the weight ratio of Sn is 90 wt% or more, and A
g is 2 wt% or more, and Au is 0.1 to 5 wt%.
It is desirably within the range of wt%.

According to the present embodiment, since an appropriate amount of Au is added to the Sn-Ag alloy as a solder alloy for solder connection, a projection of Ag ₃ Sn crystal is formed on the solder bump during the solder bump forming process. Generation can be effectively prevented.

FIG. 4 shows an electronic circuit using the semiconductor device of this embodiment. In this electronic circuit, the semiconductor element 10 of the present embodiment is connected to a circuit board 20 by soldering. On the circuit board 20, a Cr layer 22a having a thickness of about 100 nm and about 0.5
An electrode layer 22 including a Cu layer 22b having a thickness of μm, a Ni layer 22c having a thickness of about 3 μm, and an Au layer 22d having a thickness of about 500 nm is formed, and the solder bump 16 of the semiconductor element 10 is connected to the electrode layer 22.

According to the present embodiment, since no projection of Ag ₃ Sn crystal is formed on the solder bump 16 of the semiconductor element 10, the projection causes ion migration or the like, or a defect such as an electric short occurs. Therefore, sufficient reliability can be ensured.

A plurality of manufacturing methods for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. In order to manufacture the semiconductor element of the present embodiment, when the solder bump 16 is formed, Sn-Ag
It is necessary that an appropriate amount of Au is added to the system alloy to form a solder alloy containing Sn, Ag, and Au. For this purpose, Au may be added to the Sn-Ag-based alloy from the beginning, or Au may be added immediately before the formation of the solder bump 16. There are the following manufacturing methods depending on the timing of adding Au.

(First Manufacturing Method) A first manufacturing method of a semiconductor device according to one embodiment of the present invention will be explained with reference to FIGS.

First, a dimple plate 30 for bump formation is prepared (FIG. 5).
(A)). The dimple plate 30 has a mortar-shaped depression 32 for forming a bump.

Next, in the depression 32 of the dimple plate 30, Sn-A in which 3.5% by weight of Ag was mixed in Sn was used.
The g-based solder paste 34 is filled (FIG. 5B). Subsequently, the dimple plate 30 is heated to about 280 ° C. and reflowed to form the solder balls 36 (FIG. 5).
(C)).

On the other hand, on the bare chip 12 of the semiconductor device 10, an Al layer 14a having a thickness of about 100 nm, a Ti layer 14b having a thickness of about 100 nm, a Ni layer 14c having a thickness of about 4 μm, and
An electrode layer 14 made of an Au layer 14d having a thickness of nm is formed in advance. For example, a Ti layer 14b is formed on the Al electrode 14a on the surface of the bare chip 12 by a sputtering method. Subsequently, the Ni layer 14 is formed on the Ti layer 14b by electrolytic plating.
Form c. Subsequently, the Ni layer 1 is formed by electrolytic plating.
An Au layer 14d is formed on 4c. The thickness of the Au layer 14d is desirably in the range of 0.05 to 2 μm.

Next, the semiconductor element 10 and the dimple plate 30 are aligned (FIG. 6A), and the dimple plate 30 is brought close to the semiconductor element 10 so that the semiconductor element 1
The solder balls 36 of the dimple plate 30 are transferred to the 0 electrode layer 14 (FIG. 5D). The transferred solder ball 36 is formed as a solder bump 16 on the electrode layer 14 of the bare chip 12 (FIG. 5E). Immediately after the transfer, as shown in FIG. 6B, a solder bump 16 of an Sn-Ag alloy is formed on the Au layer 14d which is the uppermost layer of the electrode layer 14 on the bare chip 12. Then, about 27
By heating at 0 to 280 ° C., the uppermost Au layer 14 is formed.
Au diffuses into the solder bump 16 as shown in FIG.
As shown in (1), a solder bump 16 in which Au is added to a Sn-Ag alloy is formed on the Ni layer 14c of the electrode layer 14 on the bare chip 12.

Next, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20, the semiconductor element 10 is brought close to the circuit board 20, and the solder bumps 16 on the electrode layers 14 of the semiconductor element 10 are attached to the circuit board 20. Solder bonding to the electrode layer 22 (FIG. 5F). Thus, an electronic circuit is completed.

As described above, according to the first manufacturing method, Sn
Since the solder bumps are formed of a solder alloy containing Ag, Au and Au, it is possible to effectively prevent the formation of Ag ₃ Sn crystal projections on the solder bumps.

(Second Manufacturing Method) A second manufacturing method of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

First, a dimple plate 30 for bump formation is prepared. A resist 40 is applied to the surface area other than the depression 32 of the dimple plate 30, and about 100 nm to 2 μm is formed on the inner surface of the depression 32 by a sputtering method or an evaporation method.
An Au layer 38 having a thickness of m is formed (FIG. 7A). This Au
The thickness of the layer 38 is desirably in the range of 0.05 to 2 μm.

Next, on the Au layer 38 in the depression 32 of the dimple plate 30, a Sn-Ag-based solder paste 34 in which 3.5% by weight of Ag is mixed with Sn is filled (FIG. 7B). Subsequently, the dimple plate 30 is heated to about 280 ° C. and reflowed to form the solder balls 36 (FIG. 7C). Sn-Ag solder paste 3
The Au in the Au layer 38 diffuses into the solder ball 36 to form a solder ball 36 in which Au is added to the Sn-Ag alloy.

On the other hand, on the bare chip 12 of the semiconductor element 10, an electrode layer 14 composed of an Al layer 14a having a thickness of about 100 nm, a Ti layer 14b having a thickness of about 100 nm, and a Ni layer 14c having a thickness of about 4 μm is formed.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the dimple plate 30 is brought close to the semiconductor element 10 so that the electrode layer 14 of the semiconductor element 10 is formed.
Then, the solder balls 36 of the dimple plate 30 are transferred (FIG. 7D). The transferred solder ball 36 is formed as a solder bump 16 on the electrode layer 14 of the bare chip 12 (FIG. 7E). As a result, as shown in FIG. 8, the solder bump 16 to which the Sn—Ag based alloy Au was added was formed on the Ni layer 14 c of the electrode layer 14 on the bare chip 12.
Is formed.

Next, similarly to the first manufacturing method, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20,
The semiconductor element 10 is brought close to the circuit board 20, and the solder bumps 16 on the electrode layers 14 of the semiconductor element 10 are
To the electrode layer 22 of FIG. Thus, an electronic circuit is completed.

According to the first manufacturing method, Sn and Ag
Since the solder bumps are formed of a solder alloy containing Au and Au, it is possible to effectively prevent the formation of projections of Ag ₃ Sn crystals on the solder bumps.

(Third Manufacturing Method) A third manufacturing method of the semiconductor device according to one embodiment of the present invention will be explained with reference to FIGS.

First, a dimple plate 30 for bump formation is prepared. Depression 3 of this dimple plate 30
2 is filled with a solder paste 34 in which an appropriate amount of Au is mixed in a Sn-Ag alloy (FIG. 9A). The solder paste 34 has, for example, a weight ratio of Sn of 90 wt% or more,
Ag weight ratio of 2 wt% or more, Au weight ratio of 0.1 to
It is within the range of 5 wt%.

Next, the dimple plate 30 is set to about 280
The solder ball 36 is formed by heating to ℃ and reflowing (FIG. 9B). The solder ball 36 is obtained by adding Au to the Sn-Ag alloy.

On the other hand, on the bare chip 12 of the semiconductor element 10, an electrode layer 14 composed of an Al layer 14a having a thickness of about 100 nm, a Ti layer 14b having a thickness of about 100 nm, and a Ni layer 14c having a thickness of about 4 μm is formed.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the dimple plate 30 is brought close to the semiconductor element 10 so that the electrode layer 14 of the semiconductor element 10 is formed.
Then, the solder balls 36 of the dimple plate 30 are transferred (FIG. 9C). The transferred solder balls 36 are formed as the solder bumps 16 on the electrode layer 14 of the bare chip 12 (FIG. 9D). As a result, as shown in FIG. 10, the solder bump 1 containing Au of the Sn—Ag alloy was added on the Ni layer 14 c of the electrode layer 14 on the bare chip 12.
6 are formed.

Next, similarly to the first manufacturing method, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20,
The semiconductor element 10 is brought close to the circuit board 20, and the solder bumps 16 on the electrode layers 14 of the semiconductor element 10 are
To the electrode layer 22 of FIG. Thus, an electronic circuit is completed.

According to the third manufacturing method, Sn and Ag are used.
Since the solder bumps are formed of a solder alloy containing Au and Au, it is possible to effectively prevent the formation of projections of Ag ₃ Sn crystals on the solder bumps.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the Au layer is formed on the electrode layer of the semiconductor element or in the depression of the dimple plate, but the Au layer is formed on the electrode layer of the circuit board to be joined, and the Au alloy is formed from the Au layer. The gold may be diffused to the surface. Further, an Au layer may be formed on both electrode layers of the semiconductor element and the circuit board.

[0055]

(Examples 1-1 to 1-6) Examples 1-1 to 1-6
In -6, a semiconductor device was manufactured by the first manufacturing method.

The solder paste 34 filled in the depressions 32 of the dimple plate 30 is reflowed to
6 was formed. As the solder paste 34, in Example 1-1, a Sn-Ag-based solder alloy in which 3.0% by weight of Ag was mixed with Sn was used, and in Example 1-2, 3.5% of Sn was used as Sn.
% Of Ag mixed Sn-Ag based solder alloy,
In Example 1-3, a Sn-Ag-based solder alloy in which 4.0 wt% of Ag was mixed with Sn was used.
Example 1 using a Sn—Ag—Zn-based solder alloy in which 3.5 wt% of Ag and 1.0 wt% of Zn are mixed in n
At -5, 3.5 wt% Ag and 1.0 wt% B were added to Sn.
In Example 1-6, a Sn-Ag-Bi-based solder alloy mixed with Sn was used.
A Sn-Ag-Cu solder alloy mixed with 7 wt% of Cu was used. In these Examples 1-1 to 1-6, the abundance ratio of Pb in Sn of the solder alloy was 1 ppm or less, and the α dose was 0.01 cph / cm ² or less.

A Ti layer 14b having a thickness of about 100 nm is formed on the Al layer 14a of the bare chip 12 of the semiconductor device 10 by a sputtering method, and the Ti layer 14b is formed by an electrolytic plating method.
A Ni layer 14c having a thickness of about 4 μm is formed on the Ni layer 14b, and a 500 nm thick Au layer 14d is formed on the Ni layer 14c by electrolytic plating.
Was formed.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the electrode layer 14 of the semiconductor element 10 is positioned.
The solder ball 36 of the dimple plate 30 is transferred to the solder bump 16 on the electrode layer 14 of the bare chip 12.
Was formed. Au diffused into the solder bump 16 from the Au layer 14d, which is the uppermost layer of the electrode layer 14, to form the solder bump 16 in which Au was added to the above-mentioned solder alloy.

Next, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20, and the electrode layer 1 of the semiconductor element 10 is
4 was soldered to the electrode layer 22 of the circuit board 20 to produce an electronic circuit.

During the manufacturing process, it was visually observed whether or not projections were generated on the solder bumps 16. As a result, no protrusion was observed in all of Examples 1-1 to 1-6.

The electronic circuit in which the semiconductor element 10 is soldered to the circuit board 20 is subjected to 125 ° C., 85% RH, 5 V
PCT (Presser Cooker)
Test). As a result, all Examples 1-
In 1 to 1-6, the insulation property was able to be secured for 200 hours or more.

The same electronic circuit was subjected to a heat cycle test at 125 ° C. for 30 minutes and at −55 ° C. for 30 minutes. as a result,
A fatigue life of 200 cycles or more was confirmed in all Examples 1-1 to 1-6.

(Examples 2-1 to 2-6) Examples 2-1 to 2-6
In 2-6, a semiconductor element was manufactured by the second manufacturing method.

A 500 nm thick Au is formed on the inner surface of the depression 32 of the dimple plate 30 by sputtering or vapor deposition.
Layer 38 was formed. Next, the solder paste 34 filled in the depressions 32 of the dimple plate 30 was reflowed to form solder balls 36.

The solder paste 34 is used in the embodiment 2-1.
Sn-Ag-based rice with 3.0 wt% Ag mixed in Sn
In Example 2-2, 3.5% by weight of Sn was used.
Using a Sn-Ag solder alloy mixed with Ag
In Example 2-3, Sn in which 4.0 wt% of Ag was mixed in Sn was used.
An n-Ag solder alloy was used, and in Example 2-4, Sn was used.
Mixed with 3.5 wt% of Ag and 1.0 wt% of Zn
Example 2 using the Sn-Ag-Zn based solder alloy
In No. 5, 3.5 wt% of Ag and 1.0 wt% of Bi were added to Sn.
Using a Sn-Ag-Bi solder alloy mixed with
In Example 2-6, 3.5 wt% of Ag and 0.7 w
Sn-Ag-Cu based solder alloy mixed with t% Cu
It was used. In these Examples 2-1 to 2-6,
The abundance ratio of Pb in Sn of solder alloy is 1 ppm or less.
Α dose is 0.01 cph / cm ^TwoUse the following
did.

Au diffuses into the solder bump 16 from the Au layer 38 on the inner surface of the recess 32 of the dimple plate 30,
Solder ball 3 in which Au is added to the above-mentioned solder alloy 3
6 was formed.

A Ti layer 14b having a thickness of about 100 nm is formed on the Al layer 14a of the bare chip 12 of the semiconductor element 10 by a sputtering method, and the Ti layer 14b is formed by an electrolytic plating method.
An Ni layer 14c having a thickness of about 4 μm was formed on “b”.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the electrode layer 14 of the semiconductor element 10 is positioned.
The solder ball 36 of the dimple plate 30 is transferred to the solder bump 16 on the electrode layer 14 of the bare chip 12.
Was formed.

Next, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20, and the electrode layer 1 of the semiconductor element 10 is
4 was soldered to the electrode layer 22 of the circuit board 20 to produce an electronic circuit.

It was observed by an optical microscope whether or not projections were generated on the solder bumps 16 during the manufacturing process.
As a result, no protrusion was observed in all of Examples 2-1 to 2-6.

The electronic circuit in which the semiconductor element 10 is soldered to the circuit board 20 is subjected to 125 ° C., 85% RH, 5 V
PCT test was performed at an applied voltage of. As a result, in all of Examples 2-1 to 2-6, the insulation was able to be secured for 200 hours or more.

The same electronic circuit was subjected to a heat cycle test at 125 ° C. for 30 minutes and at −55 ° C. for 30 minutes. as a result,
A fatigue life of 200 cycles or more was confirmed in all Examples 2-1 to 2-6.

(Examples 3-1 to 3-6) Examples 3-1 to 3-6
In 3-6, a semiconductor device was manufactured by the third manufacturing method.

The S in the recess 32 of the dimple plate 30
The solder paste 34 in which an appropriate amount of Au was mixed in the n-Ag alloy was filled.

The solder paste 34 used in the embodiment 3-1 is a Sn-Ag based solder alloy in which 3.0 wt% of Ag is mixed in Sn, and the solder paste 34 in the embodiment 3-2 is 3.5 wt% of Sn.
In Example 3-3, Sn containing 4.0 wt% of Ag was mixed with Sn.
An n-Ag solder alloy was used, and in Example 3-4, Sn was used.
Example 3 using a Sn-Ag-Zn-based solder alloy mixed with 3.5 wt% of Ag and 1.0 wt% of Zn
In No. 5, 3.5 wt% of Ag and 1.0 wt% of Bi were added to Sn.
Using a Sn-Ag-Bi solder alloy mixed with
In Example 3-6, 3.5 wt% of Ag and 0.7 w
A Sn-Ag-Cu-based solder alloy mixed with t% Cu was used, and 1 wt% of gold was added to each of them.
In these Examples 3-1 to 3-6, S of the solder alloy
The abundance of Pb in n was 1 ppm or less, and the α dose was 0.01 cph / cm ² or less.

The solder paste 34 in the depression 32 was reflowed from the dimple plate 30 to form a solder ball 36 on the solder alloy having the above-described composition.

A Ti layer 14b having a thickness of about 100 nm is formed on the Al layer 14a of the bare chip 12 of the semiconductor element 10 by a sputtering method, and the Ti layer 14b is formed by an electrolytic plating method.
An Ni layer 14c having a thickness of about 4 μm was formed on “b”.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the electrode layer 14 of the semiconductor element 10 is positioned.
The solder ball 36 of the dimple plate 30 is transferred to the solder bump 16 on the electrode layer 14 of the bare chip 12.
Was formed.

Next, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20 and the electrode layer 1 of the semiconductor element 10 is
4 was soldered to the electrode layer 22 of the circuit board 20 to produce an electronic circuit.

During the manufacturing process, it was visually observed whether or not protrusions were generated on the solder bumps 16. As a result, no protrusion was observed in any of Examples 3-1 to 3-6.

The electronic circuit in which the semiconductor element 10 is soldered to the circuit board 20 is subjected to 125 ° C., 85% RH, 5 V
PCT test was performed at an applied voltage of. As a result, in all of Examples 3-1 to 3-6, the insulating property was able to be secured for 200 hours or more.

The same electronic circuit was subjected to a heat cycle test at 125 ° C. for 30 minutes and at −55 ° C. for 30 minutes. as a result,
In all Examples 3-1 to 3-6, a fatigue life of 200 cycles or more was confirmed.

(Comparative Examples 1 to 6) In Comparative Examples 1 to 6, solder bumps were formed without adding gold.

The solder paste 34 filled in the depressions 32 of the dimple plate 30 is reflowed to
6 was formed. The solder paste 34 is S in Comparative Example 1.
A Sn-Ag solder alloy in which 3.0 wt% of Ag is mixed into n is used. In Comparative Example 2, 3.5 wt% of Ag was added to Sn.
Comparative Example 3 using a Sn-Ag solder alloy mixed with
In this example, a Sn-Ag solder alloy in which 4.0 wt% of Ag was mixed in Sn was used. In Comparative Example 4, 3.5 wt% of Sn was used.
Ag and 1.0 wt% Zn mixed with Sn-Ag-
A Zn-based solder alloy was used. In Comparative Example 5, 3.5 was added to Sn.
Sn- mixed with wt% Ag and 1.0 wt% Bi
An Ag-Bi-based solder alloy was used. In Comparative Example 6, a Sn-Ag-Cu-based solder alloy in which 3.5 wt% of Ag and 0.7 wt% of Cu were mixed in Sn was used. In these Comparative Examples 1 to 6, the abundance ratio of Pb in Sn of the solder alloy was 1 ppm or less, and the α dose was 0.01 cph / cm.
^The following ^two were used.

A Ti layer 14b having a thickness of about 100 nm is formed on the Al layer 14a of the bare chip 12 of the semiconductor element 10 by a sputtering method, and the Ti layer 14b is formed by an electrolytic plating method.
An Ni layer 14c having a thickness of about 4 μm was formed on “b”.

Next, the semiconductor element 10 and the dimple plate 30 are aligned, and the electrode layer 14 of the semiconductor element 10 is positioned.
The solder ball 36 of the dimple plate 30 is transferred to the solder bump 16 on the electrode layer 14 of the bare chip 12.
Was formed.

Next, the semiconductor element 10 is aligned with the element mounting position of the circuit board 20, and the electrode layer 1 of the semiconductor element 10 is
4 was soldered to the electrode layer 22 of the circuit board 20 to produce an electronic circuit.

During the manufacturing process, it was visually observed whether or not protrusions were generated on the solder bumps 16. As a result, Comparative Example 1 has a probability of 0.05%, Comparative Example 2 has a probability of 0.1%, Comparative Example 3 has a probability of 0.2%, and Comparative Example 4 has a probability of 0.1%. In Comparative Example 5, protrusions occurred at a probability of 0.1%, and in Comparative Example 6, protrusions occurred at a probability of 0.2%.

The electronic circuit in which the semiconductor element 10 is soldered to the circuit board 20 is subjected to 125 ° C., 85% RH, 5 V
PCT test was performed at an applied voltage of. As a result, in all of Comparative Examples 1 to 6, the insulating property could be secured only for about 50 to 100 hours.

A heat cycle test was performed on the same electronic circuit at 125 ° C. for 30 minutes and at −55 ° C. for 30 minutes. as a result,
In all Comparative Examples 1 to 6, a fatigue life of 200 cycles or more was confirmed.

[0091]

[Table 1]

Embodiments 1-1 to 1-6 and Embodiment 2 described above
Table 1 collectively shows experimental results of -1 to 2-6, Examples 3-1 to 3-6, and Comparative Examples 1 to 6.

[0093]

As described above, according to the present invention, Sn-A
By adding an appropriate amount of Au to the g-based alloy and using a solder alloy containing Sn, Ag, and Au, a reliable solder joint can be realized without occurrence of protrusions.

[Brief description of the drawings]

FIG. 1 is a view showing a state in which a protrusion is generated on a solder bump of a semiconductor element.

FIG. 2 is a phase diagram of a Sn—Ag alloy.

FIG. 3 is a sectional view showing a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a sectional view showing an electronic circuit according to an embodiment of the present invention.

FIG. 5 is a process sectional view of a first method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view showing details of a first method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a process sectional view of a second method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 8 is a sectional view showing details of a second method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a process sectional view of a third method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 illustrates a third example of a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the details of the manufacturing method of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor element 12 ... Bear chip 14 ... Electrode layer 14a ... Al layer 14b ... Ti layer 14c ... Ni layer 14d ... Au layer 16 ... Solder bump 20 ... Circuit board 22 ... Electrode layer 22a ... Cr layer 22b ... Cu layer 22c ... Ni Layer 22d Au layer 30 Dimple plate 32 Depression 34 Solder paste 36 Solder ball 38 Au layer 40 Resist 100 Semiconductor chip 102 Electrode 104 Solder bump 106 Projection

Claims (9)

[Claims] 1. An electronic circuit, wherein a semiconductor element is solder-connected to a circuit board by a solder alloy containing Sn, Ag, and Au. 2. The electronic circuit according to claim 1, wherein the solder alloy has a weight ratio of Sn of 90 wt% or more,
g is 2 wt% or more, and Au is 0.1 to 5 wt%.
An electronic circuit comprising a solder material in the range of wt%. 3. A semiconductor device having a solder bump made of a solder alloy containing Sn, Ag and Au. 4. The semiconductor device according to claim 3, wherein the solder alloy has a weight ratio of Sn of 90 wt% or more and A
g is 2 wt% or more, and Au is 0.1 to 5 wt%.
A semiconductor device comprising a solder material in a range of wt%. 5. An electrode layer including at least an Au layer is formed on an electrode, a solder bump made of a solder alloy containing Sn and Ag is formed on the electrode layer, and Au is formed on the bump from the electrode layer. A method for manufacturing a semiconductor device, comprising: forming a solder bump made of a solder alloy containing Sn, Ag, and Au by diffusing. 6. An Au layer is formed on an inner surface of a depression of a substrate for forming a bump, and the depression is filled with a solder paste containing Sn and Ag. Au is diffused from the Au layer on the inner surface of the depression into the solder paste. Forming a solder ball made of a solder alloy containing Sn, Ag and Au, transferring the solder ball onto an electrode of a semiconductor element,
A method of manufacturing a semiconductor device, comprising forming a solder bump made of a solder alloy containing n, Ag, and Au. 7. Sn and Ag are formed in a depression of a substrate for bump formation.
A solder paste made of a solder alloy containing Sn, Ag, and Au is formed in the depression, and the solder ball is transferred onto an electrode of a semiconductor element.
A method of manufacturing a semiconductor device, comprising forming a solder bump made of a solder alloy containing n, Ag, and Au. 8. The method for manufacturing a semiconductor device according to claim 5, wherein said Au layer has a thickness of 0.05 to 2 μm. 9. The method for manufacturing a semiconductor device according to claim 5, wherein a weight ratio of Sn in the solder alloy is 90 wt% or more, and A
g is 2 wt% or more, and Au is 0.1 to 5 wt%.
A method for manufacturing a semiconductor device, comprising a solder material in a range of wt%.