JP2001100708A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device for preventing the deterioration of the contrast of a display screen displayed on a liquid crystal display element due to the variation of the characteristics of the liquid crystal display element. SOLUTION: This liquid crystal display device is provided with a liquid crystal display element having plural picture elements and plural video signal lines for impressing gradation voltages corresponding to display data to the plural picture elements and a video signal line driving means for supplying the gradation voltages corresponding to the display data to each video signal line. The video signal line driving means is provided with a gradation voltage generating means for dividing a gradation reference voltage to be inputted from the outside part, and for generating plural gradation voltages. Then, the gradation voltages for several gradations continuing to the gradation voltages whose potential difference is the highest against a voltage to be impressed to the common electrode of each picture element among the gradation voltages generated by the gradation voltage generating means are prepared so that the inter-gradation potential difference can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a video signal line driving means (drain driver) of a liquid crystal display device capable of multi-tone display.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switchingly driving the active element is widely used as a display device of a notebook type personal computer or the like. This active matrix type liquid crystal display device applies a video signal voltage (a gray scale voltage corresponding to display data; hereinafter, referred to as a gray scale voltage) to a pixel electrode via an active element. There is no need to use a special driving method for preventing crosstalk unlike a simple matrix type liquid crystal display device, and multi-tone display is possible. TF is one of the active matrix type liquid crystal display devices.
A liquid crystal display panel (TFT-LCD) of a T (Thin Film Transistor) system, a drain driver disposed on the upper side of the liquid crystal display panel, and a gate driver and an interface section disposed on a side surface of the liquid crystal display panel are provided. A TFT type liquid crystal display module is known. In this TFT type liquid crystal display module, a gradation voltage generation circuit is provided in a drain driver,
A gradation voltage selection circuit (decoder circuit) for selecting one gradation voltage corresponding to display data from a plurality of gradation voltages generated by the gradation voltage generation circuit, and a gradation voltage selection circuit And an amplifier circuit to which the inputted one gradation voltage is inputted. Such a technique is described in, for example, Japanese Patent Application No. 8-866668.

[0003]

The gradation voltage generation circuit in the drain driver is constituted by a resistance voltage dividing circuit for dividing a plurality of gradation reference voltages supplied from a power supply circuit. In this case, in general, the relationship between the voltage applied to the liquid crystal layer and the transmittance is not linear, and the transmittance changes little with respect to the voltage applied to the liquid crystal layer at high and low transmittances. Where the change in transmittance is large. Therefore, the resistance value of each voltage dividing resistor of the resistance voltage dividing circuit in the gradation voltage generating circuit in the drain driver is not the same, and a predetermined weight is set according to the relationship between the voltage applied to the liquid crystal layer and the transmittance. Have been.

FIG. 10 is a schematic diagram for explaining each gradation voltage generated by a gradation voltage generation circuit in a conventional drain driver. Note that FIG. 10 is a graph in which the horizontal axis represents the gradation (64 gradations) and the vertical axis represents each gradation voltage. In FIG. Gray scale voltage. As can be seen from FIG. 10, in the conventional gray scale voltage generation circuit, in the range from gray scale 0 to gray scale 8, the larger the potential difference between the common voltage and the gray scale voltage, the larger the potential difference between adjacent gray scale voltages. In this direction, the potential difference (inter-grayscale potential difference) increased. That is, in the conventional gradation voltage generation circuit, the line connecting the absolute value of the difference between each gradation voltage between the 0th gradation and the 8th gradation and the voltage of Vcom applied to the common electrode is represented by the 0th gradation. Gray scale voltage (V ″ in FIG. 10)
9) and the voltage Vcom with respect to the straight line connecting the absolute value of the difference between the Vcom voltage and the absolute value of the difference between the eight gradation voltages (V ″ 8 in FIG. 10) and the voltage Vcom. In other words, the gray scale voltage generated by the conventional gray scale voltage generation circuit is
On the gradation voltage side where the potential difference from the common voltage is large, the S-shape is horizontal, and on the gradation voltage side where the potential difference from the common voltage is small, the inverted S-shape is horizontal. If the TFT type liquid crystal display module is a normally white type, 63 gray scales indicate "white" and 0 gray scales indicate "black" in FIG.

[0005] Now, if the characteristics of the TFT substrate are varied due to the influence of the manufacturing process and the like and the pixel write voltage is insufficient, a pixel which should have a gray scale voltage of 0 gray scale (black) is added to a pixel of 1 gray scale. The gradation voltage is written. Therefore, there is a problem that the contrast is reduced because the “black” pixels are not black. If each gradation voltage generated by the gradation voltage generation circuit has a value as shown in the graph of FIG. 10, a potential difference between gradations between 0 gradation (black) and 1 gradation is large. In the above case, there is a problem that the contrast is significantly reduced.
In the above description, the normally white type liquid crystal display module which becomes “black” when the gradation voltage is 0 is described. However, the normally black liquid crystal display module becomes “white” when the gradation voltage is 0. Type liquid crystal display module,
Since the “white” pixel is no longer “white”, the contrast is reduced as described above. The present invention has been made in order to solve the problems of the prior art, and an object of the present invention is to provide a liquid crystal display device, in which a variation in characteristics of the liquid crystal display element causes a display screen to be displayed on the liquid crystal display element. It is an object of the present invention to provide a technique capable of preventing a decrease in contrast. The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention includes a plurality of pixels,
A liquid crystal display element having a plurality of video signal lines for applying a gray scale voltage corresponding to display data to one of the liquid crystal layers of the plurality of pixels; and a gray scale voltage corresponding to the display data to each of the video signal lines. A liquid crystal display device comprising: a video signal line driving unit that supplies a plurality of grayscale voltages by dividing a grayscale reference voltage input from the outside; Generating means, wherein, among the gray scale voltages generated by the gray scale voltage generating means, a voltage applied to the other of the liquid crystals of each pixel has several levels continuous with the gray scale voltage having the largest potential difference. It is characterized in that the gradation voltage for the adjustment is set so that the potential difference between the gradations becomes small.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. <Basic Configuration of Display Device to which the Present Invention is Applied> FIG. 1 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module to which the present invention is applied. The liquid crystal display module shown in FIG. 1 adopts the digital interface as an interface between the PC side, the liquid crystal display module of the present embodiment, LVDS from the computer main body (L ow V oltage D ifferential S ignaling ), Each control timing signal of a clock signal (CK), a display timing signal (DTMG), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and display data (R, G, B) are transmitted. . For this reason, in the present embodiment, the LVDS receiver 160 constituted by a semiconductor integrated circuit device (LSI) is connected to the connector (CN1).
Is connected. In addition, a liquid crystal display panel (TFT-LC
D) The drain driver 130 is arranged below the 10;
Further, a gate driver 1 is provided on a side surface of the liquid crystal display panel 10.
40 are arranged. Behind the liquid crystal display panel 10, a timing converter 100 and a power supply circuit 120 are provided.
Is arranged. The drain driver 130 and the gate driver 140 are provided on the TFT substrate of the liquid crystal display panel 10 by COG.
(Chip On Glass) method. FIG.
Now, the drain driver 130 and the gate driver 1
Although 40 is represented by one block diagram, it is actually composed of a plurality of semiconductor integrated circuit devices (LSIs).

<Configuration of liquid crystal display panel 10 shown in FIG. 1>
FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel 10 shown in FIG. As shown in FIG. 2, the liquid crystal display panel 10 has a plurality of pixels formed in a matrix. Each pixel includes two adjacent signal lines (a drain signal line (D) or a gate signal line (G)) and two adjacent signal lines (a gate signal line (G) or a drain signal line (D)). And is arranged in the intersection area with. Each pixel has a thin film transistor (TFT1, TFT2), and the source electrode of the thin film transistor (TFT1, TFT2) of each pixel is connected to the pixel electrode (ITO1). Since a liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (ITO2), a liquid crystal capacitance (CLC) is equivalently provided between the pixel electrode (ITO1) and the common electrode (ITO2). Connected. Furthermore, thin film transistors (TFT1,
An additional capacitor (CADD) is connected between the source electrode of the TFT 2) and the previous gate signal line (G).

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG. In the example shown in FIG.
Although an additional capacitance (CADD) is formed between the gate signal lines (G) and the source electrodes in all stages, in the equivalent circuit of the example shown in FIG. 3, the capacitance between the common signal line (COM) and the source electrodes is increased. Are different in that a storage capacitor (CSTG) is formed in the storage capacitor. Although the present invention can be applied to both, in the former method, the gate signal line (G) pulse of all stages jumps into the pixel electrode (ITO1) via the additional capacitance (CADD), whereas the latter method. In the system, since there is no dive, better display is possible. 2 and 3 show an equivalent circuit of a vertical electric field type liquid crystal display panel. In FIGS. 2 and 3, AR is a display area. 2 and 3
Is a circuit diagram, which is drawn corresponding to the actual geometric arrangement. In the liquid crystal display panel 10 shown in FIGS. 2 and 3, the thin film transistors (T
The drain electrodes of FT) are connected to drain signal lines (D), respectively, and each drain signal line (D) is connected to a drain driver 130 that applies a gradation voltage to the liquid crystal of each pixel in the column direction. The gate electrode of the thin film transistor (TFT) in each pixel arranged in the row direction is
Each gate signal line (G) is connected to the gate signal line (G), and each gate signal line (G) is connected to the gate electrode of the thin film transistor (TFT) of each pixel in the row direction for one horizontal scanning time by a scanning drive voltage (positive bias voltage or negative (Bias voltage).

<Timing converter 100 shown in FIG.
Outline of Operation> Timing converter 100 is composed of one semiconductor integrated circuit device (LSI), and each display control signal of a clock signal, a display timing signal, a horizontal synchronization signal, and a vertical synchronization signal transmitted from the computer main body side. And display data (R, G, B)
Drain driver 130 and gate driver 14
0 is controlled and driven. The timing converter 100
When the display timing signal is input, the display timing signal is determined as a display start position, a start pulse (display data capture start signal) is output to the first drain driver 130 via a signal line, and the received simple signal is output. One column of display data is output to the drain driver 130 via the display data bus line. At this time, the timing converter 100 uses the display data latch clock (CL2) (hereinafter simply referred to as clock (CL2)), which is a display control signal for latching display data in the data latch circuit of each drain driver 130. Is output via a signal line. The display data from the main body computer is 6 bits, and is transferred in units of one pixel, that is, data of red (R), green (G), and blue (B) as one set for each unit time. The latch operation of the data latch circuit in the first drain driver 130 is controlled by the start pulse input to the first drain driver 130. When the latch operation of the data latch circuit in the first drain driver 130 ends, a start pulse is input from the first drain driver 130 to the second drain driver 130, and the second drain driver 130 The latch operation of the data latch circuit is controlled. Hereinafter, similarly, the latch operation of the data latch circuit in each drain driver 130 is controlled to prevent erroneous display data from being written to the data latch circuit. When the input of the display timing signal ends, or when a predetermined time passes after the input of the display timing signal, the timing converter 100 determines that one horizontal display data has ended, An output timing control clock (CL1) (hereinafter simply referred to as a clock (CL1)) which is a display control signal for outputting the display data stored in the data latch circuit to the drain signal line (D) of the liquid crystal display panel 10. ) Is output to each drain driver 130 via a signal line.

When the first display timing signal is input after the vertical synchronization signal is input, the timing converter 100 determines that the first display timing signal is the first display line and sends it to the gate driver 140 via the signal line. It outputs a frame start instruction signal. Further, the timing converter 100 uses a signal line to sequentially apply a positive bias voltage to each gate signal line (G) of the liquid crystal display panel 10 every horizontal scanning time based on the horizontal synchronization signal. A clock (CL3), which is a shift clock of one horizontal scanning time period, is output to the gate driver 140. Thereby, each gate signal line (G) of the liquid crystal display panel 10
A plurality of thin film transistors (TFTs) connected to
It conducts during the horizontal scanning time. By the above operation, an image is displayed on the liquid crystal display panel 10.

<Structure of power supply circuit 120 shown in FIG. 1> FIG.
FIG. 2 is a block diagram showing a configuration of a power supply circuit 120 shown in FIG. The power supply circuit 120 shown in FIG. 1 includes a positive voltage generation circuit 121, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, and a gate electrode voltage generation circuit 12.
4 Each of the positive voltage generation circuit 121 and the negative voltage generation circuit 122 is configured by a series resistance voltage dividing circuit,
The positive voltage generation circuit 121 is a positive five-level gray scale reference voltage (V "0 to V" 4), and the negative voltage generation circuit 122 is a negative five-level gray scale reference voltage (V "5 to V"). 9) is output.
The positive polarity gradation reference voltages (V "0 to V" 4) and the negative polarity gradation reference voltages (V "5 to V" 9) are supplied to the respective drain drivers 130. Further, each drain driver 130 is also supplied with an alternating signal (M) from the timing converter 100. The common electrode voltage generation circuit 123 receives a drive voltage applied to the common electrode (ITO2), and the gate electrode voltage generation circuit 124 receives a drive voltage (positive bias voltage and negative bias voltage) applied to the gate electrode of the thin film transistor (TFT). Generate.

<Method of AC Drive of Liquid Crystal Display Module shown in FIG. 1> Generally, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed.
As a result, an afterimage phenomenon is caused, and the life of the liquid crystal layer is shortened. In order to prevent this, in the liquid crystal display module, the voltage applied to the liquid crystal layer is converted into an alternating voltage at certain time intervals, that is, the pixel electrode (ITO1) is turned on based on the voltage applied to the common electrode (ITO2). Is changed to the positive voltage side / negative voltage side at regular time intervals. As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known. The common inversion method is a common electrode (ITO
In this method, the voltage applied to 2) and the voltage applied to the pixel electrode (ITO1) are alternately inverted to positive and negative. Further, the common symmetry method means that the voltage applied to the common electrode (ITO2) is kept constant, and the voltage applied to the pixel electrode (ITO1) is alternately set based on the voltage applied to the common electrode (ITO2). This is a method of inverting positive and negative. The common symmetric method has a disadvantage that the amplitude of the voltage applied to the pixel electrode (ITO1) is twice as large as that of the common inversion method, and a driver with a low withstand voltage cannot be used. The dot inversion method or the N-line inversion method, which is excellent in the above point, can be used.

The liquid crystal display module shown in FIG. 1 uses the above-described dot inversion method as a driving method. When the dot inversion method is used as a driving method of the liquid crystal display module, for example, in an odd line of an odd frame, a voltage is applied from the drain driver 130 to an odd drain signal line (D) to the common electrode (ITO2). The liquid crystal driving voltage (VCOM) applied to the common electrode (ITO2) is applied to the even-numbered drain signal line (D).
M) is applied with a positive liquid crystal drive voltage. Further, in the even-numbered lines of the odd-numbered frame, the drain driver 130 applies a positive liquid crystal drive voltage to the odd-numbered drain signal lines (D) and a negative liquid crystal drive voltage to the even-numbered drain signal lines (D). Is applied. In addition, the polarity of each line is inverted for each frame, that is, in the odd lines of the even frames, the drain driver 130 supplies the liquid crystal drive voltage of the positive polarity to the odd drain signal lines (D), and the even number lines. , A negative liquid crystal drive voltage is applied to the drain signal line (D). Further, in the even lines of the even frame, the drain driver 130 applies a negative liquid crystal drive voltage to the odd drain signal lines (D) and a positive liquid crystal drive voltage to the even drain signal lines (D). Is applied. By using this dot inversion method, the voltage applied to the adjacent drain signal line (D) has the opposite polarity, so that the common electrode (ITO2)
In addition, currents flowing through the gate electrodes of thin film transistors (TFTs) cancel each other out, and power consumption can be reduced. Further, since the current flowing through the common electrode (ITO2) is small and the voltage drop does not increase, the common electrode (I
The voltage level of TO2) is stabilized, and a decrease in display quality can be minimized.

<Structure of Drain Driver 130 shown in FIG. 1> FIG. 5 is a block diagram showing a schematic structure of an example of the drain driver 130 shown in FIG. As described above, the drain driver 130 shown in FIG. 1 is composed of a plurality of semiconductor integrated circuit devices (LSI), and the drain driver 130 shown in FIG. FIG. 3 is a diagram illustrating a configuration. In the figure, a positive polarity gradation voltage generation circuit 151a is
5, a positive-polarity quinary gradation reference voltage (V "0
To V ″ 4), generates a gradation voltage of 64 gradations of positive polarity, and outputs the voltage to the output circuit 15 via the voltage bus line 158a.
7 is output. The negative-polarity gradation voltage generation circuit 151b receives the negative-polarity 64 voltage based on the five-valued negative-polarity gradation reference voltage (V "5 to V" 9) input from the negative voltage generation circuit 122.
A grayscale voltage of the grayscale is generated and output to the output circuit 157 via the voltage bus line 158b. Also, the shift register circuit 15 in the control circuit 152 of the drain driver 130
3 generates a data capture signal for the input register circuit 154 based on the clock (CL2) input from the timing converter 100,
4 is output. The input register circuit 154 latches 6-bit display data for each color by the number of outputs in synchronization with the clock (CL2) input from the timing converter 100 based on the data capture signal output from the shift register circuit 153. I do. The storage register circuit 155 operates according to the clock (CL1) input from the timing converter 100.
The display data in 54 is latched. The display data captured by the storage register circuit 155 is input to the output circuit 157 via the level shift circuit 156.
The output circuit 157 outputs one gray scale voltage (one gray scale among 64 gray scales) corresponding to the display data based on the gray scale voltage of 64 gray scales of positive polarity or the gray scale voltage of 64 gray scales of negative polarity. (Adjustment voltage) is selected and output to each drain signal line (D).

FIG. 6 mainly shows the configuration of the output circuit 157.
FIG. 6 is a block diagram for describing a configuration of a drain driver shown in FIG. 5. 5, reference numeral 153 denotes a shift register circuit in the control circuit 152 shown in FIG. 5, 156 denotes a level shift circuit shown in FIG. 5, and a data latch unit 265 comprises an input register circuit 154 and a storage register shown in FIG. And a decoder section (grayscale voltage selection circuit) 261 and an amplifier circuit pair 26.
3. The switch unit (2) 264 for switching the output of the amplifier circuit pair 263 constitutes the output circuit 157 shown in FIG. Here, the switch unit (1) 262 and the switch unit (2) 264 are controlled based on the AC signal (M). Y1, Y2, Y3, Y4, Y5, and Y6 are the first, second, third, fourth, and fifth, respectively.
The sixth and sixth drain signal lines (D) are shown.
In the drain driver 130 illustrated in FIG. 6, the switch (1) 262 switches the data capture signal input to the data latch unit 265 (more specifically, the input register 154 illustrated in FIG. The display data is input to the adjacent data latch unit 265 for each color. The decoder unit 261 is provided with the positive polarity gray scale voltage generation circuit 15.
1a via the voltage bus line 158a, the display voltage output from each data latch unit 265 (more specifically, the storage register 155 shown in FIG. 5) out of the positive 64 grayscale voltages. A high voltage decoder circuit 278 for selecting a positive gradation voltage corresponding to the data;
The voltage bus line 1 from the negative gradation voltage generation circuit 151b
A low-voltage decoder circuit for selecting a negative gradation voltage corresponding to display data output from each data latch unit 265 from among 64 negative gradation voltages output via 58b. 279. The high voltage decoder circuit 278 and the low voltage decoder circuit 279 are provided for each adjacent data latch unit 265. The amplifier circuit pair 263 includes a high-voltage amplifier circuit 271 and a low-voltage amplifier circuit 272. The positive gray scale voltage generated by the high voltage decoder circuit 278 is input to the high voltage amplifier circuit 271, and the high voltage amplifier circuit 271 outputs a positive gray scale voltage. The low-voltage amplifier circuit 272 receives the negative gradation voltage generated by the low-voltage decoder circuit 279, and the low-voltage amplifier circuit 272 outputs the negative gradation voltage. In the dot inversion method, the gradation voltages of adjacent colors have opposite polarities, and the arrangement of the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 of the amplifier circuit pair 263 is such that the high-voltage amplifier circuit 271 → low Since the voltage amplifier circuit 272 → the high-voltage amplifier circuit 271 → the low-voltage amplifier circuit 272, the data latch unit 1 is switched by the switch unit (1) 262.
Switching the data capture signal input to 65,
The display data for each color is input to the adjacent data latch unit 265 for each color, and the output voltage output from the high-voltage amplifier circuit 271 or the low-voltage amplifier circuit 272 is switched to the switch unit (2) 264 accordingly. And output to a drain signal line (D) from which a gradation voltage for each color is output, for example, a first drain signal line (Y1) and a fourth drain signal line (Y4). It is possible to output a positive or negative gradation voltage to each drain signal line (D).

<Characteristic Configuration of Liquid Crystal Display Module of the Present Embodiment> FIG. 7 is a circuit diagram showing a circuit configuration of the positive gradation voltage generation circuit 151a or the negative gradation voltage generation circuit 151b shown in FIG. is there. In FIG. 7, V ′
0 to V'4 indicate five-valued gray scale reference voltages (V "0 to V" 4, V "5 to V" 9) of positive polarity or negative polarity. As shown in the figure, the grayscale voltage generation circuit has five grayscale reference voltages (V "0-V" 4, V "5
V ″ 9) is divided by a resistance element to generate a positive or negative 64 gray scale gray scale voltage. In this case, it is connected between each gray scale reference voltage. The resistance value of each resistance element is given a predetermined weight according to the relationship between the voltage applied to the liquid crystal layer and the transmittance.

FIG. 8 explains each gray scale voltage generated by the gray scale voltage generation circuit (positive gray scale voltage generation circuit 151a or negative gray scale voltage generation circuit 151b shown in FIG. 5) of the present embodiment. FIG. FIG. 8 is a graph in which the horizontal axis represents gradation (64 gradations) and the vertical axis represents each gradation voltage. In FIG. Gray scale voltage. As can be seen from FIG. 8, in the gray scale voltage generation circuit of the present embodiment, the potential difference between each gray scale voltage and the common voltage is reduced from 0 gray scale to 4 gray scale, and 4 gray scale to 8 gray scale. Up to the gradation, the potential difference between each gradation voltage and the common voltage is increased. That is, in the present embodiment, the line connecting the absolute value of the difference between each gradation voltage between the 0th gradation and the 8th gradation and the voltage of Vcom applied to the common electrode (ITO2) is the 0th gradation. And the absolute value of the difference between the grayscale voltage (which is equal to the grayscale reference voltage (V "0, V" 9)) and the voltage of Vcom, and the grayscale voltage of eight grayscales (this is (Equivalent to the voltage (V "1, V" 8)) and the absolute value of the difference between the voltages of Vcom and Vcom. As a result, in the present embodiment, the characteristics of the TFT substrate vary due to the influence of the manufacturing process and the like, and the pixel writing voltage becomes insufficient.
For example, even if a gray scale voltage of one gray scale is written to a pixel that should be a gray scale voltage of zero gray scale (black), the potential difference between gray scales of 0 gray scale and 1 gray scale is different. Because it is small, for example, 1
Even with the gradation voltage of the gradation, the pixel displays almost “black”. Therefore, in the present embodiment, the decrease in contrast is not noticeable, and variations in the characteristics of the TFT substrate can be absorbed by the influence of the manufacturing process and the like.

FIG. 9 is a graph plotting each gray scale voltage actually generated by the positive gray scale voltage generation circuit 151a of the present embodiment. In the above description, an embodiment in which the present invention is applied to a vertical electric field type liquid crystal display panel is described. However, the present invention is not limited to this, and the present invention is also applicable to a horizontal electric field type liquid crystal display panel. . Further, in each of the above embodiments, the embodiment in which the dot inversion method is applied as the driving method has been described, but the present invention is not limited to this, and a common symmetric method such as an N line inversion method, or It is also applicable to the common inversion method.
As described above, the invention made by the inventor has been specifically described based on the embodiment of the present invention. However, the present invention is not limited to the embodiment of the invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made in.

[0020]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, with respect to the voltage applied to the common electrode of each pixel, a gradation voltage corresponding to several gradations continuous with the gradation voltage having the largest potential difference has a smaller potential difference between gradations. Thus, it is possible to prevent the contrast of the display screen displayed on the liquid crystal display element from being lowered due to the characteristic variation of the liquid crystal display element.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module to which the present invention is applied.

FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel shown in FIG.

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel shown in FIG.

FIG. 4 is a block diagram showing a configuration of a power supply circuit shown in FIG.

FIG. 5 is a block diagram illustrating a schematic configuration of an example of a drain driver illustrated in FIG. 1;

FIG. 6 is a block diagram for explaining the configuration of the drain driver shown in FIG. 5, focusing on the configuration of the output circuit;

7 is a circuit diagram showing a circuit configuration of a positive polarity gray scale voltage generation circuit or a negative polarity gray scale voltage generation circuit shown in FIG. 5;

FIG. 8 is a schematic diagram for explaining each gray scale voltage generated by the gray scale voltage generation circuit of the present embodiment.

FIG. 9 is a graph in which each gray scale voltage actually generated by an example of the positive polarity gray scale voltage generation circuit of the present embodiment is plotted.

FIG. 10 is a schematic diagram for explaining each gradation voltage generated by a gradation voltage generation circuit in a conventional drain driver.

[Explanation of symbols]

10: liquid crystal display panel (TFT-LCD), 100: timing converter, 120: power supply circuit, 121, 12
2 ... voltage generation circuit, 123 ... common electrode voltage generation circuit,
124: gate electrode voltage generation circuit, 130: drain driver, 140: gate driver, 151a, 151b
... Grayscale voltage generation circuit, 152 ... Control circuit, 153 ... Shift register circuit, 154 ... Input register circuit, 155 ...
Storage register circuit, 156 ... level shift circuit,
157 output circuit, 158a, 158b voltage bus line, 261 decoder part, 262,264 switch part, 263 amplifier circuit pair, 265 data latch part
271, high-voltage amplifier circuit, 272, low-voltage amplifier circuit, 278, high-voltage decoder circuit, 279, low-voltage decoder circuit, D, drain signal line (video signal line or vertical signal line), G, gate Signal line (scanning signal line or horizontal signal line), ITO1 ... pixel electrode, ITO2 ... common electrode), COM ... common signal line, TFT ... thin film transistor, CLC ... liquid crystal capacity, CSTG ... storage capacity, CADD ... additional capacity, CN ... connector.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA31 NA53 NC03 NC11 NC21 NC65 ND04 ND06 ND58 5C006 AA02 AA22 AC02 AC24 AC25 AC28 AF42 AF44 BB16 BC03 BC06 BC11 BF03 BF04 BF34 BF49 EC05 FA20 FA54 FA56 5C080 AA30 BB30 FF09 JJ02 JJ05 KK02

Claims (4)

[Claims] A liquid crystal display element comprising: a plurality of pixels; a plurality of video signal lines for applying a gradation voltage corresponding to display data to one of liquid crystal layers of the plurality of pixels; And a video signal line driving means for supplying a gray scale voltage corresponding to display data to the video signal line. And a gradation voltage generating means for generating a gradation voltage of Vco.
m, among the gradation reference voltages input from the outside,
com is the gradation reference voltage having the largest potential difference from the voltage of
0, among the gray scale reference voltages input from the outside,
The potential reference voltage having the second largest potential difference from the voltage of V.com is V1.
When the grayscale voltages generated by the grayscale voltage generation means are plotted with the absolute value of the potential difference from the om voltage as the vertical axis, each grayscale between V0 grayscale voltage and V1 grayscale voltage is plotted. The line connecting the absolute value of the potential difference between the voltage and the voltage of Vcom is the absolute value of the potential difference between the grayscale voltage of V0 and the voltage of Vcom, the grayscale voltage of V1 and the Vco.
A liquid crystal display device, which is higher than a straight line connecting the voltage of m and the absolute value of the potential difference. 2. A liquid crystal display element comprising: a plurality of pixels; and a plurality of video signal lines for applying a gradation voltage corresponding to display data to one of liquid crystal layers of the plurality of pixels; And a video signal line driving means for supplying a gradation voltage corresponding to display data to the liquid crystal display device, wherein the video signal line driving means divides a positive gradation reference voltage inputted from the outside. Voltage generating means for generating a plurality of positive polarity gray scale voltages, and dividing a negative gray scale reference voltage inputted from outside,
A negative polarity gray scale voltage generating means for generating a plurality of negative polarity gray scale voltages, wherein a voltage applied to the other of the liquid crystal layers of each pixel is Vco
m, V0 denotes the grayscale reference voltage having the largest potential difference from the voltage of the Vcom among the positive and negative grayscale reference voltages input from the outside, and the positive and negative polarity input from the outside. Among the gradation reference voltages, a gradation reference voltage having the second largest potential difference from the voltage of the Vcom is denoted by V1, and the absolute value of a potential difference between each gradation voltage and the voltage of the Vcom is represented by the horizontal axis of the gradation. On the vertical axis, when the absolute value of the potential difference between each gradation voltage generated by the positive polarity gradation voltage generation means and the negative polarity gradation voltage generation means and the voltage of Vcom is plotted, The line connecting the absolute value of the potential difference between each gradation voltage between the V1 gradation voltage and the Vcom voltage is the gradation voltage of the V0 and the Vcom.
A liquid crystal display device which is higher than a straight line connecting an absolute value of a potential difference with a voltage of V.com and a potential difference between the gradation voltage of V1 and the voltage of Vcom. 3. A liquid crystal display element comprising: a plurality of pixels; and a plurality of video signal lines for applying a gradation voltage corresponding to display data to one of liquid crystal layers of the plurality of pixels; And a video signal line driving means for supplying a gray scale voltage corresponding to display data to the video signal line. And a gradation voltage generating means for generating a gradation voltage of Vco.
m, among the gradation reference voltages input from the outside,
com is the gradation reference voltage having the largest potential difference from the voltage of
0, among the gray scale reference voltages input from the outside,
When the grayscale reference voltage having the second largest potential difference from the voltage of V.com is V1, the grayscale voltage between the grayscale voltage of V0 and the grayscale voltage of V1 generated by the grayscale voltage generation means. Among them, the gray scale voltage having the largest potential difference between the gray scales between adjacent gray scales is located at an intermediate position between the gray scale voltage of V0 and the gray scale voltage of V1, and
A liquid crystal display device characterized in that gray-scale voltages of several gray-scale levels that are continuous with a gray-scale voltage of 0 have an inter-gray-scale potential difference smaller than the largest inter-gray-scale potential difference. 4. A liquid crystal display element comprising: a plurality of pixels; a plurality of video signal lines for applying a gray scale voltage corresponding to display data to one of the plurality of pixels; And a video signal line driving means for supplying a gray scale voltage corresponding to the liquid crystal display device, wherein the video signal line driving means divides a positive gray scale reference voltage inputted from the outside, A positive gradation voltage generating means for generating a plurality of positive gradation voltages; and dividing a negative gradation reference voltage inputted from outside,
A negative polarity gray scale voltage generating means for generating a plurality of negative polarity gray scale voltages, wherein a voltage applied to the other of the liquid crystal layers of each pixel is Vco
m, V0 denotes the grayscale reference voltage having the largest potential difference from the voltage of the Vcom among the positive and negative grayscale reference voltages input from the outside, and the positive and negative polarity input from the outside. When a gray-scale reference voltage having the second largest potential difference from the voltage of the Vcom among the gray-scale reference voltages is denoted by V1, the V generated by the gray-scale voltage generating means is V1.
Among the gray scale voltages between the gray scale voltage of 0 and the gray scale voltage of V1, the gray scale voltage having the largest potential difference between gray scales between adjacent gray scales is the gray scale voltage of V0 and the gray scale voltage of V1. The grayscale voltages of several grayscales that are located after the middle of the grayscale voltage and the grayscale voltage of V0 and that are continuous with the grayscale voltage of V0 have a potential difference between grayscales smaller than the largest potential difference between grayscales. Characteristic liquid crystal display device.