JP2001099898A - Test circuit for a/d and d/a converters - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a test circuit for A/D and D/A converters in which the linearity and differential linearity of the A/D and D/A converters can be inspected while reducing the scale. SOLUTION: Linearity and differential linearity are measured for the total characteristics of an A/D converter 12 and a D/A converter 13 through a through path 14 for connecting the digitally converted output of the A/D converter 12 directly with the input of the D/A converter 13. A decision is made whether an error is present in the measurement of linearity by means of an MSB inversion circuit 15 and an all bit inversion circuit 16 and then a decision is made whether an error is present in the measurement of differential linearity by means of a fixed amount adder/subtractor 17. According to the arrangement, linearity and differential linearity of the A/D converter 12 and the D/A converter 13 can be inspected accurately through a small scale test circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to A / D and D / A
The present invention relates to a test circuit for a converter, and more particularly to a test circuit for checking the linearity and differential linearity of an A / D and a D / A converter.

[0002]

2. Description of the Related Art A conventional A / D and D / A converter test circuit will be described with reference to the block diagram of FIG. In FIG. 6, reference numeral 1 denotes a semiconductor integrated circuit. The semiconductor integrated circuit 1 includes an (internal) A / D converter 2 and an (internal) D
/ A converter 3 is provided. The A / D converter 2 and the D / A converter 3 are each connected to an external A / D converter 4 of the semiconductor integrated circuit 1 whose accuracy is guaranteed.

A signal generation circuit 5 for generating a test signal input to the D / A converter 3 is provided in the semiconductor integrated circuit 1.
A digital conversion value output from the internal A / D converter 2 or the external A / D converter 4 and a signal generation circuit 5
Is provided with a comparator 6 for comparing the test signal with the test signal generated in step (1). The operation of the test circuit configured as described above will be described below.

First, in order to test the internal D / A converter 3, a digital test signal generated by the signal generation circuit 5 is input to the D / A converter 3. Then, this test signal is converted into an analog signal by the D / A converter 3, and the analog output after the D / A conversion is digitized again by the external A / D converter 4 whose accuracy is guaranteed. The comparator 6 compares the digital conversion signal of the external A / D converter 4 with the digital test signal of the expected value generated by the signal generation circuit 5, and compares the internal D / A
The quality of the characteristic of the converter 3 is determined.

Next, if the result of the determination is a good determination, the analog output of the internal D / A converter 3 is directly connected to the input of the internal A / D converter 2 externally, and one input of the comparator 6 is The output of the external A / D converter 4 is switched to the output of the internal A / D converter 2. With this circuit configuration, the digital test signal generated by the signal generation circuit 5 can be used for the internal D / A converter 3 which has already been determined to be good.
Is converted into an analog signal whose accuracy within the inspection standard range is guaranteed, and is converted again into a digital signal by the internal A / D converter 2. The comparator 6 has the internal A
The digital conversion signal of the / D converter 2 is compared with the digital test signal of the expected value generated by the signal generation circuit 5, and the characteristics obtained by integrating the characteristics of the internal A / D converter 2 and the characteristics of the internal D / A converter 3 are obtained. Measure and judge pass / fail.

[0006]

However, in the conventional test circuit configuration of the A / D converter 2 and the D / A converter 3, the signal for generating a test signal having a complicated circuit configuration is provided inside the semiconductor integrated circuit 1. Since the generation circuit 5 and the comparator 6 are required, the area of the semiconductor integrated circuit 1 is increased and the chip cost is increased. In addition, the A / D converter 4 whose accuracy is guaranteed is required outside, so that the inspection cost is increased. There was a problem of doing.

Further, since it is necessary to input a digital conversion signal of the external A / D converter 4 to the semiconductor integrated circuit 1, a terminal corresponding to the number of bits is required, so that the number of terminals of the semiconductor integrated circuit 1 increases, There is a problem that the use of the original terminals of the integrated circuit 1 is restricted. According to the present invention, such a test circuit for an A / D and a D / A converter can be simplified in a small scale and further easily converted to an A / D converter.
And to check the linearity and differential linearity of the D / A converter.

[0008]

A / D and D of the present invention
An A / D converter test circuit is a test circuit for an A / D and D / A converter built in a semiconductor integrated circuit, the digital integrated output of the A / D converter being output to the semiconductor integrated circuit. An MSB inverting circuit for inverting and outputting the most significant bit;
An all-bit inverting circuit for inverting and outputting all bits of a digital conversion output output from the converter;
A fixed amount adder / subtractor for adding or subtracting a fixed integer value to or from a digital conversion output output from the D converter, outputting the digital conversion output of the A / D converter, the output of the MSB inversion circuit, and the all bit inversion circuit And the output of the fixed-quantity adder / subtractor are switched so that the D /
A selector for inputting to the A / D converter, an analog test signal being input to the A / D converter, and a digital conversion output of the A / D converter being switched by the selector and input to the D / A converter; The characteristic of the A / D converter and the characteristic of the D / A converter can be determined by judging the analog conversion output from the A / D converter.

According to the present invention, small-scale simplification can be achieved,
A / D and D which can easily check the linearity and differential linearity of the A / D and D / A converters
/ A converter test circuit is obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a test circuit for an A / D and D / A converter built in a semiconductor integrated circuit, wherein the semiconductor integrated circuit has the A / D converter. An MSB inversion circuit for inverting and outputting the most significant bit of the digital conversion output output from the D converter, and an all-bit inversion circuit for inverting and outputting all bits of the digital conversion output output from the A / D converter A fixed amount adder / subtractor for adding or subtracting a fixed integer value to or from a digital conversion output output from the A / D converter, a digital conversion output of the A / D converter, an output of the MSB inverting circuit, A selector for switching between the output of the all-bit inverting circuit and the output of the fixed amount adder / subtractor and inputting the output to the D / A converter; The input to the A / D converter inputs the digital conversion output of the A / D converter to the D / A converter is switched by said selector, and
The characteristic of the A / D converter and that of the D / A converter can be determined by judging the analog conversion output output from the D / A converter. The linearity and differential linearity of the combined characteristics of the A / D converter and the D / A converter are measured by measuring the digital conversion output directly input to the D / A converter via the selector, and an erroneous determination on the linearity is made. Is determined by the measurement through the MSB inversion circuit and the all-bit inversion circuit, and the presence or absence of the erroneous determination on the differential linearity is determined by the measurement through the fixed amount adder / subtractor.

The invention according to claim 2 is the invention according to claim 1, wherein an arbitrary integer value is added to or subtracted from a digital conversion output output from the A / D converter and output to the semiconductor integrated circuit. An arbitrary amount adder / subtractor is provided, and the selector is switched to the output of the arbitrary amount adder / subtractor and can be input to the D / A converter. The characteristics of the A / D converter and the characteristics of the D / A converter It is possible to suppress erroneous determination that occurs in the test circuit of claim 1 when the characteristic has a special correlation.
It has the action of:

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a test circuit of an A / D and D / A converter according to an embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a semiconductor integrated circuit, in which an A / D converter 12 and a D / A converter 13 are provided.

The semiconductor integrated circuit 11 has a through path 14 for outputting a digital conversion output of the A / D converter 12 and an inverted and output most significant bit of the digital conversion output output from the A / D converter 12. MS
A B inversion circuit 15, an all bit inversion circuit 16 for inverting and outputting all bits of the digital conversion output output from the A / D converter 12, and a fixed integer value for the digital conversion output output from the A / D converter 12 Fixed-value adder / subtracter 17 that adds or subtracts an integer, and an arbitrary-value adder / subtractor 18 that adds or subtracts an arbitrary integer value to or from a digital conversion output output from the A / D converter 12 and outputs the result.
A digital conversion output directly output from the A / D converter 12 via the through path 14, an output of the MSB inversion circuit 15, an output of the all-bit inversion circuit 16, an output of the fixed amount adder / subtractor 17, A selector 19 for switching the output of the quantity adder / subtractor 18 and inputting it to the D / A converter 13
Is provided.

The A / D converter 12 and the D / A converter 13 are each connected to an external analog tester 20 of the semiconductor integrated circuit 11 whose accuracy is guaranteed. A signal input from the selector 19 to the D / A converter 13 is selected by a selection signal output from the analog tester 20. The operation of the test circuit configured as described above will be described below. [Measurement of Overall Linearity and Differential Linearity Matching Characteristics of A / D Converter 12 and Characteristics of D / A Converter 13] A selection signal of the through path 14 is input from the external analog tester 20 to the selector 19, and is fixed. Is input to the A / D converter 12.

Then, the test signal digitally converted by the A / D converter 12 is directly input to the D / A converter 13 via the through path 14 and the selector 19, and is again converted into an analog signal. 20. Analog tester 20
Compares the analog test signal input to the A / D converter 12 with the analog signal input from the D / A converter 13 to determine the characteristics of the A / D converter 12
The overall linearity and differential linearity that match the characteristics of the A / A converter 13 are measured.

However, in this method, the A / D converter 1
When the characteristic of the D / A converter 13 and the characteristic of the D / A converter 13 are symmetrical with respect to the ideal straight line as shown in FIG. For example, at the input α point, the characteristic of the A / D converter 12 has an error + βLSB with respect to the ideal straight line, and the characteristic of the D / A converter 13 has an error −βLSB with respect to the ideal straight line.
In the case of (β> inspection standard upper limit value), in the measurement via the through path 14, the characteristics are canceled each other and an error from the ideal straight line is output as 0LSB, so that there is a problem that a non-defective product is determined. [Determination of presence / absence of erroneous determination of linearity by the above measurement method] Selection of MSB Inverting Circuit 15 by Selector 19 Therefore, when a non-defective product is determined in the above measurement, the external analog tester 20 further sends MSB to the selector 19.
The selection signal of the inversion circuit 15 is input, and the MSB inversion circuit 15
Is measured again with the circuit configuration selected by the selector 19.

If the result of the re-measurement is a good determination, it is determined that the measurement via the through path 14 is not an erroneous determination. On the other hand, if the determination is a bad determination, the measurement via the through path 14 is an erroneous determination. It is determined that This is because the characteristic is canceled when the measurement is performed via the through path 14 by inverting the MSB of the output of the A / D converter 12, shifting the level by 出力 full scale, and inputting it to the D / A converter 13. Is no longer canceled and is detected as defective.

However, in the above measurement, A /
As shown in FIG. 3, the characteristic of the D converter 12 and the characteristic of the D / A converter 13 are
An erroneous determination occurs in the special case of matching by full-scale shift. 2. Selection of all-bit inversion circuit 16 by selector 19 In order to further eliminate the case where this erroneous determination occurs, a selection signal of all-bit inversion circuit 16 is output from external analog tester 20 to selector 19, and all-bit inversion circuit 16 Is measured again in the circuit configuration selected by the selector 19 again.

If the result of the re-remeasurement is a good judgment, it is judged that the measurement via the through path 14 is not an erroneous judgment, whereas if the judgment is a bad judgment, the measurement via the previous through path 14 is an erroneous judgment. It is determined that there is. According to the above process, a case where an erroneous determination occurs in the embodiment of the present invention is shown in FIG.
As shown in FIG. 7, the characteristics of the A / D converter 12 and the characteristics of the D / A converter 13 are symmetrical with respect to the ideal straight line, coincide with each other by 1/2 full scale shift, and are symmetrical with respect to 1/2 full scale. Limited to cases. In other words, this case is a very special case in which the characteristics of the A / D converter 12 and the characteristics of the D / A converter 13 are as follows.

A. In the A / D converter 12, the characteristic from zero scale to 1/2 full scale is 1/4
Symmetry about full scale point b. In the D / A converter 13, the characteristic from zero scale to 1/2 full scale is symmetric with respect to the 1/4 full scale point. C. In the A / D converter 12, the characteristic from 1/2 full scale to full scale is symmetric with respect to the point of 3/4 full scale. D. In the D / A converter 13, the characteristic from 1/2 full scale to full scale is symmetric with respect to the point of 3/4 full scale. E. In the A / D converter 12, the characteristic from zero scale to full scale is symmetric with respect to a point of 1/2 full scale. F. In the D / A converter 13, the characteristic from zero scale to full scale is symmetric with respect to the point of 1/2 full scale. G. 2. In the above 1 to 6, the characteristics of the A / D converter 12 and the characteristics of the D / A converter 13 are symmetric with respect to an ideal straight line. Selection of Arbitrary Adder / Subtractor 18 by Selector 19 A special A / D converter 12 and D which need to determine the presence or absence of erroneous determination even in the special case (correlation) described above.
Only when the A / A converter 13 is used, the optional analog adder / subtracter 1
8, the linearity is measured in a circuit configuration in which the selector 19 selects the output of the arbitrary amount adder / subtractor 18.

The linearity is measured again by a circuit configuration in which the characteristic of the A / D converter 12 and the characteristic of the D / A converter 13 are shifted by an arbitrary value by the arbitrary amount adder / subtractor 18, thereby obtaining
The case where the characteristic of the A / D converter 12 and the characteristic of the D / A converter 13 shown in FIG. 4 have a special correlation can be further limited. [Determination of presence / absence of erroneous determination on differential linearity by the above-described measurement method] Next, presence / absence of erroneous determination on differential linearity characteristics is determined by the following method.

An external analog tester 20 selects a selector 19
The selector 19 receives the selection signal of the fixed amount adder / subtractor 17 and switches the selector 19 to select the output of the fixed amount adder / subtractor 17.
The differential linearity is measured in the same manner as when the measurement is performed via the through path 14. Thereby, for example, as shown in FIG. 5, {1/2 full scale (FS) -1 LSB} and 1
Defective products whose differential linearity is not maintained between / 1/2 full scale and between (1/2 full scale + 1 LSB) and (1/2 full scale + 2 LSB) depend on the characteristics of the A / D converter 12. Since the characteristics of the D / A converter 13 are symmetrical with respect to the ideal straight line, in a case where the determination is good in the measurement via the through path 14, the characteristics of the A / D converter 12 and the D / A converter 1
By shifting the characteristic of No. 3 by a fixed value, the presence / absence of erroneous determination can be detected.

As described above, the linearity and the differential linearity are measured by the measurement via the through path 14, and the presence / absence of an erroneous determination on the linearity is determined by the MSB inverting circuit 15, the all-bit inverting circuit 16, and the arbitrary amount adder / subtracter 18 (Special case), and the presence / absence of erroneous determination on the differential linearity is determined by measurement through the fixed-quantity adder / subtracter 17, thereby providing a small-scale test circuit with a simple circuit configuration. In addition, the linearity and differential linearity of the A / D converter 12 and the D / A converter 13 can be accurately inspected, the increase in the area of the semiconductor integrated circuit 11 can be suppressed, and the chip cost can be reduced. Further, inspection costs can be reduced.

Further, as compared with the conventional example, the number of terminals of the semiconductor integrated circuit 11 required for the test can be reduced, the restriction on the use of the original terminals of the semiconductor integrated circuit 11 can be eased, and the A / D can be reduced by the restriction on the number of terminals. Even when digital values cannot be directly controlled or observed externally during the test of converter 12 and D / A converter 13, A / D converter 1
The linearity and differential linearity of the 2 and D / A converters 13 can be accurately inspected.

Further, by setting an arbitrary amount of addition / subtraction using the arbitrary amount adder / subtractor 18 from outside, it is possible to further improve the accuracy of detection of erroneous determination of linearity.

[0026]

As described above, according to the present invention, the linearity and differential linearity of the A / D and D / A converters can be easily and accurately inspected with a small-scale test circuit. The effect is obtained.

[Brief description of the drawings]

FIG. 1 shows A / D and D / in an embodiment of the present invention.
It is a block diagram of a test circuit of A converter.

FIG. 2 is a characteristic diagram of the A / D and D / A converters in which an erroneous determination occurs at the time of measurement via a through path in the test circuit of the A / D and D / A converters.

FIG. 3 is a characteristic diagram of the A / D and D / A converters in which an erroneous determination occurs at the time of measurement via a through path and an MSB inversion circuit in the A / D and D / A converter test circuit.

FIG. 4 shows an A / D in which an erroneous determination occurs in a test circuit of the A / D and D / A converters at the time of measurement through a through path, an MSB inversion circuit, and an all-bit inversion circuit.
FIG. 4 is a characteristic diagram of a D / A converter.

FIG. 5 is a characteristic diagram of an A / D and D / A converter in which an erroneous determination occurs when differential linearity is measured via a through path in a test circuit of the A / D and D / A converter.

FIG. 6 is a block diagram of a test circuit of a conventional A / D and D / A converter.

[Explanation of symbols]

 Reference Signs List 11 semiconductor integrated circuit 12 A / D converter 13 D / A converter 14 through path 15 MSB inverting circuit 16 all bit inverting circuit 17 fixed amount adder / subtractor 18 arbitrary amount adder / subtractor 19 selector 20 external analog tester

Claims (2)

[Claims] 1. A test circuit for an A / D and D / A converter built in a semiconductor integrated circuit, wherein a most significant bit of a digital conversion output output from the A / D converter is provided to the semiconductor integrated circuit. An MSB inverting circuit for inverting and outputting; an all-bit inverting circuit for inverting and outputting all bits of a digital conversion output output from the A / D converter; and a digital conversion output output from the A / D converter. A fixed amount adder / subtracter for adding or subtracting a fixed integer value and outputting the result; a digital conversion output of the A / D converter;
The output of the SB inverting circuit, the output of the all bit inverting circuit, and the output of the fixed amount adder / subtractor are switched to form the D / A
A selector for inputting the analog test signal to the A / D converter;
The digital conversion output of the A / D converter is switched by the selector and input to the D / A converter.
A / D converter characterized in that it is possible to determine whether the characteristics of the A / D converter and the D / A converter are good or not by determining the analog conversion output output from the A converter.
And a D / A converter test circuit. 2. The semiconductor integrated circuit further comprises an arbitrary amount adder / subtractor for adding or subtracting an arbitrary integer value to or from a digital conversion output output from an A / D converter, and the selector includes an output of the arbitrary amount adder / subtractor. Switch to D
2. A test circuit for an A / D and D / A converter according to claim 1, wherein the test circuit can be inputted to a / A converter.