JP2001094983A - Data transmission method and data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To multiplex a plurality of digital video signals with a means that is comparatively easily prepared, in such a way that they can surely be reproduced at a receiver side and to transmit the multiplexed video signal through 8B/10B conversion. SOLUTION: Each of unit blocks for plural digital video signals is written respectively in each of plural memory means, the unit blocks written respectively to each of the plural memory means are read sequentially as word stream data, 8B/10B conversion processing is applied to the plural word stream data read respectively from the plural memory means to form 20-bit word stream data. A transmission speed conversion processing is applied to the 20-bit word stream data, an attached word data group, including 20-bit word synchronous data with a preset code given thereto, is inserted to the processed 20-bit word stream data to form composite 20-bit word stream data. The composite 20-bit word steam data are converted into serial data, and these are transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The invention described in the claims of the present application obtains 20-bit word string data by subjecting a digital signal to 8-bit / 10-bit conversion processing, and obtains the obtained 20-bit word string data. A data transmission method for forming composite 20-bit word string data by inserting an additional word data group containing word synchronization data into the Related to the device.

[0002]

2. Description of the Related Art In the field of transmission of digital data containing information data representing various kinds of signal information such as image information, the digital data is converted into serial data, an electric signal based on the serial data is obtained, and the signal is coaxial. A system for transmitting data through a transmission line formed using a cable or twisted pair line,
Alternatively, digital data is converted into serial data, and the serial data is converted into an optical signal, and the optical
A system for transmitting data through a transmission line formed using fibers has been put to practical use.

As one of such digital data transmission systems, a fiber channel system (Fibr
e Channel System) is known. Digital data handled under a digital data transmission system such as this fiber channel system is converted on the transmission side into, for example, 8 bits / 10 bits (8B / 8 bits) where every 8 bits is converted to 10 bits.
10B conversion) to obtain 10-bit word string data. And what is actually transmitted is 8B / 10B
The 10-bit word string data formed by the conversion is converted into serial data obtained by further performing a parallel / serial conversion (P / S conversion) process.

On the other hand, on the receiving side, serial / parallel conversion (S / P conversion) is performed on received serial data.
Conversion) processing is performed to form 10-bit word string data, and the 10-bit word string data is subjected to 10-bit / 8-bit conversion (10B / 8B conversion) in which conversion is performed for every 10 bits to 8 bits. Is done. And 10B /
The original digital data is reproduced from the word string data formed by performing the 8B conversion.

[0005] In transmitting such digital data, in order to make the 10B / 8B conversion performed on the reception side proper, it is necessary to accurately grasp each of the 10 bits formed by the 8B / 10B conversion on the transmission side. Therefore, it is assumed that 10-bit word string data converted into serial data and transmitted is appropriately inserted with word synchronization data on the transmission side. The word synchronization data is a word data having a 10-bit structure, but has a specific code which is not used as the word data having a 10-bit structure for transmitting information.

As described above, data transmission in which digital data to be transmitted is subjected to 8B / 10B conversion is recognized as providing good transmission quality.

On the other hand, in the field of video signals, digitization has been attempted from the viewpoint of diversifying transmitted information and improving the quality of reproduced images. High Definition Television (HDT
V) Systems and the like have been proposed. A digital video signal such as a digitized video signal under the HDTV system follows a data format as shown in FIG. 21, for example.

The data format of the digital video signal shown in FIG. 21 is a brightness signal data sequence (Y data sequence) representing a brightness signal component in the video signal as shown in FIG. in the as shown, comprises from the color difference signal data sequence representing the color difference signal components (P _B / P _R data sequence) in the video signal, the word data forming the respective Y data sequence and P _B / P _R data sequence Each has a 10-bit configuration. That is, each of the Y data sequence and P _B / P _R data sequence is a 10-bit quantized digital signal. FIG. 21A shows a line blanking period in each line period in the Y data series and a portion corresponding to a part of the video data period before and after the line blanking period. FIG. It has been shown a portion corresponding to a portion of the video data period in the line blanking period and before and after in each line period in the P _B / P _R data sequence.

In the Y data series, each video data period
Immediately before the portions corresponding to the intervening portions, each has a 10-bit configuration.
4 words (3FF (Y), 000 (Y), 000)
(Y), XYZ (Y); 3FF and 000 are displayed in hexadecimal
XYZ is hexadecimal display.
Variable value information, field identification, field
Identification of timing periods and timing reference code data
Data (SAV, EAV). (Y) is Y
Represents a word in the data series. )
Timing reference code data (SAV: Start of Ac)
tive Video) and each video data period
Immediately after the corresponding parts, each has a 10-bit configuration.
4 words (3FF (Y), 000 (Y), 000)
(Y), XYZ (Y))
Data (EAV: End of Active Video) is provided.
Similarly, P_B/ P_REach video, even in the data series
Immediately before the portion corresponding to the data period, each has 10 bits
4 words (3FF (C), 000 (C),
000 (C), XYZ (C); (C) is P_B/ P_RDay
Indicates that it is a word in the data series. ) Consisting of
AV is provided and corresponds to each video data period.
Immediately after the part, 4 words each consisting of 10 bits
(3FF (C), 000 (C), 000 (C), XYZ
(C)) is provided. Of course, Y data system
Each of the EAV and SAV in the column is
Is arranged in a portion corresponding to each line blanking period,
Also, P_B/ P _RHusband of EAV and SAV in data series
Are P_B/ P_REach line blank in the data series
Is allocated to the portion corresponding to the switching period.

[0010] In such Y data sequence and P _B / P _R data sequence is transmitted, Y data sequence and P _B /
The P _R data sequence, word multiplexing process at Moto the portion corresponding to the line blanking period, each of EAV and SAV are disposed has been made to the synchronization is performed, the word multiple data series as shown in FIG. 22 , Formed as a 10-bit quantized digital signal. In the word multiplexed data series, immediately before a portion corresponding to each video data period, 8 words (3FF) each having a 10-bit configuration are used.
(C), 3FF (Y), 000 (C), 000 (Y),
000 (C), 000 (Y), XYZ (C), XYZ
(Y)) are arranged, and 10 bits are formed immediately after a portion corresponding to each video data period.
Words (3FF (C), 3FF (Y), 000 (C),
000 (Y), 000 (C), 000 (Y), XYZ
(C), XYZ (Y)) are provided.

The digital video signal in the form of a word multiplex data sequence is converted from parallel data to serial data, subjected to scrambling, and transmitted in the form of a transmission signal that is converted into an electric signal or an optical signal. .

In the scrambling process in such a case, the serial data to be processed is represented by a polynomial, which is sequentially divided by a primitive polynomial, for example, a ninth-order primitive polynomial: X ⁹ + X ⁴ +1. The quotient resulting from the operation is obtained as transmission data, the mark ratio of transmission data (the ratio of "0" and "1") is statistically reduced to 1/2 on average, and the transmission data is expressed by a primitive polynomial. This is a process for performing encryption. In actual transmission of transmission data, for example, instead of directly transmitting a quotient obtained by division by a ninth-order primitive polynomial: X ⁹ + X ⁴ +1, the quotient is further divided by an expression: X + 1. The transmission data is data (polarity-free data) in which it and the inverted data have the same information.

On the receiving side receiving the transmission data, the received transmission data is multiplied by the equation: X + 1, and further, is multiplied by a ninth-order primitive polynomial: X ⁹ + X ⁴ +1 to perform a descrambling process. Plays back serial data.

[0014]

BRIEF Problem to be Solved] In the digital video signal in the form of such Y data sequence and P _B / P _R data sequence, not Upon its transmission, for a single digital video signal only, a plurality If the digital video signal can be multiplexed and transmitted so that it can be reliably reproduced on the receiving side, the digital video signal can be used efficiently, and the range of use of the digital video signal can be expanded. Will be. Efficient use of digital video signals, expansion of the range of use of digital video signals, and the like, for example, lead to further development of technology in the field of business or household electronic devices. Therefore, from such a viewpoint, it is desired to provide a method of multiplexing and transmitting a plurality of digital video signals so that the digital video signals can be reliably reproduced on the receiving side by means that can be prepared relatively easily.

However, in the prior art, the aforementioned Y
For digital video signal as the digital video signal in the form of data sequences and P _B / P _R data sequence,
There is no concrete example that realizes a transmission system capable of multiplexing and transmitting a plurality of the multiplexes so that the plurality of multiplexes can be reliably reproduced on the receiving side. Further, there is no document or the like describing a technique relating to a transmission system capable of multiplexing and transmitting such a plurality of digital video signals so that the digital video signals can be reliably reproduced on the receiving side.

[0016] In view of the above, the invention described in the claims of the present application provides, for example, the aforementioned Y data series and P data.
For digital video signal as the digital video signal in the form of a _B / P _R data sequence, relatively easily with a means that can adjust the data transmission method及capable of transmitting the plurality reproducibly by multiplexing Provided is a data transmission device used for the implementation.

[0017]

According to a first aspect of the present invention, there is provided a data transmission method comprising the steps of: Each of the unit sections is written into a plurality of memory means, respectively, and the unit sections written into each of the plurality of memory means are sequentially read as word string data. A 10-bit conversion process is performed and 20-bit word string data is formed.
A transmission rate conversion process is performed on the 0-bit word string data, and an additional word data group including 20-bit word synchronization data to which a predetermined code is given is inserted at a predetermined word interval, and It forms 20-bit word string data, converts the composite 20-bit word string data into serial data, and transmits the serial data for transmission.

According to a seventh aspect of the present invention, there is provided a data transmission apparatus for writing a predetermined unit section of each of a plurality of digital video signals into a plurality of memory means. The unit divisions written in each of the plurality of memory means are sequentially read as word string data, and the plurality of word string data read from each of the plurality of memory means are subjected to an 8-bit / 10-bit conversion process and the 20-bit word string data are processed. And a transmission rate conversion process for the 20-bit word string data obtained from the 20-bit word string data formation means, and a predetermined code interval at predetermined word intervals. The additional word data group including the 20-bit word synchronization data given by Speed conversion / data insertion means for forming composite 20-bit word string data, and converts the composite 20-bit word string data obtained from the speed conversion / data insertion means into serial data and transmits the serial data. And data transmission means for transmitting the data.

In the data transmission method according to any one of the first to sixth aspects of the present invention, a plurality of memories for a plurality of digital video signals are provided. The word string data obtained by writing to the means and reading from a plurality of memory means is synthesized, and is formed by subjecting it to 8B / 10B conversion processing and transmission rate conversion processing. The composite 20-bit word string data transmitted to be converted into data and transmitted includes 20-bit word synchronization data provided with a predetermined code. Such 20-bit word synchronization data is selected, for example, from a plurality of 20-bit word data to which a predetermined code is assigned, which is connected in a specific arrangement, and a plurality of word strings obtained from a plurality of memory means. 8B /
Only when the additional word data group is inserted into the 20-bit word data formed by performing the 10B conversion process, it appears in the composite 20-bit word string data.

The 20-bit word synchronizing data provided with the predetermined code and included in the composite 20-bit word string data is transmitted to the receiving side that receives serial data based on the composite 20-bit word string data including the data. The composite 20-bit word string data obtained based on the received serial data is properly detected as word synchronization data required for processing for reproducing a plurality of digital video signals. You. Also, 2 included in the composite 20-bit word string data
Since the 0-bit word string data is obtained through the 8B / 10B conversion processing, good transmission quality is provided. Therefore, on the receiving side, the data synchronization state required for the reproduction processing of a plurality of digital video signals based on the composite 20-bit word string data received while obtaining good transmission quality is established. , A state that can be obtained reliably.

In the data transmission method according to any one of the first to sixth aspects of the present invention, a predetermined code is provided. Conversion of composite 20-bit word string data to which bit word synchronization data is added into serial data, transmission of the converted serial data, and
The receiving side receives the serial data, converts the received serial data into composite 20-bit word string data, and uses, for example, a transmission circuit device used for transmitting and receiving a digital video signal under an HDTV system. You can do it. Therefore, according to the data transmission method according to any one of the first to sixth aspects of the present invention,
A digital video signal can be multiplexed and transmitted by performing 8B / 10B conversion so that it can be reproduced reliably on the receiving side by means that can be prepared relatively easily.

Further, in the data transmission apparatus according to the invention described in claim 7 of the present application, the data transmission means converts the plurality of serial data transmitted to be transmitted after being converted into serial data. 8B / 10B conversion processing and transmission rate conversion are performed on a composite of word string data obtained by writing the digital video signal into a plurality of memory units and reading out from the plurality of memory units. The composite 20-bit word string data formed by the processing includes 20-bit word synchronization data provided with a predetermined code. Such 20-bit word synchronization data is, for example,
A plurality of 20-bit word data to which a predetermined code is assigned is selected to be continuous with a specific arrangement, and a plurality of word string data obtained from a plurality of memory means are combined into an 8B / 10B conversion. Only by inserting the additional word data group into the 20-bit word data formed by the processing,
It appears in the 0-bit word string data.

The 20-bit word synchronizing data provided with the predetermined code and included in the composite 20-bit word string data is transmitted to the receiving side receiving the serial data based on the composite 20-bit word string data including the same. The composite 20-bit word string data obtained based on the received serial data is properly detected as word synchronization data required for processing for reproducing a plurality of digital video signals. You. Also, 2 included in the composite 20-bit word string data
Since the 0-bit word string data is obtained through the 8B / 10B conversion processing, good transmission quality is provided. Therefore, on the receiving side, the data synchronization state required for the reproduction processing of a plurality of digital video signals based on the composite 20-bit word string data received while obtaining good transmission quality is established. , A state that can be obtained reliably.

According to the data transmission apparatus according to the present invention as set forth in claim 7 of the present application, a composite in which a 20-bit word synchronous data to which a predetermined code is given is added. The conversion of the 20-bit word string data into serial data, the transmission of the converted serial data, and the reception side receiving the serial data, converting the received serial data into composite 20-bit word string data, For example, the transmission can be performed using a transmission circuit device used for transmission and reception of a digital video signal under an HDTV system. And 8B /
The transmission can be performed after performing the 10B conversion.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a data transmission method according to the present invention described in claims 1, 2, 3, 4 or 6 of the present invention. An example of the data transmission device according to the invention described in claim 7 in the range of FIG.

In the example shown in FIG. 1, four channels of digital video signals DVS1, DVS2, DVS3
And DVS4 are supplied to the compound word string data forming unit 11. 4-channel digital video signal DVS1
DVS4 Each of the, for example, multiplexing processing in the Y data sequence and P _B / P _R data sequence shown in A and B of Figure 21 is formed is subjected, word multiple data format as shown in FIG. 22 Is obtained by serializing and scrambling the 10-bit quantized digital signal in the form of (1), and the bit transmission rate is set to, for example, serial data at 270 Mbps.

In the composite word string data forming section 11, four-channel digital video signals DVS1 to DVS are output.
S4 is supplied to the switches 12, 13, 14 and 15, respectively. A control signal CSF from the control signal forming unit 17 is also supplied to each of the switches 12 to 15.

The control signal forming section 17 includes a frame synchronizing signal SSF and a horizontal synchronizing signal S synchronized with the frame period for each of the digital video signals DVS1 to DVS4.
H, a vertical synchronizing signal SV, a clock pulse signal CA having a frequency of 270 MHz, and a clock pulse signal CB having a frequency of 74.25 MHz are supplied. Then, the control signal CSF obtained from the control signal forming unit 17 is based on the frame synchronization signal SSF and the digital video signal DV.
This is synchronized with the frame period of each of S1 to DVS4.

The switch 12 has the memory sections 20A and 20B, the switch 13 has the memory sections 21A and 21B, the switch 14 has the memory sections 22A and 22B, and the switch 15 has the memory sections 22A and 22B. Is connected to the memory unit 23A and the memory unit 23B, respectively.

The switch 12, to which the digital video signal DVS1 is supplied, operates to supply the digital video signal DVS1 to the memory unit 20A and the memory unit 20B alternately, for example, for each frame period in response to the control signal CSF. To distribute the odd frame period portion and the even frame period portion of the digital video signal DVS1 to the memory units 20A and 20B, respectively. Similarly, the switch 13 to which the digital video signal DVS2 is supplied switches the digital video signal DVS2 in accordance with the control signal CSF.
For example, an operation of alternately supplying each frame period portion to the memory portions 21A and 21B is performed, and the odd frame period portion and the even frame period portion of the digital video signal DVS2 are distributed to the memory portions 21A and 21B, respectively. The switch 14 to which the digital video signal DVS3 is supplied is supplied with the digital video signal DVS3 in response to the control signal CSF, for example, alternately supplying the digital video signal DVS3 to the memory unit 22A and the memory unit 22B for each frame period. To supply the odd frame period part and the even frame period part of the digital video signal DVS3 to the memory units 22A and 22B, respectively. Further, the switch 15 to which the digital video signal DVS4 is supplied is switched according to the control signal CSF. The digital video signal DVS4 is, for example, Each arm period portion and the memory portion 23A and the memory unit 23B performs an operation of alternately supplying, distributing supplies an odd frame period portion and the even frame period portion of the digital video signal DVS4 respectively memory unit 23A and 23B.

The memory units 20A, 21A, 22A and 23
A is supplied with the write control signal QWO from the control signal forming unit 17, and the memory units 20B, 21B, 2
The write control signal QWE from the control signal forming unit 17 is supplied to each of 2B and 23B. Write control signal QWO
Sets the frequency to 270 based on the clock pulse signal CA.
MHz, and is formed so as to synchronize with the odd frame period portion of each of the digital video signals DVS1 to DVS4. The write control signal QWE also has a frequency of 270 MHz based on the clock pulse signal CA.
The digital video signals DVS1 to DVS4 are formed so as to be synchronized with even frame period portions.

As a result, the digital video signal DVS1
Are sequentially written to the memory unit 20A in response to the write control signal QWO, and each even frame period portion in the digital video signal DVS1 is sequentially written to the memory unit 20B in response to the write control signal QWE. Written. Similarly, each odd frame period portion of digital video signal DVS2 is sequentially written to memory portion 21A in response to write control signal QWO, and each even frame period portion of digital video signal DVS2 is written to memory portion 21B. Control signal Q
The digital video signal DV is sequentially written according to the WE.
Each odd frame period portion in S3 is stored in the memory unit 22.
A is sequentially written in response to the write control signal QWO, and each even-numbered frame period portion of the digital video signal DVS3 is stored in the memory section 22B by the write control signal QWE.
Are sequentially written in accordance with the write control signal QWO in the digital video signal DVS4, and each even frame period in the digital video signal DVS4 is sequentially written in the memory unit 23A in accordance with the write control signal QWO. Write control signal Q to memory unit 23B
The data is sequentially written according to WE.

Thus, as shown in FIG. 2A, writing in the memory units 20A to 23A and
To 23B correspond to the digital video signal DV.
This is performed alternately for each period 1SF corresponding to one frame period for each of S1 to DVS4. In addition,
In FIG. 2, an arrow t indicates a lapse of time.

The read control signals QR1O and QR1E from the control signal forming unit 17 are supplied to the memory units 20A and 20B, respectively. Similarly, the memory units 21A and 21B
The read control signals QR2O and QR2E from the control signal forming unit 17 are supplied to the memory units 22A and 22B, respectively.
, Read control signals QR3O and QR3E from the control signal forming unit 17 are supplied to the memory units 23A and 23B, respectively.
R4O and QR4E are supplied respectively.

The read control signals QR1O, QR1E, QR2O, QR2E, QR3 obtained from the control signal forming section 17
Each of O, QR3E, QR4O and QR4E is formed based on the clock pulse signal CA and has a frequency of 27.
0 MHz / 2 = 135 MHz, and
The transmission state from the control signal forming unit 17 is controlled by the horizontal synchronization signal SH and the vertical synchronization signal SV.

Then, the odd frame period portions and the even frame period portions of the digital video signal DVS1 written in the memory sections 20A and 20B are read out in accordance with the read control signals QR1O and QR1E, respectively.
The odd frame period portion and the even frame period portion of the digital video signal DVS2 written in the memory portions 21A and 21B are read out according to the read control signals QR2O and QR2E, respectively, and the memory portions 22A and 2B are read out.
2B, the odd frame period portion and the even frame period portion of the digital video signal DVS3 respectively read in accordance with the read control signals QR3O and QR3E, respectively, and further written into the memory units 23A and 23B. Each odd frame period portion and each even frame period portion of the video signal DVS4 are read in accordance with the read control signals QR4O and QR4E, respectively.

At this time, the memory units 20A to 23A and 2
As shown in FIG. 2B, reading from memory units 20A to 23A and reading from memory units 2A to 23B are performed.
0B to 23B corresponds to the digital video signal D
It is performed alternately for a period 1SF corresponding to one frame period for each of VS1 to DVS4.

Each of the odd frame period portion and the even frame period portion of the digital video signal DVS1 read out from the memory units 20A and 20B in accordance with the read control signals QR1O and QR1E, respectively, is an 8-bit word string having a word transmission rate of 135 MBps. Read output D1O (8) from the memory units 20A and 20B, each being 8-bit word string data.
And D1E (8) are obtained respectively. Similarly, the memory unit 2
1A and 21B to read control signals QR2O and QR, respectively.
Digital video signal DVS2 read in accordance with 2E
Each of the odd frame period portion and each even frame period portion has a word transmission rate of 135 MBps.
Readout outputs D2O (8) and D2E (8), each of which is formed as 8-bit word string data, are obtained from the memory sections 21A and 21B to form bit word string data, respectively, and are stored in the memory sections 22A and 22B. Each of the odd frame period portions and the even frame period portions of the digital video signal DVS3 read out in accordance with the read control signals QR3O and QR3E respectively has a word transmission rate of 1
It is assumed that 8-bit word string data of 35 MBps is formed, and a read output D3O (8) is output from the memory units 22A and 22B as 8-bit word string data.
And D3E (8) are obtained, respectively, and the memory unit 23
A and 23B read control signals QR4O and QR4, respectively.
Each of the odd frame period portion and each even frame period portion of the digital video signal DVS4 read in accordance with E has a word transmission rate of 135 MBps8.
Readout outputs D4O (8) and D4E (8), each of which is formed as 8-bit word string data, are obtained from the memory sections 23A and 23B, which form bit word string data.

Then, the read outputs D1O (8) to D4O (8) obtained from the memory units 20A to 23A are collected in the data collecting unit 25A. Also, the memory units 20B-
Readouts D1E (8) to D4E obtained respectively from B23B
(8) is collected in the data collection unit 25B.

The memory unit 20 in the data collection unit 25A
Readout outputs D1O (8) to D4O (8) from A to 23A
Are set according to the respective transmission states of the read control signals QR1O to QR4O from the control signal forming unit 17. Then, in the data collection unit 25A, the memory unit 2
Read outputs D1O (8) to D4O from 0A to 23A
The word transmission rate is set to 135 according to the aggregation state of (8).
Combination section 8-bit word string data DXO with MBps
(8) is formed. The combined section 8-bit word string data DXO (8) is provided with a line period corresponding to the horizontal synchronization signal SH and the vertical synchronization signal SV for controlling the transmission state of the read control signals QR1O to QR4O from the control signal forming unit 17, respectively. It has a frame period.

Also, the read outputs D1E (8) to D4E from the memory units 20B to 23B in the data collecting unit 25B.
The aggregation state of (8) is set according to each transmission state of the read control signals QR1E to QR4E from the control signal forming unit 17. Then, in the data collection unit 25B, the read outputs D1E (8) to D4 from the memory units 20B to 23B
According to the aggregation state of E (8), the word transmission rate is set to 13
Synthetic division 8-bit word string data DX with 5 MBps
E (8) is formed. The combined section 8-bit word string data DXE (8) also has a line period corresponding to the horizontal synchronization signal SH and the vertical synchronization signal SV for controlling the transmission state of the read control signals QR1E to QR4E from the control signal forming unit 17, and It has a frame period.

FIG. 3 shows a first example of the combined section 8-bit word string data DXO (8) and DXE (8) formed in the data collecting sections 25A and 25B, respectively. In the example shown in FIG. 3, as shown in FIG. 3A, portions L1, L2, L3,...
.. Begin with a blank portion (BA), and are followed by a read output D1O (8), a blank portion (BB),
The read outputs D1O (8) to D4O (8) are sequentially arranged. Also, as shown in FIG. 3B, portions L1, L2, L3,... Constituting each line period 1DL of the composite section 8-bit word string data DXE (8).
.. Begin with a blank portion (BA), and are followed by a read output D1E (8), a blank portion (BB),
The read outputs D1E (8) to D4E (8) are sequentially arranged.

FIG. 4 shows a second example of the combined section 8-bit word string data DXO (8) and DXE (8) formed in the data collecting units 25A and 25B, respectively. In the example shown in FIG. 4, as shown in FIG. 4A, the portions L1, L2, L3,... Constituting each line period 1DL of the composite section 8-bit word string data DXO (8).
.., The part L1 starts from the blank part (BA),
Subsequently, the read output D1O (8) and the blank portion (B
B) and the read output D1O (8)
The part L2 following 1 starts from the blank part (BA),
Subsequently, the read output D2O (8) and the blank portion (B
B) and the read output D2O (8)
The part L3 following 2 starts from the blank part (BA),
Subsequently, the read output D3O (8) and the blank portion (B
B) and the readout output D3O (8) are arranged, and the part L4 is connected to the part L4 in the same manner.
The content is returned to the same content as Also, as shown in FIG. 4B, the composite section 8-bit word string data DXE
Portions L1 and L configuring each line period 1DL in (8)
2, L3,..., Part L1 is a blank part (BA)
, Followed by a read output D1E (8), a blank portion (BB) and a read output D1E (8), and a portion L2 following the portion L1 is replaced by a blank portion (BA)
, Followed by a read output D2E (8), a blank portion (BB) and a read output D2E (8), and a portion L3 following the portion L2 is replaced by a blank portion (BA).
, Followed by a readout output D3E (8), a blank portion (BB) and a readout output D3E (8), to which a portion L4 is similarly connected.
5 returns to the same content as the portion L1.

FIG. 5 shows a third example of the combined section 8-bit word string data DXO (8) and DXE (8) formed in the data collecting sections 25A and 25B, respectively. In the example shown in FIG. 5, as shown in FIG. 5A, portions L1, L2, L3,... Constituting each line period 1DL of the composite section 8-bit word string data DXO (8).
.. Begin with a blank portion (BA), and subsequently read outputs D1O (8) to D4O (8) are sequentially arranged. Also, as shown in FIG. 5B, portions L1, L2, L3,... Constituting each line period 1DL of the composite section 8-bit word string data DXE (8).
.. Begin with a blank portion (BA), and subsequently, read outputs D1E (8) to D4E (8) are sequentially arranged.

FIG. 6 shows a fourth example of the combined section 8-bit word string data DXO (8) and DXE (8) formed in the data collecting sections 25A and 25B, respectively. In the example shown in FIG. 6, as shown in FIG. 6A, portions L1, L2, L3,... Constituting each line period 1DL of the composite section 8-bit word string data DXO (8).
.., The part L1 starts from the blank part (BA),
Subsequently, a read output D1O (8) is provided,
A portion L2 following the portion L1 starts with a blank portion (BA), followed by a read output D2O (8), and a portion L3 following the portion L2 is a blank portion (BA).
, Followed by a readout output D3O (8), to which a portion L4 is likewise connected,
The part L5 returns to the same content as the part L1.
Also, as shown in FIG. 6B, the portions L1, L2, L3,... Constituting each line period 1DL of the synthesized section 8-bit word string data DXE (8), the portion L1 is a blank portion (BA ) Followed by the read output D
1E (8), and a portion L2 following the portion L1
Starts from a blank portion (BA), and is followed by a read output D2E (8). A portion L3 following the portion L2 starts from the blank portion (BA), and subsequently, a read output D3E (8). 8) is arranged, and the part L4 is connected to the part L4 in the same manner, and thereafter, the part L5 returns to the same content as the part L1.

The combined section 8-bit word string data DXO (8) formed in the data collecting section 25A and the combined section 8-bit word string data DXE (8) formed in the data collecting section 25B are combined with the digital video signal DVS.
1 to DVS4, which are alternately derived from the data collection units 25A and 25B by a period corresponding to one frame period.
Supplied to In the data aggregating unit 26, the combined section 8-bit word string data DXO (8) and the combined section 8-bit word string data DXE (8) are sequentially and alternately connected to form a series of 8-bit word string data DM. Form (8).

The 8-bit word string data DM (8) formed in the data collection section 26 is obtained by multiplexing and synthesizing digital video signals DVS1 to DVS4 of four channels, and the word transmission rate is set to 135 MBps. It is. Then, 8-bit word string data DM (8) with a word transmission rate of 135 MBps obtained from the data collecting section 26 is supplied to the 8B / 10B conversion / 20-bit word string data forming section 27.

In the 8B / 10B conversion / 20-bit word string data forming section 27, the 8-bit word string data D
M (8) is subjected to an 8B / 10B conversion process in which each of the 8 bits forming each word in the M (8) is divided, and each of the divided 8 bits is sequentially converted into 10-bit data. The word transmission rate is set to 1 based on 10-bit data sequentially obtained by the conversion process.
20-bit word string data DM (20) with 35 MBps / 2 = 67.5 MBps is formed. And 8B
The 10-bit conversion / 20-bit word string data DM (20) obtained from the 20-bit word string data forming unit 27 and having a word transmission rate of 67.5 MBps is converted into a speed-converted data.
The data is supplied to the data insertion unit 28.

The speed conversion / data insertion unit 28 receives a predetermined data from the word data transmission unit 30 controlled by the control signal CDW from the control signal forming unit 17 in addition to the 20-bit word string data DM (20). An additional word data group DAV including a plurality of 20-bit word data including 20-bit word synchronization data to which a code has been assigned is supplied, and a control signal CIN and a clock pulse signal from the control signal forming unit 17 are further provided. CA and CB are supplied.

In the speed conversion / data insertion unit 28, the word transmission rate is set to 67.5 MBps.
For the 0-bit word string data DM (20), the word transmission rate is, for example, from 67.5 MBps to 7
While performing speed conversion to convert to 4.25 MBps,
At a predetermined word interval, an additional word data group DAV including the 20-bit word synchronization data from the word data transmission unit 30 is inserted, and thereby, based on the digital video signals DVS1 to DVS4 of four channels,
The compound 20-bit word string data DZ (20) having a word transmission rate of, for example, 74.25 MBps is formed.

FIG. 7 shows a specific configuration example of the speed conversion / data insertion unit 28. In the example shown in FIG. 7, the word transmission rate obtained from 8B / 10B conversion / 20-bit word string data forming section 27 is 67.5 MB.
20-bit word string data DM (20) having ps is supplied to the switch 31. The switch 31 is controlled by a control signal CSA from a switch control signal forming unit 32.

The control signal CIN from the control signal forming unit 17 is supplied to the switch control signal forming unit 32, and the switch control signal forming unit 32 responds to the control signal CIN for a predetermined period, for example, a period of 1 ms. Control signal CS having
A, and a control signal CSB synchronized with a control signal CDW for controlling the word data transmission unit 30 is transmitted.

As a result, the switch 31 outputs the control signal CS
A, switching is performed every predetermined period, for example, every 1 ms, so that the 20-bit word string data DM
(20) is changed to the memory unit 33 and the memory unit 34 every 1 ms.
And alternately supply 20-bit word string data DM
(20) is distributed to the memory unit 33 and the memory unit 34.

Further, a memory control signal forming unit 35 is provided in association with the memory unit 33 and the memory unit 34,
The memory control signal forming unit 35 includes, for example, a clock pulse signal CA having a frequency of 270 MHz synchronized with the clock signal in each of the digital video signals DVS1 to DVS4 of four channels, and a frequency of 74.25 MHz.
Is supplied. Then, the memory control signal forming unit 35 sets the frequency to 270 MHz / 4 = 67.5 based on the clock pulse signal CA.
A write control signal QW having a frequency of 74.2 MHz and a frequency of 74.2 based on a clock pulse signal CB are generated.
A read control signal QR of 5 MHz is generated, and the write control signal QW and the read control signal QR are supplied to both the memory unit 33 and the memory unit.

Thus, in the memory section 33, the 20-bit word string data DM (2
0) is supplied, the word transmission rate of the 20-bit word string data DM (20) is set to 67.5 according to the write control signal QW having a frequency of 67.5 MHz.
It is written in the state of MBps. Also, the memory unit 3
4, during the period in which the 20-bit word string data DM (20) is supplied through the switch 31,
The bit word string data DM (20) sets the frequency to 67.
According to the write control signal QW of 5 MHz, writing is performed in a state where the word transmission rate is 67.5 MBps.
Therefore, the writing in the state where the word transmission rate of the 20-bit word string data DM (20) in each of the memory unit 33 and the memory unit 34 is 67.5 MBps is performed alternately for 1 ms in accordance with the switching of the switch 31 every 1 ms. It is performed one by one.

The 20-bit word string data DM (20) written into the memory unit 33 for 1 ms is read in response to a read control signal QR having a frequency of 74.25 MHz during the next 1 ms. , The word transmission rate to 74.
20-bit word string data DM '(2
0) from the memory unit 33 and the switch 36
Supplied to Also, the 20-bit word string data DM (20) written in the memory unit 34 for 1 ms
Also, within the next 1 ms, the frequency is set to 74.25M.
In response to the read control signal QR at Hz, 20-bit word string data DM '(20) having a word transmission rate of 74.25 MBps is read from the memory unit 34 and supplied to the switch 36. The switch 36 is also supplied with the additional word data group DAV from the word data transmission unit 30. The additional word data group DAV has a word transmission rate of 74.25 MBps.

The switch 36 reads an additional word data group DAV from the word data transmitting section 30 at a word transmission rate of 74.25 MBps and the memory section 34 in response to the control signal CSB from the switch control signal forming section 32. 74.25 MBps
20-bit word string data DM ′ (20)
The word transmission rate read from the memory unit 33 is set to 7
20-bit word string data D at 4.25 MBps
Each of M ′ (20) is sequentially extracted for a predetermined word period. Then, the word transmission rate is set to 74.
Compound 20-bit word string data DZ with 25 MBps
(20) is derived.

At this time, the additional word data group DA from the word data transmitting unit 30 in response to the control signal CSB
The extraction of V is performed by 20-bit word string data DM '(20)
, The combined section 8-bit word string data DXO
(8) and DXE (8) in each blank part (B
A) is performed during the blank period corresponding to each of (A) and (BB), and the memory unit 34 according to the control signal CSB.
Of 20-bit word string data DM '(20) from the memory section 33 and the 20-bit word string data D
M ′ (20) is read out from 20-bit word string data D
This is performed in a period other than the period of the blank portion corresponding to each of the blank portions (BA) and (BB) in the combined section 8-bit word string data DXO (8) and DXE (8) in M ′ (20). .

An additional word data group DAV whose word transmission rate from the word data transmission unit 30 is 74.25 MBps is a group 2 which is given a predetermined code.
It is composed of a plurality of 20-bit word data including 0-bit word synchronization data. The 20-bit word synchronization data to which a predetermined code included in the additional word data group DAV is given is, for example, A shown in FIG.
And three word data 3FF constituting EAV and SAV the respective contained in the Y data sequence and the P _B / P _R data series as shown in B (Y), 000 (Y ), 00
0 (Y) or 3FF (C), 000 (C), 000
Three 10-bit word data 3FF corresponding to (C)
3FF: 3FFh, 000: 000000h, which is three word data formed by multiplexing two of a data group consisting of h, 000h, 000h (h represents a hexadecimal notation, and the same applies hereinafter). 000: 0
00h are sequentially arranged. 3FF:
3FFh is obtained by bit-multiplexing 10-bit word data 3FFh and 10-bit word data 3FFh into 20-bit word data.
000h is obtained by bit-multiplexing 10-bit word data 000h and 10-bit word data 000h into 20-bit word data.

The additional word data group DAV whose word transmission rate from the word data transmitting section 30 is 74.25 MBps is composed of three 20-bit word data 3FF: 3FF which are 20-bit word synchronous data.
h, 000: 000h, 000: in addition to 000h, for example, EAV and SAV contained in the Y data sequence and P _B / P _R data series as shown in A and B in FIG. 21
Word data XYZ (Y) or X
10-bit word data XYZh corresponding to YZ (C)
XY, which is word data formed by multiplexing two
Z: XYZh is also included.

Such an additional word data group DAV
Is, in one specific example, three consecutive 20-bit word data 3 which are 20-bit word synchronization data.
FF: 3FFh ,, 000,000: h ,, 000,000: 000h
, 20-bit word data XYZ: XYZh continues, and three consecutive 20-bit word data 3F
Prior to F: 3FFh, 000: 000h, 0,000,000: 000h, arbitrary 20-bit word data DX is arranged. In the composite 20-bit word string data DZ (20) formed by inserting such an additional word data group DAV, the portion into which the additional word data group DAV is inserted is, for example, as shown in FIG. You. 8, DM represents 20-bit word data forming the 20-bit word string data DM '(20) read from each of the memory units 33 and 34 shown in FIG. 7, and DX represents an arbitrary , And the arrow t indicates the passage of time.

The additional word data group DAV
Is, in another one of the specific examples, three consecutive 20-bit word data 3FF: 3FFh, 000000h, 000000, which are 20-bit word synchronous data.
0h is followed by 20-bit word data XYZ: XYZh, and four consecutive 20-bit word data 3
FF: 3FFh, 000,000: 000h, 000,000,000,000
h, XYZ: An arbitrary 20-bit word data DX is arranged before and after XYZh. In the composite 20-bit word string data DZ (20) formed by inserting such an additional word data group DAV, the portion into which the additional word data group DAV is inserted is, for example, as shown in FIG. You. Also in FIG.
M represents 20-bit word data forming 20-bit word string data DM '(20) read from each of the memory units 33 and 34 shown in FIG.
X represents arbitrary 20-bit word data, and an arrow t represents a lapse of time.

As described above, in the speed conversion / data insertion unit 28, the composite 20-bit word string data DZ (2
0) is formed. FIG. 10 shows a first example of the composite 20-bit word string data DZ (20). In the example shown in FIG. 10, portions LO1, LO2, LO3,... Constituting each line period 1ZL in each odd field period of composite 20-bit word string data DZ (20).
.. Start with the additional word data group DAV, followed by the word string data D1O (20) based on the read output D1O (8), the additional word data group DAV, and the read outputs D1O (8) to D4O. (8)
String data D1O (20) to D4O based on
(20) are sequentially arranged, and portions LE1, LE2, L constituting each line period 1ZL in each even field period of the composite 20-bit word string data DZ (20)
Each of E3,... Is an additional word data group DA
V, followed by word string data D1E (20) based on readout output D1E (8), additional word data group DAV, and readout outputs D1E (8) to D4.
Word string data D1E (20)-based on E (8), respectively.
D4E (20) are sequentially arranged.

FIG. 11 shows a second example of the composite 20-bit word string data DZ (20). In the example shown in FIG. 11, composite 20-bit word string data DZ (2
0) Each line period 1Z in each odd field period
Each of the parts LO1, LO2, LO3,...
, Followed by word string data D1O (20) based on the read output D1O (8), additional word data group DAV and word string data D1O (20) based on the read output D1O (8), Partial LO1
LO2 following the additional word data group DAV
, Followed by word string data D2O (20) based on the read output D2O (8), additional word data group DAV and word string data D2O (20) based on the read output D2O (8). Partial LO2
LO3 following the additional word data group DAV
, Followed by word string data D3O (20) based on the read output D3O (8), an additional word data group DAV, and word string data D3O (20) based on the read output D3O (8). Then, part LO4 is similarly connected, and then part LO5 becomes part LO.
The contents are returned to the same contents as in 1.

Further, in the example shown in FIG.
Each of the parts LE1, LE2, LE3,... Constituting each line period 1ZL in each even field period of the composite 20-bit word string data DZ (20) is a part LE
1 starts with the additional word data group DAV, followed by word string data D1E (20) based on the read output D1E (8) and the additional word data group DAV.
And word string data D1 based on read output D1E (8)
E (20), and a portion LE following the portion LE1
2 starts from the additional word data group DAV, and is followed by word string data D2E (20) based on the read output D2E (8) and the additional word data group DAV.
And word string data D2 based on read output D2E (8)
E (20), and a part LE following the part LE2
3 starts with the additional word data group DAV, followed by the word string data D3E (20) based on the read output D3E (8) and the additional word data group DAV.
And word string data D3 based on read output D3E (8)
E (20) is arranged, and the part LE4 is connected to the part LE4, and then the part LE5 returns to the same contents as the part LE1.

FIG. 12 shows a third example of the composite 20-bit word string data DZ (20). In the example shown in FIG. 12, composite 20-bit word string data DZ (2
0) Each line period 1Z in each odd field period
Each of the parts LO1, LO2, LO3,... Constituting the L starts from the additional word data group DAV, and is followed by the word string data D1O (20) based on the read outputs D1O (8) to D4O (8). ) To D4O (2
0) are sequentially arranged, and furthermore, portions LE1, LE2, LE constituting each line period 1ZL in each even field period of the composite 20-bit word string data DZ (20).
Each of 3,... Is an additional word data group DAV
, Followed by the read outputs D1E (8) to D1E
Word string data D1E (20) based on each of 4E (8)
To D4E (20) are sequentially arranged.

FIG. 13 shows a fourth example of the composite 20-bit word string data DZ (20). In the example shown in FIG. 13, composite 20-bit word string data DZ (2
0) Each line period 1Z in each odd field period
Each of the parts LO1, LO2, LO3,...
, Followed by word string data D1O (20) based on the read output D1O (8), and the part LO2 following the part LO1 starts with the additional word data group DAV, and subsequently, the read output D2O
The word string data D2O (20) based on (8) is arranged, and the part LO3 following the part LO2 starts from the additional word data group DAV, and subsequently, the word string data D3O based on the read output D3O (8). (20)
Is arranged, and the part LO4 is similarly connected to the part LO4. Thereafter, the part LO5 returns to the same content as the part LO1.

Further, in the example shown in FIG.
Each of the parts LE1, LE2, LE3,... Constituting each line period 1ZL in each even field period of the composite 20-bit word string data DZ (20) is a part LE
1 starts with the additional word data group DAV, followed by word string data D1E (20) based on the read output D1E (8), and a part LE2 following the part LE1 is read from the additional word data group DAV. The word string data D2E (20) based on the read output D2E (8) is arranged, followed by the partial LE
2 is a part LE3 following the additional word data group DA.
V, followed by word string data D3E (20) based on the read output D3E (8),
Then, the part LE4 is similarly connected, and then the part LE5
Returns to the same content as the part LE1.

The word transmission rate obtained from the switch 36 in the rate conversion / data insertion unit 28 is 74.25.
MBps composite 20-bit word string data DZ (2
0) is transmitted from the compound word string data forming unit 11 and supplied to the P / S conversion unit 38. P / S converter 38
, The composite 20-bit word string data DZ (2
0), P for converting parallel data into serial data
/ S conversion to obtain composite 20-bit word string data DZ
A bit transmission rate of 74.25 × 2 based on (20)
A composite 20-bit word is obtained by obtaining serial data with 0 = 1.485 Gbps, dividing the serial data by, for example, a ninth-order primitive polynomial: X ⁹ + X ⁴ +1 and further dividing by an expression: X + 1. Column data DZ
The scramble processing is performed on the serial data based on (20) to form scrambled serial data DZS, and the serial data DZS is supplied to the transmission signal forming unit 39.

The transmission signal forming section 39 outputs the serial data D
For example, a ZS is connected to a coaxial cable or an optical cable.
An electric signal suitable for a data transmission line formed using a coaxial cable or a data transmission line formed using an optical fiber for transmission through a data transmission line formed using a fiber. The signal is converted into a transmission signal SZ that is a suitable optical signal and transmitted.
Thereby, transmission of the scrambled serial data DZS is performed.

As described above, the 8-bit word string data DM (8) obtained by performing the multiplexing / combining processing on the 4-channel digital video signals DVS1 to DVS4 is subjected to the 8B / 10B conversion processing. The speed conversion process is performed on the 20-bit word string data DM (20) formed through the process, and three consecutive 20-bit word data 3F which are 20-bit word synchronization data.
The composite 20-bit word string data DZ (20) formed by inserting an additional word data group DAV including F: 3FFh, 000: 000h, 000: 000h and 20-bit word data XYZ: XYZh is subjected to scramble processing. The data is converted into serial data DZS and transmitted. At this time, a 20-bit word string formed through a process of performing 8B / 10B conversion processing on the 8-bit word string data DM (8) Data DM (2
In the case of 0), because of the characteristics of the 8B / 10B code, the sequence of the code "0" or "1" does not become 6 or more, so the 20-bit word synchronous data 3FF: 3FF
h, 000: 000h, m: 00000: h do not appear. Therefore, the composite 20-bit word string data DZ
In (20), 20-bit word string data DM
Additional word data group DAV added to (20)
20-bit word synchronous data 3FF: 3FF contained in
Only h, 000: 000h, m: 00000h are assumed to play the role of synchronous data.

The composite 20 in the P / S converter 38
The scrambling process for the serial data based on the bit word string data DZ (20) is not always necessary. It may be supplied to the unit 39. Composite 2
When serial data based on the 0-bit word string data DZ (20) is transmitted without being subjected to scramble processing, improvement in transmission characteristics is expected.

In the data transmission apparatus shown in FIG. 1 as described above, the P / S conversion section 38 and the transmission signal forming section 3
9 is a composite 20-bit word string having a word transmission rate of 74.25 MBps and a bit transmission rate of 1.
485 Gbps, and is transmitted without being subjected to scramble processing or being subjected to scramble processing.
The S conversion unit 38 and the transmission signal formation unit 39 are, for example, HD
The present invention can be configured by effectively utilizing an integrated circuit (IC) element provided for transmitting a digital video signal under a TV system. Accordingly, the digital video signals DVS1 to DVS4 of four channels each having a bit transmission rate of 270 Mbps are converted into 20-bit word synchronous data 3FF: 3FFh, 00000: 000h, 00.
Assuming that the data synchronization state required for the reproduction process on the receiving side can be reliably obtained by 0: 000h, it can be performed by means that can be prepared relatively easily without developing new circuit elements and the like. become.

FIG. 14 shows another example of the data transmission method according to the invention described in claims 1, 2, 3, 5 or 6 in the claims of the present application. 7 shows another example of the data transmission apparatus according to the invention described in claim 7 in the first embodiment.

In the example shown in FIG. 14, for example,
4 channel digital video signals DVP1, DVP
2, DVP3 and DVP4 are supplied to the compound word string data forming unit 11 '. Each of the four-channel digital video signals DVP1 to DVP4 is, for example, A
And multiplexing process is formed is subjected to a Y data sequence and P _B / P _R data sequence shown in B, taking word multiplexed data format embodiment of as shown in FIG. 22 1
It is a 0-bit quantized digital signal, and is parallel data whose word transmission rate is, for example, 27 MBps.

In the composite word string data forming section 11 ', the frame synchronizing signal SSF, horizontal synchronizing signal SH, vertical synchronizing signal SV, and frequency of each of the digital video signals DVP1 to DVP4 synchronized with the frame period are set to 74.25.
MHz clock pulse signal CB and frequency 27
A clock pulse signal CC of MHz is also supplied.

Although not shown, the composite word string data forming section 11 'is configured similarly to the composite word string data forming section 11 shown in FIG. In the composite word string data forming unit 11 ', the composite word string data forming unit 11 shown in FIG. The same processing as that performed is performed to obtain composite 20-bit word string data DZ (20) based on the digital video signals DVP1 to DVP4.

At this time, in each of the four-channel digital video signals DVP1 to DVP4, each odd frame period portion and each even frame period portion are formed based on the clock pulse signal CC, and a write control signal having a frequency of 27 MHz. Are sequentially written into a pair of memory means in accordance with the following formula.
5 = 135 MHz, and the supply state is the horizontal synchronization signal S.
According to the read control signal controlled by H and the vertical synchronization signal SV, the data is read as 8-bit word string data having a word transmission rate of 135 MBps. And
The multiplexing and synthesizing process is performed on the 8-bit word string data read from each memory means, and the 8-bit word string data D
M (8) is formed and its 8-bit word string data DM
(8) is subjected to 8B / 10B conversion processing to form 20-bit word string data DM (20), and the word transmission rate is set to 74.25 MB for the 20-bit word string data.
In addition to performing the speed conversion processing of ps, three consecutive 20-bit word data 3FF: 3FFh, 000000h, 00 which are 20-bit word synchronous data
0: 000h and 20-bit word data XYZ: XYZ
h is added. Thereby, composite 20-bit word string data DZ (20) into which additional word data groups DAV are inserted at predetermined word intervals is obtained.

The compound 20-bit word string data DZ (20) obtained from the compound word string data forming section 11 'is P
/ S conversion section 41. In the P / S converter 41, the composite 20-bit word string data DZ (20)
Performs P / S conversion and performs composite 20-bit word string data DZ
Bit transmission rate of 74.25 MB based on (20)
The serial data DZS with ps × 20 = 1.485 Gbps is formed, and the serial data DZS is supplied to the transmission signal forming unit. The transmission signal forming unit 42 is suitable for a data transmission path formed by using a coaxial cable so as to transmit the serial data DZS through, for example, a data transmission path formed by using a coaxial cable or an optical fiber. The signal is converted into an electric signal or a transmission signal SZ which is an optical signal suitable for a data transmission path formed using an optical fiber and transmitted. Thereby, transmission of the serial data DZS is performed.

As described above, a 20-bit word string formed through a process of performing an 8B / 10B conversion process on 8-bit word string data DM (8) based on 4-channel digital video signals DVP1 to DVP4. Data D
M (20) is subjected to speed conversion processing,
Three consecutive 20-bit word data 3FF: 3FFh, 000000h, which are bit word synchronization data
Additional word data group D including 000: 000h
The composite 20-bit word string data DZ (20) formed by inserting the AV is converted into scrambled serial data DZS and transmitted.
At this time, 8B / 1 is added to the 8-bit word string data DM (8).
In the 20-bit word string data DM (20) formed through the process of performing the 0B conversion process, 8B / 10
According to the characteristics of the B code, since the continuation of the code: "0" or "1" does not become 6 or more, the 20-bit word synchronous data 3FF: 3FFh, 000: 000h, 00
0: 000h does not appear. Therefore, composite 20
In the bit word string data DZ (20), 20-bit word synchronization data 3FF: 3FFh, 000: 000h, 00 included in the additional word data group DAV added to the 20-bit word string data DM (20).
Only 0: 000h plays the role of synchronous data.

The composite 20 in the P / S converter 41
The scrambling process for the serial data based on the bit word string data DZ (20) is not always necessary. It may be supplied to the unit 42. Composite 2
When serial data based on the 0-bit word string data DZ (20) is transmitted without being subjected to scramble processing, improvement in transmission characteristics is expected.

Even in the data transmission apparatus shown in FIG. 14 as described above, P / S conversion section 41 and transmission signal forming section 42 transmit composite 20-bit word string data having a word transmission rate of 74.25 MBps. Since the data is converted into serial data having a bit transmission rate of 1.485 Gbps and transmitted without being subjected to scrambling or scrambling, the P / S converter 41 and the transmission signal formation are performed. The part 42 is, for example,
The present invention can be configured by effectively utilizing an integrated circuit (IC) element provided for transmitting a digital video signal under an HDTV system. Therefore, the digital video signals DVP1 to DVP4 of four channels each being parallel data having a bit transmission rate of 27 MBps.
To 20-bit word synchronous data 3FF: 3FFh, 0
The data synchronization state required for the reproduction process on the receiving side can be reliably obtained by 00: 000h and 000000h, and can be relatively easily prepared without the need to develop new circuit elements and the like. It can be done by means.

FIG. 15 shows another example of the data transmission method according to the invention described in claims 1, 2, 3, 4 or 6 in the claims of the present application. 7 shows still another example of the data transmission apparatus according to the invention described in claim 7 of the present invention.

In the example shown in FIG. 15, for example,
Two-channel digital video signals DVS1 and DVS2, each of which is a serial digital signal, and four-channel serialized digital video signals DVSa, DVSb, DV, each of which is a serial digital signal.
Sc and DVSd are combined word string data forming unit 1
1 ".

Two-channel digital video signal DVS
1 and DVS2 Each of the, for example, multiplexing processing in the Y data sequence and P _B / P _R data sequence shown in A and B of Figure 21 is formed is subjected, word multiple as shown in FIG. 22 This is a 10-bit quantized digital signal having a data format, and its bit transmission rate is set to, for example, 270 Mbps serial data. Also, the digital video signal DVS of four channels
Each of a to DVSd is a 10-bit quantized digital signal having a data format similar to the word multiplexed data format as shown in FIG. 22, and is serial data having a bit transmission rate of, for example, 143 Mbps. .

In the composite word string data forming section 11 ″, in addition to the digital video signals DVS1 and DVS2 and the digital video signals DVSa to DVSd, the digital video signals DVS1 and DVS2 and the digital video signal DVS are provided.
a to DVSd, a frame synchronization signal SSF synchronized with the frame period, a horizontal synchronization signal SH, a vertical synchronization signal SV, a clock pulse signal CA having a frequency of 270 MHz, a clock pulse signal CB having a frequency of 74.25 MHz, and A clock pulse signal CD having a frequency of 143 MHz is also supplied.

Although not shown, the composite word string data forming unit 11 ″ is configured similarly to the composite word string data forming unit 11 shown in FIG. 1. However, the compound word string data forming unit 11 ″ is not shown. , Six switches corresponding to the switches 12 to 15 in the compound word string data forming unit 11, six memory units corresponding to the memory units 20A to 23A in the compound word string data forming unit 11, and
Memory unit 20B in compound word string data forming unit 11
The six memory units corresponding to .about.23B are converted into the control signal forming unit 17, the data collecting units 25A and 25B and the 26,8B / 10B conversion / 20 in the compound word string data forming unit 11.
The bit word string data forming unit 27, the speed conversion / data inserting unit 28, and the word data transmitting unit 30 are provided in addition to the corresponding units.

Then, the compound word string data forming unit 11 ″
, Digital video signals DVS1 and DVS2
Are two of the six memory units corresponding to the memory units 20A to 23A in the compound word string data forming unit 11, and the memory units 20B to 20B in the compound word string data forming unit 11 respectively. The memory is sequentially written into two of the six memory units corresponding to 23B in accordance with a write control signal having a frequency of 270 MHz from a portion corresponding to the control signal forming unit 17 in the composite word string data forming unit 11, and , Digital video signal DV
Each frame period portion in each of Sa to DVSd is
Memory unit 20A in compound word string data forming unit 11
Out of the six memory units corresponding to .about.23A and the memory unit 2 in the compound word string data forming unit 11.
Data is sequentially written to four of the six memory units corresponding to 0B to 23B in accordance with a write control signal having a frequency of 143 MHz from a portion corresponding to the control signal forming unit 17 in the composite word string data forming unit 11. . The data reading from each memory unit, the read output obtained from each memory unit, and the combination of the additional word data group DAV are performed in the same manner as in the case of the composite word string data forming unit 11.

Thus, compound word string data forming section 1
1 ", the digital video signals DVS1 and DVs
A composite 20-bit word string data DZ (20) is obtained based on S2 and the digital video signals DVSa to DVSd.
The composite 20-bit word sequence data DZ (20) is also a digital video signal of 6 channels in total, similarly to the composite 20-bit word sequence data DZ (20) transmitted from the composite word sequence data forming unit 11 shown in FIG. 8B / 1 is added to 8-bit word string data DM (8) based on DVS1 and DVS2 and digital video signals DVSa to DVSd.
Through the process of performing the 0B conversion process, the 20-bit word sequence data DM (20) is formed. The speed conversion process is performed on the 20-bit word sequence data DM (20). Three consecutive
20-bit word data 3FF: 3FFh, 00
This is 20-bit word string data with a word transmission rate of 74.25 MBps, formed by inserting an additional word data group DAV including 0: 000h, 000000: 000h and 20-bit word data XYZ: XYZh.

The compound 20-bit word string data DZ (20) obtained from the compound word string data forming unit 11 ″ is
/ S converter 43. The P / S converter 43 converts the composite 20-bit word string data DZ (20) into
Performs P / S conversion and performs composite 20-bit word string data DZ
Bit transmission rate of 74.25 MB based on (20)
The serial data DZS with ps × 20 = 1.485 Gbps is formed, and the serial data DZS is supplied to the transmission signal forming unit 44. The transmission signal forming unit 44 is suitable for a data transmission line formed using a coaxial cable, for transmitting the serial data DZS through a data transmission line formed using, for example, a coaxial cable or an optical fiber. The signal is converted into an electric signal or a transmission signal SZ which is an optical signal suitable for a data transmission path formed using an optical fiber and transmitted. Thereby, transmission of the serial data DZS is performed.

As described above, the 8B / 10B conversion process is performed on the 8-bit word string data DM (8) based on the digital video signals DVS1 and DVS2 of the total of 6 channels and the digital video signals DVSa to DVSd. 20-bit word string data DM formed through
(20) is subjected to a speed conversion process, and three consecutive 20-bit word data 3FF: 3FFh, 0,000,000: 000h, 0 which are 20-bit word synchronous data.
Additional word data group DA including 00: 000h
The composite 20-bit word string data DZ (20) formed by inserting V is converted into scrambled serial data DZS and transmitted. At this time, the 8-bit word string data DM (8) has 8B / 10
In the 20-bit word string data DM (20) formed through the process of performing the B conversion processing, 8B / 10B
From the characteristics of the code, since the sequence of the code: "0" or "1" does not become 6 or more, the 20-bit word synchronous data 3FF: 3FFh, 000: 000h, 00
0: 000h does not appear. Therefore, composite 20
In the bit word string data DZ (20), 20-bit word synchronization data 3FF: 3FFh, 000: 000h, 00 included in the additional word data group DAV added to the 20-bit word string data DM (20).
Only 0: 000h plays the role of synchronous data.

The composite 20 in the P / S converter 43
The scrambling process for the serial data based on the bit word string data DZ (20) is not always necessary. It may be supplied to the unit 44. Composite 2
When serial data based on the 0-bit word string data DZ (20) is transmitted without being subjected to scramble processing, improvement in transmission characteristics is expected.

Even in the data transmission apparatus shown in FIG. 15 as described above, P / S conversion section 43 and transmission signal forming section 44 transmit composite 20-bit word string data having a word transmission rate of 74.25 MBps. Since the data is converted into serial data having a bit transmission rate of 1.485 Gbps and transmitted without being subjected to scrambling or scrambling, the P / S converter 43 and the transmission signal formation are performed. The part 44 is, for example,
The present invention can be configured by effectively utilizing an integrated circuit (IC) element provided for transmitting a digital video signal under an HDTV system. Therefore, the two-channel digital video signals DVS1 and DVS2 each having a bit transmission rate of 270 Mbps and the four channel digital video signals DVSa to DVSd each having a bit transmission rate of 143 Mbps are converted into 20-bit word synchronous data by the receiving side. As a means for reliably obtaining the data synchronization state required for the reproduction processing in the above, it can be performed by means that can be prepared relatively easily without the need to develop new circuit elements and the like.

FIG. 16 shows a composite 20-bit signal transmitted from the transmission signal forming unit 39 in the example of the data transmission apparatus shown in FIG. 1 according to the example of the data transmission method according to the invention described in the claims of the present application. Word string data DZ (2
0) is an example of a data receiving apparatus that receives a transmission signal SZ based on serial data DZS that has been converted and has been subjected to scramble processing (or not subjected to scramble processing).

In the example of the data receiving apparatus shown in FIG. 16, for example, an electric signal suitable for a data transmission path formed by using a coaxial cable or an optical fiber formed by using an optical fiber is used. A receiving unit 60 is provided for receiving a transmission signal SZ which is an optical signal suitable for the data transmission path. The receiving unit 60 transmits the transmission signal SZ
, The scrambled (or unscrambled) serial data DZS based on the received transmission signal SZ is reproduced,
It is supplied to the synchronous data detection / S / P converter 61.

In the synchronous data detection / S / P converter 61, the scrambled serial data DZ
S is multiplied by the expression: X + 1, and a ninth-order primitive polynomial:
The descrambling process is performed on the scrambled serial data DZS by multiplying by X ⁹ + X ⁴ +1 to obtain the scrambled serial data (or directly take in the scrambled serial data DZS). ).

Further, a synchronous data detection / S / P converter 6
1 is 20-bit word synchronous data in serial data DZS obtained by performing descrambling processing on the scrambled serial data DZS (or serial data DZS not performing scrambling processing). Three consecutive 20-bit word data 3FF: 3FFh, 000: 000h, 000:
000h is converted into serial data, the serial data is detected as synchronous data, word synchronization is performed based on the detected synchronous data, and the serial data DZS is descrambled to obtain serial data (or
Serial data DZ not subjected to scramble processing
S) is subjected to S / P conversion, and as shown in FIG. 17A or FIG.
Composite 20 which is parallel data with 4.25 MBps
The bit word string data DZ (20) is formed. Then, the composite 20-bit word string data DZ (20) obtained from the synchronous data detection / S / P converter 61 is supplied to the word data separation / speed converter 62.

The synchronous data detection / S / P converter 61
, The composite 20-bit word string data DZ (2
0) in the additional word data group DAV
Three consecutive 20-bit word data 3FF: 3FFh, 000000h which are 0-bit word synchronous data
And 000: 000h, and sends out a synchronous data detection output signal SDD. This synchronous data detection output signal S
DD is, for example, the composite 20-bit word string data DZ detected by the synchronous data detection / S / P converter 61.
Three consecutive 20-bit word data 3FF: 3FF in the additional word data group DAV in (20)
Corresponding to the last one of h: 000: 000h and 000: 000h, it is obtained as shown in FIG. 17B or FIG. 18B. Note that the arrow t in FIGS. 17 and 18 indicates the passage of time. In this way,
The synchronous data detection output signal SDD obtained from the synchronous data detection / S / P conversion unit 61 is supplied to the word data separation / speed conversion unit 62 and the serial data restoration unit 63.

The word data separation / speed conversion section 62 uses the synchronization data detection output signal SDD from the synchronization data detection / S / P conversion section 61 to add the data from the composite 20-bit word string data DZ (20). The word data group DAV is separated, and the word transmission rate based on the composite 20-bit word string data DZ (20) is set to 74.
20-bit word string data DM (2
0) and the additional word data group DAV are separated from each other and taken out. Then, a word transmission rate of 7 is added to the extracted 20-bit word string data DM (20).
From 4.25 MBps, increase the word transmission rate to 6.
A rate conversion to 7.5 MBps is performed.

As a result, the word transmission speed obtained from the word data separation / speed conversion unit 62 is reduced to 67.5 MBp.
s, the 20-bit word string data DM (20) is 1
The additional word data group DAV obtained from the 0B / 8B conversion / 8-bit word string data forming unit 64 and obtained from the word data separation / speed conversion unit 62 is supplied to the serial data restoration unit 63.

In 10B / 8B conversion / 8-bit word string data forming section 64, 20-bit word string data D
M (20) is subjected to a 10B / 8B conversion process in which each of the 10 bits is divided, and each of the divided 10 bits is sequentially converted to 8-bit data. The word transmission rate is set to 135 MBp based on the obtained 8-bit data.
The 8-bit word string data DM (8) is formed as s. The word transmission rate obtained from the 10B / 8B conversion / 8-bit word string data forming unit 64 is 135M
The 8-bit word string data DM (8) having Bps is supplied to the serial data restoration unit 63.

In the serial data restoration section 63, the synchronous data detection output signal SDD from the synchronous data detection / S / P conversion section 61 and the additional word data group DAV from the word data separation / speed conversion section 62 are controlled. The signal is supplied to the signal forming unit 66, and the 10B / 8B conversion.
The 8-bit word string data DM (8) from the bit word string data forming unit 64 is supplied to the movable contact 65a of the switch 65. The control signal forming unit 66 is also supplied with a clock pulse signal CA having a frequency of 270 MHz.

The 8-bit word string data DM (8) from the 10B / 8B conversion / 8-bit word string data forming section 64
Is supplied with the control signal CDF from the control signal forming unit 66. The control signal CDF is the 20-bit word data X in the additional word data group DAV from the word data separation / speed conversion unit 62 which is detected by the control signal forming unit 66 using the synchronous data detection output signal SDD.
YZ: formed based on XYZh and synchronized with a frame period (hereinafter, referred to as a specific frame period) of 20-bit word string data DM (20) obtained from the word data separation / speed conversion unit 62.

The switch 65 alternately connects the movable contact 65a to the selection contact 65b and the selection contact 65c for each time section corresponding to a specific frame period according to the control signal CDF from the control signal forming unit 66. Perform the operation. The selection contacts 65b of the switch 65 include the memory units 70A, 71
A, 72A and 73A are connected.
Of the memory sections 70B, 71B, 72
B and 73B are connected.

Thus, the switch 65 sets the control signal C
According to the DF, the 8-bit word string data DM from the 10B / 8B conversion / 8-bit word string data forming unit 64
(8) is replaced by a portion corresponding to a specific frame period, each of the memory units 70A, 71A, 72A and 73A, and
The data is supplied to the memory units 70B, 71B, 72B, and 73B alternately and sequentially.

The write control signals QW1O, QW2O, QW from the control signal forming section 66 are provided in the memory sections 70A to 73A.
3O and QW4O are supplied, respectively.
Write control signals QW1E, QW2E, QW3E, and QW4E from the control signal forming unit 66 are supplied to B to 73B, respectively. Each of the write control signals QW1O to QW4O and QW1E to QW4E obtained from the control signal forming unit 66 is formed based on the clock pulse signal CA, and has a frequency of 270 MHz / 2 = 135 MHz. The transmission timing from the control signal forming unit 66 is determined according to the synchronous data detection output signal SDD.
Further, control is performed in accordance with a preset timing corresponding to the data synthesis mode of each line period portion in the 8-bit word string data DM (8) from the 10B / 8B conversion / 8-bit word string data forming unit 64. Is done.

At this time, writing in each of the memory units 70A to 73A and writing in each of the memory units 70B to 73B are alternately performed for each time section corresponding to a specific frame period in which the control signal CDF is synchronized. . Then, in the time section corresponding to each specific frame period, the specific frame period of the 8-bit word string data DM (8) is set in accordance with the transmission timing of the write control signals QW1O to QW4O from the control signal forming unit 66. 8-bit word string data D1O (8), D2 constituting corresponding first portion
O (8), D3O (8) and D4O (8) are written together in the memory units 70A, 71A, 72A and 73A, respectively. In addition, the write control signal QW from the control signal forming unit 66 is added to the time section corresponding to the next specific frame period.
1E to QW4E, the 8-bit word string data D (8) forming the second part corresponding to the specific frame period of the 8-bit word string data DM (8) in accordance with the transmission timing.
1E (8), D2E (8), D3E (8) and D4E
(8) are written together in the memory units 70B, 71B, 72B, and 73B, respectively.

Further, each of memory units 70A to 73A is supplied with a read control signal QRO from control signal forming unit 66, and each of memory units 70B to 73B is provided with a read control signal QRO from control signal forming unit 66. A control signal QRE is provided. The read control signal QRO has a frequency of 270 MHz based on the clock pulse signal CA.
8B from the 8B conversion / 8-bit word string data forming unit 64
The control signal forming unit 6 synchronizes with the first portion corresponding to the specific frame period in the bit word string data DM (8).
6 and the read control signal QRE is formed to have a frequency of 270 MHz based on the clock pulse signal CA, and the synchronous data detection output signal SDD
In response to this, the control signal forming unit 66 transmits the 8-bit word string data DM (8) from the 10B / 8B conversion / 8-bit word string data forming unit 64 in synchronization with the second portion corresponding to the specific frame period. Is done.

Thus, in the time division corresponding to every other specific frame period, memory units 70A to 73A
8-bit word string data D1O respectively written to
(8) to D4O (8) are read from the memory units 70A to 73A in the time section corresponding to the next specific frame period in accordance with the read control signal QRO. At this time, each of the 8-bit word string data D1O (8) to D4O (8) written in each of the memory units 70A to 73A has a bit transmission rate corresponding to the frequency 270 MHz of the read control signal QRO.
270 Mbps according to the data, read out as forming serial data, and read out the memory units 70A to 73A.
From the 8-bit word string data D1O (8) to D1O (8) to D, respectively.
The bit transmission rate based on 4O (8) is 270 Mbp
The readout outputs S1O and S2 converted to serial data as s
O, S3O and S4O are obtained.

Further, in a time section corresponding to every other specific frame period, the 8-bit word string data D1E (8) written in the memory units 70B to 73B respectively.
To D4E (8) in the time section corresponding to the next specific frame period in accordance with the read control signal QRE.
B to 73B. At that time, the memory unit 7
Each of the 8-bit word string data D1E (8) to D4E (8) read from 0B to 73B forms serial data whose bit transmission rate is 270 Mbps corresponding to the frequency 270 MHz of the read control signal QRE. Then, the read outputs S1E, S2E, and S are converted from the memory units 70B to 73B into serial data based on the 8-bit word string data D1E (8) to D4E (8), respectively.
3E and S4E are obtained.

Read output S1 obtained from memory unit 70A
O and the read output S1E obtained from the memory unit 70B are connected to the switch 75, and the read output S1 obtained from the memory unit 71A.
2O and the read output S2E obtained from the memory unit 71B are obtained from the switch 76, the read output S3O obtained from the memory unit 72A and the read output S3E obtained from the memory unit 72B are obtained from the switch 77, and obtained from the memory unit 73A. The read output S4O and the read output S4E obtained from the memory unit 73B are supplied to the switch 78, respectively.

Each of the switches 75 to 78 is also supplied with a control signal CSF from the control signal forming section 66. The control signal CSF is synchronized with the control signal CDF.

The switch 75 alternately takes out the readout output S1O and the readout output S1E according to the control signal CSF, and outputs a digital video signal DV having a bit transmission rate of 270 Mbps as a series of serial digital signals.
Play S1. Similarly, switch 76 sets control signal C
According to the SF, the read output S2O and the read output S2E are alternately taken out, and are a series of serial digital signals.
The digital video signal DVS2 having the bit transmission rate of 270 Mbps is reproduced, and the switch 77
According to SF, the read output S3O and the read output S3E are alternately taken out, and are a series of serial digital signals.
The digital video signal DVS3 having the bit transmission rate of 270 Mbps is reproduced, and the switch 78 further operates the readout output S40 and the readout output S4 according to the control signal CSF.
E are alternately taken out, and a digital video signal DVS4 having a bit transmission rate of 270 Mbps, which is a series of serial digital signals, is reproduced.

In this way, the four-channel digital video signal DVS obtained from the switches 75 to 78, respectively.
1 to DVS4 are transmitted from the serial data restoration unit 63.

FIG. 19 shows a transmission signal forming unit 42 in the example of the data transmission apparatus shown in FIG. 14 according to the example of the data transmission method according to the invention described in the claims of the present application.
, Composite 20-bit word string data DZ
(20) shows an example of a data receiving apparatus that receives a transmission signal SZ based on serial data DZS that has been converted and has been subjected to scramble processing (or not subjected to scramble processing).

In the example of the data receiving apparatus shown in FIG. 19, for example, an electric signal suitable for a data transmission path formed by using a coaxial cable or an optical fiber formed by using an optical fiber is used. A receiving unit 80 is provided for receiving a transmission signal SZ which is an optical signal suitable for the data transmission path. The receiving unit 80 transmits the transmission signal SZ
, The scrambled (or unscrambled) serial data DZS based on the received transmission signal SZ is reproduced,
It is supplied to the synchronous data detection / S / P converter 81.

In the synchronous data detection / S / P converter 81, the scrambled serial data DZ
S is multiplied by the expression: X + 1, and a ninth-order primitive polynomial:
The descrambling process is performed on the scrambled serial data DZS by multiplying by X ⁹ + X ⁴ +1 to obtain the scrambled serial data (or directly take in the scrambled serial data DZS). ).

Further, a synchronous data detection / S / P converter 8
1 is 20-bit word synchronous data in serial data DZS obtained by performing descrambling processing on the scrambled serial data DZS (or serial data DZS not performing scrambling processing). Three consecutive 20-bit word data 3FF: 3FFh, 000: 000h, 000:
000h is converted into serial data, the serial data is detected as synchronous data, word synchronization is performed based on the detected synchronous data, and the serial data DZS is descrambled to obtain serial data (or
Serial data DZ not subjected to scramble processing
S) is subjected to S / P conversion, and for example, compound 2 which is parallel data with a word transmission rate of 74.25 MBps
The 0-bit word string data DZ (20) is formed. Then, the composite 20-bit word string data DZ (20) obtained from the synchronous data detection / S / P converter 81 is supplied to the word data separation / speed converter.

Synchronous data detection / S / P converter 81
, The composite 20-bit word string data DZ (2
0) in the additional word data group DAV
Three consecutive 20-bit word data 3FF: 3FFh, 000000h which are 0-bit word synchronous data
And 000: 000h, and sends out a synchronous data detection output signal SDD. This synchronous data detection output signal S
DD is, for example, the composite 20-bit word string data DZ detected by the synchronous data detection / S / P converter 81.
Three consecutive 20-bit word data 3FF: 3FF in the additional word data group DAV in (20)
It is obtained corresponding to the last of h: 000: 000h and 0: 000h. In this way, the synchronous data detection output signal SDD obtained from the synchronous data detection / S / P converter 81 is converted to the word data separation / speed converter 8.
2 and the serial data restoration unit 63 '. A clock pulse signal CA having a frequency of 270 MHz is also supplied to the serial data restoration unit 63 '.

The word data separation / speed conversion section 82 uses the synchronization data detection output signal SDD from the synchronization data detection / S / P conversion section 81 to add the data from the composite 20-bit word string data DZ (20). The word data group DAV is separated, and the word transmission rate based on the composite 20-bit word string data DZ (20) is set to 74.
20-bit word string data DM (2
0) and the additional word data group DAV are separated from each other and taken out. Then, a word transmission rate of 7 is added to the extracted 20-bit word string data DM (20).
From 4.25 MBps, increase the word transmission rate to 6.
A rate conversion to 7.5 MBps is performed.

As a result, the word transmission speed obtained from the word data separation / speed conversion unit 82 is reduced to 67.5 MBp.
s, the 20-bit word string data DM (20) is 1
The additional word data group DAV obtained from the 0B / 8B conversion / 8-bit word string data forming unit 83 and obtained from the word data separation / speed conversion unit 82 is supplied to the serial data restoration unit 63 '.

In 10B / 8B conversion / 8-bit word string data forming section 83, 20-bit word string data D
M (20) is subjected to a 10B / 8B conversion process in which each of the 10 bits is divided, and each of the divided 10 bits is sequentially converted to 8-bit data. The word transmission rate is set to 135 MBp based on the obtained 8-bit data.
The 8-bit word string data DM (8) is formed as s. The word transmission rate obtained from the 10B / 8B conversion / 8-bit word string data forming unit 83 is 135M.
The 8-bit word string data DM (8) having Bps is supplied to the serial data restoration unit 63 ′.

Although not shown, the serial data restoring unit 63 'has the same configuration as the serial data restoring unit 63 shown in FIG. In the serial data restoring unit 63 ′, redundant description is omitted for the 8-bit word string data DM (8) obtained from the 10B / 8B conversion / 8-bit word string data forming unit 83. 16 is 10B / 8
The same processing as that performed on the 8-bit word string data DM (8) obtained from the B conversion / 8-bit word string data forming unit 64 is performed, and the 8-bit word string data DM is processed.
Based on (8), each increases the bit transmission rate to 270 Mb
ps 4-channel serial digital signal DV
S1 'to DVS4' are obtained. Thus, the four-channel serial digital signals DVS1 'to DVS4' obtained from the serial data restoration unit 63 'are supplied to the S / P conversion units 84, 85, 86 and 87, respectively.

In the S / P converter 84, the serial digital signal DVS1 'is multiplied by the formula: X + 1, and the product of the operation result is further multiplied by a ninth-order primitive polynomial: X
⁹ + X ⁴ +1 is subjected to descrambling processing (or without descrambling processing), and is applied to the descrambled serial digital signal DVS1 ′ (or directly to the serial digital signal DVS1 ′). A word transmission rate of 27 MBps, which is a 10-bit quantized digital signal based on the serial digital signal DVS1 'after being subjected to S / P conversion.
The digital video signal DVP1 is reproduced.

Similarly, in the S / P converter 85, the serial digital signal DVS2 'is multiplied by the formula: X + 1, and the product of the operation result is further multiplied by a ninth-order primitive polynomial: X ⁹ + X ⁴ +1. S / P conversion is performed on the descrambled serial digital signal DVS2 ′ (or directly on the serial digital signal DVS2 ′) by performing descrambling processing by multiplication (or without descrambling processing). And a word transmission rate of 27 MB, which is a 10-bit quantized digital signal based on the serial digital signal DVS2 ′.
and reproduces the digital video signal DVP2 at
In the P conversion section 86, the serial digital signal DV
S3 ′ is subjected to descrambling by multiplying the expression: X + 1 and further multiplying the product resulting from the operation by a ninth-order primitive polynomial: X ⁹ + X ⁴ +1 (or
The S / P conversion is performed on the descrambled serial digital signal DVS3 '(or directly on the serial digital signal DVS3') without descrambling the serial digital signal DVS3 '.
The digital video signal DVP3 having a word transmission rate of 27 MBps, which is a 10-bit quantized digital signal based on S3 ', is reproduced.
, The serial digital signal DVS4 '
The descrambling process is performed by multiplying the product of the formula: X + 1 and further multiplying the product of the operation result by a ninth-order primitive polynomial: X ⁹ + X ⁴ +1 (or without performing the descrambling process). The applied serial digital signal DVS4 ′ (or
A digital video signal DVP having a word transmission rate of 27 MBps, which is a 10-bit quantized digital signal based on the serial digital signal DVS4 'by performing S / P conversion (directly on the serial digital signal DVS4').
Play 4

As a result, the S / P converters 84 to 87
Reproduced word transmission rate of 4 channels is 27MB
Digital video signals DVP1 to DVP4 of ps are obtained.

FIG. 20 shows a transmission signal forming unit 44 in the example of the data transmission apparatus shown in FIG. 15 according to the example of the data transmission method according to the invention described in the claims of the present application.
, Composite 20-bit word string data DZ
(20) shows an example of a data receiving apparatus that receives a transmission signal SZ based on the serial data DZS that has been converted and has been subjected to scramble processing (or not subjected to scramble processing).

In the example of the data receiving apparatus shown in FIG. 20, for example, an electric signal suitable for a data transmission path formed by using a coaxial cable or an optical fiber formed by using an optical fiber is used. And a receiving unit 90 for receiving a transmission signal SZ which is an optical signal suitable for the data transmission path. The receiving unit 90 transmits the transmission signal SZ
, The scrambled (or unscrambled) serial data DZS based on the received transmission signal SZ is reproduced,
It is supplied to the synchronous data detection / S / P converter 91.

In the synchronous data detection / S / P converter 91, the scrambled serial data DZ
S is multiplied by the expression: X + 1, and a ninth-order primitive polynomial:
The descrambling process is performed on the scrambled serial data DZS by multiplying by X ⁹ + X ⁴ +1 to obtain the scrambled serial data (or directly take in the scrambled serial data DZS). ).

Further, a synchronous data detection / S / P converter 9
1 is 20-bit word synchronous data in serial data DZS obtained by performing descrambling processing on the scrambled serial data DZS (or serial data DZS not performing scrambling processing). Three consecutive 20-bit word data 3FF: 3FFh, 000: 000h, 000:
000h is converted into serial data, the serial data is detected as synchronous data, word synchronization is performed based on the detected synchronous data, and the serial data DZS is descrambled to obtain serial data (or
Serial data DZ not subjected to scramble processing
S / P conversion is performed on S, for example, the word transmission rate is
Composite 20 which is parallel data with 4.25 MBps
The bit word string data DZ (20) is formed. Then, the composite 20-bit word string data DZ (20) obtained from the synchronous data detection / S / P converter 91 is supplied to the word data separation / speed converter 92.

The synchronous data detection / S / P converter 91
, The composite 20-bit word string data DZ (2
0) in the additional word data group DAV
Three consecutive 20-bit word data 3FF: 3FFh, 000000h which are 0-bit word synchronous data
And 000: 000h, and sends out a synchronous data detection output signal SDD. This synchronous data detection output signal S
DD is, for example, the composite 20-bit word string data DZ detected by the synchronous data detection / S / P converter 91.
Three consecutive 20-bit word data 3FF: 3FF in the additional word data group DAV in (20)
It is obtained corresponding to the last of h: 000: 000h and 0: 000h. In this way, the synchronous data detection output signal SDD obtained from the synchronous data detection / S / P conversion section 91 is output from the word data separation / speed conversion section 9.
2 and a serial data restoration unit 63 ″. The serial data restoration unit 63 ″ has a clock pulse signal CA having a frequency of 270 MHz and a frequency of 143 MHz.
Is also supplied.

In the word data separation / speed conversion section 92, the synchronization data detection output signal SDD from the synchronization data detection / S / P conversion section 91 is used and added from the composite 20-bit word string data DZ (20). The word data group DAV is separated, and the word transmission rate based on the composite 20-bit word string data DZ (20) is set to 74.
20-bit word string data DM (2
0) and the additional word data group DAV are separated from each other and taken out. Then, a word transmission rate of 7 is added to the extracted 20-bit word string data DM (20).
From 4.25 MBps, increase the word transmission rate to 6.
A speed conversion to 9.5 MBps is performed.

As a result, the word transmission rate obtained from the word data separation / speed conversion unit 92 is reduced to 69.5 MBp.
s, the 20-bit word string data DM (20) is 1
An additional word data group DAV obtained from the 0B / 8B conversion / 8-bit word string data forming unit 93 and obtained from the word data separation / speed conversion unit 92 is supplied to the serial data restoration unit 63 ″.

In 10B / 8B conversion / 8-bit word string data forming section 93, 20-bit word string data D
M (20) is subjected to a 10B / 8B conversion process in which each of the divided 10 bits is divided into 8-bit data by dividing the 10 bits at a time, and is sequentially performed by the 10B / 8B conversion process. Based on the obtained 8-bit data, the word transmission rate is set to 139 MBp
The 8-bit word string data DM (8) is formed as s. The word transmission rate obtained from the 10B / 8B conversion / 8-bit word string data forming unit 83 is 139M.
The 8-bit word string data DM (8) having Bps is supplied to the serial data restoration unit 63 ″.

Although not shown, the serial data restoring section 63 ″ is configured in the same manner as the serial data restoring section 63 shown in FIG. 16. However, the serial data restoring section 63 ″ has a serial data restoring section 63 ″. Six memory units corresponding to the memory units 70A to 73A in the unit 63;
Memory units 70B to 7 in serial data restoration unit 63
6B corresponding to 3B and six switches corresponding to four switches 75 to 78 in the serial data restoration unit 63 are respectively provided in the switch 65 and the control signal forming unit 66 in the serial data restoration unit 63. It is provided in addition to the corresponding parts.

In the serial data restoration unit 63 ″, the 8-bit word string data DM is divided for each time section corresponding to a specific frame period in which a control signal corresponding to the control signal CDF shown in FIG. 16 is synchronized. Eight 20-bit word string data constituting the first portion corresponding to the specific frame period of (8) are written together in six memory units, respectively, and the 8-bit word string data DM
Six 20-bit word string data constituting the second portion corresponding to the specific frame period of (8) are written together in six memory units.

Then, in the time section corresponding to every other specific frame period, the six 20-bit word string data written in the six memory units are read out from the six memory units, respectively. At this time, each of the six 20-bit word string data written in the six memory units is read as forming serial data, and each of the six 20-bit word string data is read from the six memory units. 6 first read outputs are obtained.

In another time section corresponding to every other specific frame period, six 20-bit word string data written in the six memory units are read from the six memory units, respectively. At this time, each of the six 20-bit word string data written in the six memory units is read as forming serial data, and each of the six 20-bit word string data is read out from the six memory units. Six second readout outputs that are serial data are obtained.

Then, these six first read outputs and six second read outputs are synthesized by six switches, and each of the six switches is converted into a series of serial digital signals. A 6-channel digital video signal is obtained. These 6-channel digital video signals are reproduced by the serial data restoration unit 63 ″.
2-channel digital video signals DVS1 and DVS2 each having a bit transmission rate of 270 Mbps;
These are four-channel digital video signals DVSa to DVSd each having a bit transmission rate of 143 Mbps.

In the example of the data transmission method implemented by using the example of the data transmission apparatus shown in FIG. 1, FIG. 14 or FIG. 15, for example, serialization of four channels or six channels is performed. A digital video signal or a digital video signal which is parallel data of four channels is multiplexed and transmitted. However, the number of digital video signals to be multiplexed and transmitted is not limited to four or six channels, but may be arbitrary. Channels.

[0141]

As is apparent from the above description, in the data transmission method according to any one of the first to sixth aspects of the present invention, a plurality of digital video Serial data based on a 20-bit word string data to which a 20-bit word synchronization data to which a predetermined code is given based on a signal and to which a 20-bit word synchronization data is added is received on the receiving side under the condition that good transmission quality is obtained. The data synchronization state required for the reproduction processing of a plurality of digital video signals based on the composite 20-bit word string data can be transmitted so as to be reliably obtained. Converting the composite 20-bit word string data to which the bit word synchronization data is added into serial data, transmitting the converted serial data, Raniwa, on the reception side, the serial data received, the received serial data composite 20
Conversion to bit word string data, for example, HDTV
This can be performed by using a transmission circuit device used for transmitting and receiving a digital video signal under the system. Therefore, according to the data transmission method according to the invention described in any one of claims 1 to 6 in the claims of the present application, a digital video signal can be relatively easily prepared by means of:
The plurality is multiplexed so that it can be reliably reproduced on the receiving side, and 8B / 10B conversion can be performed before transmission.

Also, in the data transmission apparatus according to the invention described in claim 7 of the present application, a 20-bit word provided with a predetermined code based on a plurality of digital video signals is provided. Reproduction of a plurality of digital video signals based on the composite 20-bit word string data received on the receiving side while obtaining good transmission quality, based on the composite 20-bit word string data to which the synchronization data is added. The data synchronization state required for the processing is transmitted in a manner that ensures that it can be obtained.
Conversion of the composite 20-bit word string data to which the 0-bit word synchronization data is added to serial data, transmission of the converted serial data, reception of serial data, and reception of the composite 20 Conversion to bit word string data, for example, HD
This can be performed by using a transmission circuit device used for transmission and reception of a digital video signal under a TV system. Therefore, according to the data transmission device of the invention described in claim 7 of the present application, a plurality of digital video signals can be reliably arranged on the receiving side by means that can relatively easily prepare the digital video signals. Multiplexed so that it can be reproduced and 8B /
The transmission can be performed after performing the 10B conversion.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A block configuration showing an example of the data transmission device according to the invention described in claim 7 in the claims of the present application, in which the example of the data transmission method according to the invention described in 2, 3, 4, or 6 is implemented. FIG.

[Fig. 2] Claims 1 and 2 in the claims of the present application.
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

[Fig. 3] Claims 1 and 2 in the claims of the present application.
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

[Fig. 4] Claims 1 and 2 in the claims of the present application.
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

[Fig. 5] Claims 1 and 2 in the claims of the present application.
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

[Fig. 6] Claim 1, Claim 1 in the claims of the present application.
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 7 is a block diagram showing a specific configuration example of a speed conversion / data insertion unit in the example shown in FIG. 1;

FIG. 8: Claim 1 in the claims of the present application
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 9: Claim 1 in the claims of the present application
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 10: Claim 1 in the claims of the present application
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 11 is a view showing a first embodiment of the present invention;
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 12: Claim 1 in the claims of the present application
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 13: Claim 1 in the claims of the present application
7 is a time chart for explaining an example of a data transmission method according to the invention described in 2, 3, 4 or 6.

FIG. 14: Claim 1 in the claims of the present application
FIG. 13 shows another example of the data transmission device according to the invention described in claim 7 in the claims of the present application, in which the example of the data transmission method according to the invention described in 2, 3, 5, or 6 is implemented. It is a block block diagram.

FIG. 15: Claim 1, in the claims of the present application
Still another example of the data transmission method according to the seventh aspect of the present invention, in which another example of the data transmission method according to the second, third, fourth, or sixth aspect of the present invention is implemented. It is a block diagram showing an example.

FIG. 16 is a view showing a first embodiment of the present invention;
FIG. 9 is a block diagram illustrating an example of a data receiving apparatus that receives a transmission signal transmitted according to the example of the data transmission method according to the invention described in 2, 3, 4, or 6.

FIG. 17 is a time chart for explaining an example of the data receiving apparatus shown in FIG. 16;

FIG. 18 is a time chart for explaining an example of the data receiving apparatus shown in FIG. 16;

FIG. 19: Claim 1 in the claims of the present application
FIG. 9 is a block diagram showing an example of a data receiving device that receives a transmission signal transmitted according to the example of the data transmission method according to the invention described in 2, 3, 5, or 6.

FIG. 20. Claim 1 in the claims of the present application
FIG. 9 is a block diagram showing an example of a data receiving device that receives a transmission signal transmitted according to another example of the data transmission method according to the invention described in 2, 3, 4, or 6.

FIG. 21 is a conceptual diagram explaining an example of a data format of a digital video signal.

FIG. 22 is a conceptual diagram explaining an example of a data format of a digital video signal.

[Explanation of symbols]

11, 11 ', 11 "... Compound word string data forming section, 12 to 15, 31, 36, 65, 75 to 78,.
・ Switch, 17, 66 ・ ・ ・ Control signal forming unit, 2
0A to 23A, 20B to 23B, 33, 34, 70A
73A, 70B to 73B: memory unit, 25A, 2
5B, 26: Data set part, 27: 8B / 1
0B conversion / 20-bit word string data forming unit
..Speed conversion / data insertion unit, 30 ... word data transmission unit, 32 ... switch control signal formation unit, 3
5 ... memory control signal forming section, 38, 41, 43
..P / S converters, 39, 42, 44... Transmission signal generators, 60, 80, 90... Receivers, 61, 8
1, 91: synchronous data detection / S / P converter, 6
2, 82, 92 ... word data separation / speed conversion unit,
63, 63 ', 63 "... serial data restoration unit,
64, 83, 93... 10B / 8B conversion / 8-bit word string data forming section, 84-87... S / P conversion section

Claims (7)

[Claims] 1. A plurality of digital video signals, each of which is written in a predetermined unit section into a plurality of memory means, and the unit sections written in each of the plurality of memory means are sequentially read out as word string data. The plurality of word string data read from the plurality of memory means are respectively subjected to 8-bit / 10-bit conversion processing to form 20-bit word string data, and the 20-bit word string data is subjected to transmission rate conversion processing. At a predetermined word interval, an additional word data group including 20-bit word synchronization data to which a preset code is given is inserted to form composite 20-bit word sequence data, and the composite 20-bit word sequence is formed. Data transmission for converting data into serial data and transmitting the serial data for transmission Law. 2. An additional word data group is selected so as to include, as a 20-bit word synchronization data, a portion in which a plurality of 20-bit word data to which a predetermined code is assigned is connected in a specific arrangement. The data transmission method according to claim 1, wherein: 3. A plurality of 20-bit word data to which an additional word data group is assigned a predetermined code based on timing reference data included in each of a plurality of digital video signals is arranged in a specific arrangement. 3. The data transmission method according to claim 1, wherein the portion is selected to include the 20-bit word synchronization data. 4. A digital video signal comprising a plurality of digital video signals,
4. The data transmission method according to claim 1, wherein the bit-quantized digital signal is obtained by serial transmission in a state where it has been subjected to a scramble process. 5. A digital video signal system comprising:
2. A method according to claim 1, wherein the bit-quantized digital signal is obtained by parallel transmission.
4. The data transmission method according to 2 or 3. 6. A scramble process is performed on serial data obtained by converting composite 20-bit word string data,
6. The data transmission method according to claim 1, wherein the scrambled serial data is transmitted to be transmitted. 7. For each of a plurality of digital video signals, each predetermined unit section is written to a plurality of memory means, and the unit sections written to each of the plurality of memory means are sequentially read as word string data. 20-bit word string data forming means for performing an 8-bit / 10-bit conversion process on the plurality of word string data respectively read from the plurality of memory means and forming 20-bit word string data; 20 obtained from
The bit word string data is subjected to transmission rate conversion processing, and at a predetermined word interval, an additional word data group including 20-bit word synchronization data to which a preset code is given is inserted, and Speed conversion / data insertion means for forming bit word string data; data transmission for converting composite 20-bit word string data obtained from the speed conversion / data insertion means into serial data and transmitting the serial data for transmission Means for transmitting data.