JP2001094403A - Delay circuit capable of setting delay time and method for measuring its delay time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay circuit capable of setting its delay time that can be tested with high accuracy and to provide a method for measuring its delay time. SOLUTION: This delay circuit is provided with a delay element section that consists of cascade connection of a plurality of delay elements, selects one of outputs of respective stages in response to a selection signal, sets a prescribed delay time to a received signal and outputs it, inverts each receiving the output, switch circuits that are closed in response to a control signal to feed back the output of the inverters to the input of the delay element section so as to form a ring oscillation circuit with the delay element section and the inverters, and a 1/n frequency divider circuit (where n is an integer being 2 or over). The 1/n frequency divider circuit, the delay element section, the inverters and the switch circuits are integrated as an IC. The IC has an input terminal and an output terminal that provides the output of the 1/n frequency divider circuit externally. The IC generates the selection signal and the control signal in response to the signal received from the input terminal for the purpose of measuring the delay time of each delay element to provide the output of the ring oscillation circuit at the output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit in which a delay time can be set, and a method for measuring the delay time. The present invention relates to a delay circuit that can be set and a method for measuring the delay time.

[0002]

2. Description of the Related Art In recent CD-R / RWs, the data writing speed has been increased to twice, four times, eight times,.... In this CD-R / RW, write data transferred from a host computer through an interface such as SCSI or ATPI is usually subjected to EFM modulation and added to a laser controller, and a laser beam controlled for writing by the laser controller is subjected to EFM. The modulated data is turned on / off and irradiated onto a predetermined track of the CD, whereby data is written.
In addition to such CD-R / RW, CD-R, DVD-
In the case of an optical disc such as a RAM, a circuit for setting a very small delay time of about psec to several nsec with high accuracy, especially when writing the data, is required. Further, with the increase in the clock speed of the CPU or the like, it is necessary to set a small delay time of about psec to several nsec with high accuracy even in a general logic circuit.

[0003]

The delay time of a delay circuit whose delay time can be set is affected by the manufacturing process of each product or each semiconductor circuit. For this reason, in a conventional delay circuit that sets a minute delay time with high accuracy, the delay time is set by adjusting the voltage from the outside in the manufacturing process,
The variation can be absorbed, for example, as described in Japanese Patent Application Laid-Open No. 7-868.
No. 88, a delay circuit is provided with a control terminal for controlling a delay time, an actual delay amount is measured by a measuring means, and control is performed so that an appropriate delay time is obtained based on the measurement result. A control signal is applied to the terminals. However, the smaller the delay time becomes from psec to several nsec, the smaller the difference between the controlled delay values becomes, so the delay time must be measured with high accuracy. Will be needed. If this high-accuracy measurement circuit is incorporated together with the delay circuit, the integrated area becomes large. For this reason, usually, an input signal is added and its output is measured externally by a measuring device to measure a delay time. However, when an external measuring device performs measurement of psec to several nsec with high accuracy, the measurement is performed. However, there is a drawback in that the method of connection and the method of connection are problematic, thereby causing errors. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and to provide a delay circuit capable of setting a delay time and a method of measuring the delay time capable of testing a set delay time with high accuracy. To provide.

[0004]

A feature of the present invention that achieves the above object is that a delay circuit whose delay time can be set is characterized in that a plurality of delay elements are connected in cascade and each of the stages is provided in accordance with a selection signal. A delay element for selecting one of the outputs and setting a predetermined delay time with respect to the input signal and outputting the signal, an inverter receiving the output, and turning on the control signal to turn on the output of the inverter And a 1 / n frequency-dividing circuit (where n is an integer of 2 or more) which receives the output of the ring oscillation circuit by forming a ring oscillation circuit with the delay element section and the inverter by feeding back to the input of the circuit. , 1 / n frequency dividing circuit, delay element section, inverter and switch circuit are I
An input terminal integrated as C and an output terminal for outputting the output of the 1 / n frequency dividing circuit to the outside are provided in the IC, and are selected according to a signal input from the input terminal for measuring the delay time of the delay element. A signal and a control signal are generated to obtain an output of the ring oscillation circuit at an output terminal. Further, according to the configuration of the delay time measuring method for a delay circuit capable of setting a delay time according to the present invention, a predetermined input signal is input to an input terminal of the delay circuit provided in the IC to control the selection signal. And output signals of first and second periods are obtained from output terminals at first and second different cascading stages of the delay element, respectively, and the delay is performed based on the first and second periods. This is for calculating the delay time of the element.

[0005]

As described above, in the delay circuit according to the present invention in which the delay time can be set, the period 2 (A + m) of the output signal of the ring oscillation circuit output from the output terminal to the outside.
With respect to X), the period Tm of the output signal obtained at the output terminal becomes Tm = 2n (A + mX), and a signal obtained by dividing the period (oscillation frequency) of the ring oscillation circuit by 1 / n can be obtained. This is a signal of 2n times the actually measured delay time, so that the influence of the error of the measurement result of the delay time measured based on this signal can be reduced to 1 / 2n. Here, A is the delay time of the inverter, m is the number of connection stages of the selected delay element, and X is the delay time per delay element stage. In this case, when the delay time A of the inverter is not known, the respective delay periods are measured with different numbers of stages by the latter delay time measurement method, and a subtraction process is performed between these, so that the delay time of the inverter as a common term is obtained. Since A can be canceled, the delay time can be obtained with high accuracy. As a result, it is possible to easily incorporate and realize a delay circuit capable of setting the delay time, which can test the set delay time with high accuracy, as an IC.

[0006]

FIG. 1 is a circuit diagram of an embodiment of the present invention to which a delay circuit whose delay time can be set is applied. The delay circuit 7 is a delay circuit built in the IC 10 and capable of setting a delay time, and has a delay element unit 1 in which buffer amplifiers 1a, 1b,... The output of each stage of the buffer amplifier is connected to an output terminal 7b via an analog switch (or transmission gate, the same applies hereinafter) SWa, SWb,..., SWn, and via an analog switch which is turned on among these analog switches. Output terminal 7b
An input signal is output. Thus, the output signal is given a selected delay time with respect to the signal input to the first-stage buffer amplifier 1a from the input terminal 7a via the analog switch 2.

The input terminal 7a is connected to the input terminal of the buffer amplifier 1a via the analog switch 2,
By turning off the analog switch 2, the delay element 1
Can be separated from the signal input side. The inverter 3 is connected to the output terminal 7b.
Output from the buffer amplifier 1 via the analog switch 6
A ring oscillator circuit is formed by the delay element unit 1 and the inverter 3 when the analog switch 6 is turned on, being connected to the input terminal a. The output of inverter 3 is
The output of the ring oscillation circuit, which is input to the n-ary counter 5, is divided by the n-ary counter 5 into 1 / n. The n-ary counter 5 is a specific example of a 1 / n frequency dividing circuit.

The controller 4 includes an analog switch SW
a, SWb,..., SWn.
Is generated, the number of delay stages is selected, and the output of the selected buffer amplifier is output to the output terminal 7b. As a result, the delay time of one buffer amplifier X × the delay time m of the number of connection stages m
× X is given to the output signal. Analog switch SW
The ON / OFF control signals of a, SWb,..., SWn are performed by the controller 4 receiving a control signal of predetermined data from the outside at the input terminal 4a, and controlling n bits corresponding to the total number n of connection stages of the buffer amplifier. This is performed by a signal S. An analog bit having a set delay time in which bits of a stage corresponding to the number of delay stages selected corresponding to a set delay time out of n bits are set to “1” and other bits are set to “0” Switches are turned on and others are turned off.
The analog switch 2 is normally set to the ON state, and is turned OFF by the controller 4. Conversely, the analog switch 6 is normally set to the OFF state,
It is turned ON by the controller 4. Therefore, the controller 4 has a built-in decoder, and when a control signal is received from the outside at the input terminal 4b, the analog switches 2, 6 according to the content of the control signal (serial data) are provided.
Are turned on / off, respectively.

Reference numerals 10a and 10b denote input terminals of the IC 10, respectively, which are connected to input terminals 4a and 4b to which control data of the controller 4 is input. Also, 10c
Is an output terminal of the IC 10, to which the output of the n-ary counter 5 is connected. 10d is a ground connection terminal of the IC 10. Therefore, when setting the delay time and measuring the delay time, first, the analog switch SW
a, SWb,..., SWn, a data string for turning on the analog switch SW at an arbitrary stage is input from the input terminal 10a to the controller 4 via the input terminal 4a. The controller 4 decodes the input data and turns on a target analog switch. On the other hand, the input terminal 10
b, another data string is input to the input terminal 4b of the controller 4. The controller 4 decodes the signal, turns on the analog switch 6, and turns the analog switch 2 on.
Change to F. As a result, the analog switches SWa, SW
b,..., SWn, a feedback circuit is formed by the analog switch turned ON and the inverter 3.
The delay circuit 7 oscillates as a ring oscillation circuit. Of course, if another data string is input from the input terminal 10b to the input terminal 4b of the controller 4, the controller 4
Decode it and turn off analog switch 6,
Turning on the analog switch 2 returns to the state as the original delay circuit. This operates as a delay circuit whose delay time can be set.

Here, assuming that the delay time of the inverter 3 is A, the cycle T of this ring oscillation circuit is T = 2 (A + m
X). Here, m is the number of stages of buffer amplifiers connected in cascade from input to output, and X is the delay time per buffer amplifier stage. Therefore, the period Tm of the output signal of the n-ary counter 5 obtained from the output terminal 10c is Tm = n × T = 2n (A + m
X). This period Tm is measured by the period measuring device 11. If the delay time A of the inverter 3 is known, X can be obtained by the above equation, but if unknown, the next analog switch is turned on to increase the number of connection stages of the buffer amplifier by one. , And the number of stages is m + 1.
At this time, the period Tm + 1 of the output signal of the n-ary counter 5 is
Tm + 1 = n × T = 2n (A + mX + X). This period Tm + 1 is measured by the period measuring device 11. And Tm + 1
When Tm is calculated, Tm + 1-Tm = 2n (A + mX + X)
−2n (A + mX) = 2nX, and the buffer amplifier 1
A value of 2n times the delay time per unit can be obtained. The actually set delay time is obtained by obtaining the delay time X per one buffer amplifier and by using mX. At this time, the measurement frequency of the cycle measuring device 11 is n times as high as the 1 / n frequency division, and the error is 2n times as large as the error. When calculating the delay time per two switches, the analog switch two steps ahead is turned ON, and m
+2, Tm + 2−Tm = 2n (A + mX + 2X) −
2n (A + mX) = 4nX can be obtained.

By the way, as the buffer amplifier to be selected in the measurement, it is preferable to select a buffer amplifier to be used as much as possible. For example, when the delay time uses a five-stage buffer, the first-stage analog switch SW
The cycle may be measured by setting a to ON, and then the cycle may be measured by turning on the sixth-stage analog switch. As described above, in the embodiment, an example of a buffer amplifier is given as a delay element. However, as the delay element of the delay element section of the present invention, a predetermined operation delay such as an even number of inverters, flip-flops, gate circuits, etc. Of course, a circuit element that operates with time may be used as the delay element.

[0012]

As described above, according to the present invention, the period of the output signal obtained at the output terminal is equal to the period 2 (A + mX) of the output signal of the ring oscillation circuit output from the output terminal to the outside. Tm becomes Tm = 2n (A + mX),
A signal obtained by dividing the cycle (oscillation frequency) of the ring oscillation circuit by 1 / n can be obtained. Since this is a signal of 2n times the actually measured delay time, the influence of the error of the measurement result of the delay time measured based on this signal is reduced by half.
n. Here, A is the delay time of the inverter, m is the number of connection stages of the selected delay element, and X is the delay time per delay element stage. As a result, it is possible to easily incorporate and realize a delay circuit capable of setting the delay time, which can test the set delay time with high accuracy, as an IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention to which a delay circuit capable of setting a delay time is applied.

[Explanation of symbols]

1 ... delay element section, 1a, 1b, 1n ... buffer amplifier,
2, 6, SWa, SWb, SWn: Analog switch (transmission gate), 4: Controller, 7a, 10a, 1
0b: input terminal, 5: n-ary counter, 7b, 10c: output terminal, 7: delay circuit, 10: IC, 11: cycle measuring device.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshikazu Iinuma 21-term Mizonzakicho, Ukyo-ku, Kyoto-shi ROHM Co., Ltd. F-term (reference) 2G032 AA03 AD06 AK11 5J001 BB00 BB07 BB12 BB20 BB21 BB24 DD09

Claims (4)

[Claims] A delay element section for cascade-connecting a plurality of delay elements, selecting one of outputs of respective stages according to a selection signal, setting a predetermined delay time with respect to an input signal, and outputting the set delay time; An inverter receiving the output, a switch circuit that is turned on in response to a control signal, feeds back the output of the inverter to an input of the delay element unit, and forms a ring oscillation circuit with the delay element unit and the inverter; A 1 / n frequency dividing circuit (where n is an integer of 2 or more) for receiving an output of the ring oscillation circuit, wherein the 1 / n frequency dividing circuit, the delay element section, the inverter, and the switch circuit form an IC. An integrated input terminal and an output terminal for outputting the output of the 1 / n frequency dividing circuit to the outside are provided in the IC, and in response to a signal input from the input terminal for measuring a delay time of the delay element. Before Selection signal and the control signal generated by the ring delay time is configurable delay circuit output, characterized in that get to the output terminal of the oscillation circuit. 2. The delay circuit according to claim 1, further comprising a circuit in said IC for generating said selection signal and said control signal in accordance with a signal from said input terminal. 3. A delay element section which cascade-connects a plurality of delay elements, selects one of the outputs of each stage according to a selection signal, sets a predetermined delay time with respect to an input signal, and outputs the result. An inverter receiving the output, a switch circuit that is turned on in response to a control signal, feeds back the output of the inverter to an input of the delay element unit, and forms a ring oscillation circuit with the delay element unit and the inverter; A 1 / n frequency dividing circuit (where n is an integer of 2 or more) for receiving an output of the ring oscillation circuit, wherein the 1 / n frequency dividing circuit, the delay element section, the inverter, and the switch circuit form an IC. For the integrated delay circuit, an input terminal and an output terminal for outputting the output of the 1 / n frequency dividing circuit to the outside are provided in the IC, and a predetermined input signal is input to the input terminal to perform the selection. Signal and said And output signals of first and second cycles are respectively obtained from the output terminals at first and second different numbers of cascaded stages of the delay element. Calculating a delay time of the delay element based on the delay time. 4. The delay time measuring apparatus according to claim 3, further comprising a circuit for generating the selection signal and the control signal in accordance with a signal from the input terminal. Method.