JP2001094018A - Semiconductor package and production method thereof - Google Patents
Semiconductor package and production method thereofInfo
- Publication number
- JP2001094018A JP2001094018A JP30283299A JP30283299A JP2001094018A JP 2001094018 A JP2001094018 A JP 2001094018A JP 30283299 A JP30283299 A JP 30283299A JP 30283299 A JP30283299 A JP 30283299A JP 2001094018 A JP2001094018 A JP 2001094018A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- resin
- line
- substrate
- mold resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器、電気機
器、コンピューター、通信機器等に用いられるプリント
基板に係る。更には、半導体を搭載する半導体パッケー
ジ用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board used for electronic equipment, electric equipment, computers, communication equipment and the like. Further, the present invention relates to a semiconductor package substrate on which a semiconductor is mounted.
【０００２】[0002]
【従来の技術】ソルダーレジスト保護膜を形成したプリ
ント回路基板において、金メッキ、銀ペースト塗布、半
導体の搭載、ワイヤボンディング、モールド樹脂で封止
をして、半導体パッケージの保護層を形成している。2. Description of the Related Art On a printed circuit board having a solder resist protective film formed thereon, gold plating, silver paste application, mounting of a semiconductor, wire bonding, and sealing with a mold resin are performed to form a protective layer of a semiconductor package.
【０００３】[0003]
【発明が解決しようとする課題】この方法では、基板、
特に、ソルダーレジスト面とモールド樹脂の接着性が低
いため、剥離したり 時には、ポップコーン現象が起こ
ったりして問題となることがある。その原因は、ソルダ
ーレジスト樹脂とモールド樹脂との相互溶解性の違い、
あるいは接触面積が少ない、あるいはモールド樹脂と銅
の熱膨張率の違い、あるいは、モールド樹脂と基板との
機械的密着力（アンカー効果）が殆どなく、僅かな水分
や有機物による汚れの影響により、加工操作の工程でこ
の剥離の問題が発生している。そこで、ソルダーレジス
ト面を粗化したり、基板面にピンを埋め込む等色々な工
夫が行われている。また、特開平９−２０５１６４で
は、半田レジストを塗布した後、これを選択的にエッチ
ング（溶解とも言う）して円形形状又は六角形形状の開
放部を形成し、回路基板とパッケージ胴体（モールド樹
脂とも言う）との接合力を強化する方法が述べられてい
るが、密着性を強化は出来るが半田レジスト（ソルダー
レジストとも言う）とパッケージ胴体の接触面での剥離
は依然として改善されていない。In this method, a substrate,
In particular, since the adhesiveness between the solder resist surface and the mold resin is low, when peeling off, a popcorn phenomenon may occur, which may cause a problem. The cause is the difference in mutual solubility between the solder resist resin and the mold resin,
Alternatively, the contact area is small, the difference in the coefficient of thermal expansion between the mold resin and copper, or the mechanical adhesion (anchor effect) between the mold resin and the substrate is negligible, and processing is performed due to the influence of dirt due to slight moisture or organic substances. This separation problem occurs in the operation process. Therefore, various measures have been taken such as roughening the solder resist surface and embedding pins in the substrate surface. In Japanese Patent Application Laid-Open No. 9-205164, after a solder resist is applied, it is selectively etched (also referred to as melting) to form a circular or hexagonal open portion, and a circuit board and a package body (mold resin) are formed. A method for enhancing the bonding strength between the solder resist and the package body has not been improved yet, although the adhesion can be enhanced, but the contact surface between the solder resist (also referred to as a solder resist) and the package body has not been improved.
【０００４】[0004]
【課題を解決するための手段】本発明は、半導体搭載の
周辺部のソルダーレジスト面に、抜き枠のラインを形成
し、その抜き枠の内部においては、基材樹脂やパターン
ラインが露出している。本技術は、そのプリント回路基
板面にも、モールド樹脂で直接封止する方法である。こ
の抜き枠ラインの構造にすることにより、ソルダーレジ
ストとモールド樹脂との剥離性の問題を解決することが
出来、その技術を完成した。According to the present invention, a line of a cutout frame is formed on a solder resist surface in a peripheral portion of a semiconductor mounting, and a base resin and a pattern line are exposed inside the cutout frame. I have. The present technology is a method of directly sealing a printed circuit board surface with a mold resin. By adopting the structure of the blank frame line, the problem of the releasability between the solder resist and the mold resin can be solved, and the technology has been completed.
【０００５】本発明は、プリント回路基板（例えば、Ｂ
ＧＡ基板，ＣＳＰ基板）において、ソルダーレジストを
塗布して保護膜を形成するに際して、樹脂モールド部の
端部の周囲にソルダーレジスト面の抜き枠のラインを有
する構造の半導体パッケージ及びその製造法である。The present invention relates to a printed circuit board (for example, B
(GA substrate, CSP substrate), and a method of manufacturing a semiconductor package having a structure having a cutout line of a solder resist surface around an end of a resin mold portion when a solder resist is applied to form a protective film. .
【０００６】本発明は、抜き枠のラインは、ソルダーレ
ジストのない空間の線幅０．１〜１ｍｍ（好ましくは、
０．３〜０．８ｍｍ）で、１〜３本を有する構造の半導
体パッケージの製造法である。According to the present invention, the line of the blank frame has a line width of 0.1 to 1 mm (preferably, a space without solder resist).
This is a method for manufacturing a semiconductor package having a structure having 0.3 to 0.8 mm) and having 1 to 3 wires.
【０００７】本発明は、ソルダーレジスト面の抜き枠の
ラインが、ソルダーレジスト面と接触するモールド樹脂
の金型面の内部に収まる構造の半導体パッケージの製造
法である。The present invention is a method of manufacturing a semiconductor package having a structure in which a line of a cutout frame on a solder resist surface fits inside a mold surface of a mold resin that comes into contact with the solder resist surface.
【０００８】[0008]
【発明の実施の形態】本発明の実施形態について以下に
詳述する。本発明は、従来の方法において、ソルダーレ
ジスト保護膜の形状に一部工夫を加えて、プリント回路
基板の基材面にモールド樹脂が直接接着できる構造（半
導体の周辺部に抜き枠のラインを有する構造）に、ソル
ダーレジスト面を加工することにより、課題を解決する
ことが出来た。Embodiments of the present invention will be described in detail below. The present invention provides a structure in which a mold resin can be directly adhered to a substrate surface of a printed circuit board by partially modifying the shape of a solder resist protective film in the conventional method (having a frame line at the periphery of a semiconductor). The problem could be solved by processing the solder resist surface to (Structure).
【０００９】本発明に使用するプリント回路基板は、市
販の銅箔５〜７０μｍと絶縁基材として、エポキシ樹
脂、ポリイミド樹脂、ビスマレインイミドトリアジン
（ＢＴ）樹脂、ＰＰＥ樹脂を、或いは、該樹脂をガラス
繊維、ガラス布或いは紙に含浸させたプリプレーグを重
ね合せて銅箔両面基板あるいは多層基板を作成した。そ
の基板の厚さは、０．０５〜２．４ｍｍの基板である。The printed circuit board used in the present invention is a commercially available copper foil having a thickness of 5 to 70 μm and an insulating base material made of epoxy resin, polyimide resin, bismaleimide triazine (BT) resin, PPE resin, or A prepreg impregnated with glass fiber, glass cloth or paper was overlapped to form a double-sided copper foil substrate or a multilayer substrate. The thickness of the substrate is 0.05 to 2.4 mm.
【００１０】次に、銅層面にドリルあるいはレーザーに
より穴を形成し、メッキにより導通を確保して後、印刷
法あるいはフォトレジストシート法を使用してエッチン
グにより回路パターンを形成する。Next, a hole is formed in the copper layer surface by a drill or a laser, and conduction is secured by plating, and then a circuit pattern is formed by etching using a printing method or a photoresist sheet method.
【００１１】続いて、ソルダーレジストにより、パター
ンの形成を行う。本発明は、プリント回路基板に、ソル
ダーレジストパターンを形成する際、半導体を搭載する
その周辺部に抜き枠のラインを形成するようにする。即
ち、金メッキする個所や半導体を搭載する箇所の他に、
その半導体を搭載する周辺部（半導体を搭載した回路か
ら引き出された導通パターン上）でモールド樹脂で封止
するソルダーレジスト面においてソルダーレジストを抜
いたライン箇所を有するパターン構造とする。プリント
回路基板の中でも、特に、ＢＧＡ基板、ＣＳＰ基板など
の半導体パッケージ基板において、本発明は優れた効果
を発揮する。Subsequently, a pattern is formed using a solder resist. According to the present invention, when a solder resist pattern is formed on a printed circuit board, a blank frame line is formed at a peripheral portion where a semiconductor is mounted. In other words, besides the place to be plated with gold and the place to mount the semiconductor,
A pattern structure having a line portion where the solder resist is removed on a solder resist surface to be sealed with a mold resin in a peripheral portion on which the semiconductor is mounted (on a conductive pattern drawn from a circuit mounting the semiconductor). Among the printed circuit boards, the present invention exerts an excellent effect particularly on a semiconductor package board such as a BGA board and a CSP board.
【００１２】本発明に使用するＢＧＡ基板、ＣＳＰ基板
は、“プリント回路技術便覧”（プリント回路学会編）
を参考にして作製した。The BGA substrate and CSP substrate used in the present invention are described in "Printed Circuit Technology Handbook" (edited by the Japan Printed Circuit Society).
The reference was made.
【００１３】本発明の基板の抜き枠ラインの形成方法に
ついて詳述する。抜き枠ラインは、ソルダーレジストパ
ターンにより形成する。その位置は、搭載した半導体の
周辺部で、導通線上に形成し、且つ、モールド材で封止
するに際して、ソルダーレジスト面に接触するモールド
樹脂の金型面の内側に抜き枠のラインの外周ラインが位
置し、モールド樹脂がそのライン内に充填される構造に
する。抜き枠ラインが金型面の下に来るような構造にす
ると、僅かな位置ずれで、モールド樹脂が抜き枠ライン
に充填されない場合があり好ましくない。また、抜き枠
ラインが金型面の内部に入りすぎると、抜き枠ラインと
モールド部端部が離れてしまい、密着性の確保されない
端部からモールド材が剥離するので好ましくない。抜き
枠の幅は、０．１〜１ｍｍ、好ましくは、０．３〜０．
８ｍｍのラインで、１〜３本形成する。ラインの本数が
多い方が、接着性が向上して好ましいが、ラインスペー
スが広くなり好ましくない。好ましい本数は、３本以内
である。抜き枠ラインの厚みは、内部の構造により多少
変動するが、硬化したソルダーレジスト面の厚みは、１
００〜１０μｍである。本発明のソルダーレジストパタ
ーンの形成方法は、スクリーン印刷法、カーテンコータ
ー法、スプレーコーター法、ロールコーター法、ディッ
プコーター法、フイルム状レジスト貼付法等の塗工／貼
付法、及び、これらに、必要に応じて、写真法等のパタ
ーン形成法を組み合わせて行う方法が挙げられる。抜き
枠ライン内には、基板の導通パターンと基材面があり、
導通パターン（具体的には、パターンラインや部分メッ
キ用のリード線）により多少の凸凹が生じている。モー
ルド樹脂で封止をすると、ソルダーレジストの厚みや導
通パターンの凸凹により接触面積が向上し、凸凹による
アンカー効果が期待される。更に、ソルダーレジストと
の密着性の高い基材樹脂と直接接触するので、密着強度
が著しく向上することが分った。The method for forming a frame line of a substrate according to the present invention will be described in detail. The blank frame line is formed by a solder resist pattern. The position is the outer peripheral line of the line of the punching frame inside the mold surface of the mold resin that contacts the solder resist surface when forming on the conductive line and sealing with the mold material at the peripheral portion of the mounted semiconductor. Is located, and the molding resin is filled in the line. If the frame line is located below the mold surface, the molding resin may not be filled into the frame line due to slight displacement, which is not preferable. On the other hand, if the blanking frame line is too much inside the mold surface, the blanking frame line is separated from the end of the molded part, and the molding material is peeled off from the end where the adhesion is not ensured, which is not preferable. The width of the blanking frame is 0.1 to 1 mm, preferably 0.3 to 0.
One to three lines are formed on an 8 mm line. A larger number of lines is preferable because the adhesion is improved, but a line space is undesirably large. The preferred number is three or less. The thickness of the blank frame line slightly varies depending on the internal structure, but the thickness of the cured solder resist surface is 1
00 to 10 μm. The method for forming a solder resist pattern of the present invention includes coating / pasting methods such as a screen printing method, a curtain coater method, a spray coater method, a roll coater method, a dip coater method, a film-like resist sticking method, and the like. According to the method, there is a method in which a pattern forming method such as a photographic method is used in combination. In the outline frame, there is a conductive pattern of the substrate and the substrate surface,
Some irregularities are caused by the conduction pattern (specifically, a pattern line or a lead wire for partial plating). When sealing with a mold resin, the contact area is improved due to the thickness of the solder resist and the unevenness of the conductive pattern, and an anchor effect due to the unevenness is expected. Furthermore, since it came into direct contact with the base resin having high adhesiveness to the solder resist, it was found that the adhesive strength was significantly improved.
【００１４】本発明に有効なソルダーレジストは、一般
に用いられている、光硬化型のソルダーレジストが用い
られる。例えば、太陽インキ製造社製のＰＳＲ−４００
０が揚げられる。As a solder resist effective for the present invention, a generally used photocurable solder resist is used. For example, PSR-400 manufactured by Taiyo Ink Manufacturing Co., Ltd.
0 is fried.
【００１５】続いて、金メッキを行い、その面に銀ペー
ストを塗布し、半導体を搭載後、銀ペーストを乾燥硬化
し、ワイヤボンディングをする。これらの操作は、一般
に行われている方法が適用できる。例えば、銀ペースト
は、熱硬化性の銀ペーストが用いられる（例えば、日立
化成工業（株）ＥＬ−４０７２）。その塗布の方法は、
一般に行われている印刷方式やポッティング方式が用い
られる。半導体を搭載後、銀ペーストを硬化して、搭載
した半導体と基板回路を金ワイヤボンディングで接続す
る。Subsequently, gold plating is performed, a silver paste is applied to the surface, a semiconductor is mounted, the silver paste is dried and hardened, and wire bonding is performed. For these operations, generally used methods can be applied. For example, as the silver paste, a thermosetting silver paste is used (for example, Hitachi Chemical Co., Ltd. EL-4072). The method of application is
A commonly used printing method or potting method is used. After mounting the semiconductor, the silver paste is cured, and the mounted semiconductor and the substrate circuit are connected by gold wire bonding.
【００１６】続いて、半導体及び接続回路を保護するた
めに、半導体とその周辺部をモールド材で封止する本発
明の方法について詳述する。本発明で使用するモールド
材は、金型を用いてトランスファー成形法により封止層
を形成する。使用出来るモールド材は、広く用いられて
いるエポキシ系樹脂からなる熱硬化性のモールド樹脂や
モールド液体が用いられる（モールド樹脂は、日東電工
社の製品：ＭＰ−１５０ＳＧ、モールド液体は、日立化
成工業（株）の製品：ＣＫＣ−１０００）。Next, the method of the present invention for sealing the semiconductor and its periphery with a molding material to protect the semiconductor and the connection circuit will be described in detail. The molding material used in the present invention forms a sealing layer by a transfer molding method using a mold. The molding material that can be used is a thermosetting molding resin or a molding liquid made of a widely used epoxy resin (the molding resin is a product of Nitto Denko Corporation: MP-150SG, and the molding liquid is Hitachi Chemical Co., Ltd.) (Product of KKC: CKC-1000).
【００１７】露出した抜き枠ラインの基板面は、基材樹
脂が露出し銅線により凸凹のある構造となっていて、モ
ールド樹脂で封止すると、基材樹脂層と直接接着し、ま
た、接着面積が増加して密着性が非常に高くなり、モー
ルド樹脂の剥離が完全に抑制することを確認した。The substrate surface of the exposed blanking frame line has a structure in which the base resin is exposed and uneven by a copper wire, and when sealed with a mold resin, directly adheres to the base resin layer. It was confirmed that the area was increased and the adhesion became extremely high, and the peeling of the mold resin was completely suppressed.
【００１８】[0018]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。使用したＢＧＡ基板は、１２μｍの銅箔のＢＴ樹
脂両面板（厚み：０．４ｍｍ）に、銅メッキされたスル
ーホール（３ｃｍ四角形内に２５０個のスルーホール）
を有する集合基板であるEmbodiments of the present invention will be described below with reference to the drawings. The BGA substrate used is a copper-plated through-hole (250 through-holes in a 3 cm square) on a 12 μm copper foil BT resin double-sided board (thickness: 0.4 mm).
Is an aggregate substrate having
【図１】。ソルダーレジスト（使用したソルダーレジス
トは、太陽インキ社製のＰＳＲ−４０００である。）を
使用して、抜き枠ラインを有するパターンを印刷して硬
化し、ソルダーレジストで保護された部分金メッキされ
たＢＧＡ基板を形成し使用したFIG. Using a solder resist (the solder resist used is PSR-4000 manufactured by Taiyo Ink Co., Ltd.), a pattern having a blank frame line is printed and cured, and the partially gold-plated BGA protected by the solder resist is printed. Substrate formed and used
【図２】。本実験では、ソルダーレジストの抜き枠ライ
ンを有するＢＧＡ基板、抜き枠ラインの無いＢＧＡ基板
のサンプルを各１０枚作成し、抜き枠ラインの有る、無
しの違いによる接着性の比較を行った。ラインの位置
は、回路パターンの外枠の位置で、しかも、成形金型の
内側に接近した位置に、０．５ｍｍ幅のラインを０．４
ｍｍ間隔で２本が接近した構造のソルダーレジスト膜
（厚さ：３０μｍ）で形成したものを使用したFIG. In this experiment, 10 samples each of a BGA substrate having a blank frame line of a solder resist and a BGA substrate having no blank frame line were prepared, and the adhesiveness was compared by the difference between having and without a blank frame line. The position of the line is the position of the outer frame of the circuit pattern, and at the position close to the inside of the molding die, a line with a width of 0.5 mm is
A solder resist film (thickness: 30 μm) having a structure in which two wires approach each other at an interval of mm was used.
【図３】。抜き枠ラインの内部は、多数の導通パターン
と露出した樹脂層が交互に存在する構造をしていたFIG. The inside of the frame line had a structure in which a large number of conductive patterns and an exposed resin layer were present alternately.
【図４】。スタッドプル法でモールド樹脂の密着性を測
定し、比較評価した。所定の場所に銀ペースト（市販
品：日立化成工業（株）：ＥＮ−４７２０）を塗布し、
半導体を搭載し、乾燥機に入れて乾燥硬化した（１５０
℃、６０分）。続いて、金ワイア・ボンディングをし
て、モールド樹脂（日東電工社の製品：ＭＰ−１５０Ｓ
Ｅ）をトランスファー成形して封止したFIG. The adhesiveness of the mold resin was measured by a stud pull method and compared and evaluated. A silver paste (commercial product: Hitachi Chemical Co., Ltd .: EN-4720) is applied to a predetermined place,
The semiconductor was mounted and dried and hardened in a dryer (150
° C, 60 minutes). Subsequently, gold wire bonding is performed, and a molding resin (a product of Nitto Denko Corporation: MP-150S) is formed.
E) was transfer molded and sealed
【図４】。ソルダーレジスト膜とモールド樹脂との密着
性はＰＣＴ（プレッシャークッカーテスト：１２１℃、
２Ｋｇ／ｃｍ２Ｇの水蒸気下で１６８時間放置）後の半
田リフロー（赤外線リフローテスト；ピーク温度２３０
℃、１８０℃以上６０秒）で密着性を調べてみた。抜き
枠のある全試料でモールド樹脂の剥離は起こらなかっ
た。また、ポップコーンの発生も起こっていなかった。FIG. The adhesion between the solder resist film and the mold resin was determined by PCT (pressure cooker test: 121 ° C,
Solder reflow (infrared reflow test; peak temperature 230) after 2 kg / cm 2 G in water vapor for 168 hours.
At 180 ° C. for 60 seconds). No peeling of the mold resin occurred in all the samples having the punched frame. Also, no popcorn was generated.
【００１９】[0019]
【比較例】実施例で使用したＢＴ樹脂両面板に、抜き枠
のないソルダーレジスト膜を形成した以外はすべて同じ
方法でサンプル（１０枚）を作製し、実施例と同じ方法
で半導体を搭載して、モールド樹脂を載せ、同じ方法で
密着性を測定した。モールド樹脂が完全に剥離した試料
は１枚あり、ほとんどの試料（１０枚中７枚）で、ソル
ダーレジスト面とモールド樹脂の界面に隙間が、全体あ
るいは一部に発生していた。COMPARATIVE EXAMPLE Samples (10 samples) were prepared by the same method except that a solder resist film without a blanking frame was formed on both sides of the BT resin used in the example, and a semiconductor was mounted by the same method as in the example. Then, the mold resin was placed, and the adhesion was measured by the same method. There was one sample from which the mold resin was completely peeled off, and in most of the samples (seven out of ten), a gap was formed in the entire or part of the interface between the solder resist surface and the mold resin.
【００２０】[0020]
【発明の効果】抜き枠ラインのあるソルダーレジストパ
ターンを形成したプリント回路基板において、モールド
樹脂で保護層を形成することにより、基板とモールド樹
脂の密着性が著しく改善される。その結果、不良品の発
生は殆どなくなり、又、長期使用に対しても剥離等が起
こらなくなり、品質的にも安定し、製造コストも安くす
ることができた。According to the present invention, in a printed circuit board on which a solder resist pattern having a frame line is formed, the adhesion between the substrate and the mold resin is significantly improved by forming the protective layer with the mold resin. As a result, almost no defective products were generated, and peeling or the like did not occur even when used for a long time, the quality was stabilized, and the manufacturing cost could be reduced.
【図１】銅メッキされたスルーホールを有するＢＧＡの
集合基板FIG. 1 BGA aggregate board with copper plated through holes
【図２】ソルダーレジストパターンが形成され金メッキ
されたプリント回路基板FIG. 2 is a printed circuit board on which a solder resist pattern is formed and plated with gold.
【図３】抜き枠ラインを形成したソルダーレジストの構
造FIG. 3 shows the structure of a solder resist having a blank frame line.
【図４】抜き枠ライン部の上から見た内部の構造FIG. 4 is an internal structure viewed from above a blank frame line portion.
【図５】半導体を搭載し、モールド樹脂保護層を形成し
たＢＧＡパッケージFIG. 5 is a BGA package on which a semiconductor is mounted and a mold resin protective layer is formed.
１：絶縁層 ２：導通パターン ３：銅メッキされたスルーホール ４：金メッキされた面 ５：ソルダーレジスト ６：抜き枠ライン ７：金／銅ライン ８；基板の樹脂面 ９：銀ペースト １０：金ボンディング １１：半導体 １２：モールド樹脂 １３：ソルダーレジストとモールド樹脂との密着性の評
価個所 １４：半田ボール1: Insulating layer 2: Conductive pattern 3: Copper plated through hole 4: Gold plated surface 5: Solder resist 6: Blanking frame line 7: Gold / copper line 8; Resin surface of substrate 9: Silver paste 10: Gold Bonding 11: Semiconductor 12: Mold resin 13: Evaluation point of adhesion between solder resist and mold resin 14: Solder ball
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M109 AA01 BA04 CA21 DB16 GA10 5E314 AA27 AA32 CC02 CC03 CC04 CC07 CC17 FF05 FF19 FF21 GG11 GG24 5F061 AA01 BA04 CA21 CB12 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M109 AA01 BA04 CA21 DB16 GA10 5E314 AA27 AA32 CC02 CC03 CC04 CC07 CC17 FF05 FF19 FF21 GG11 GG24 5F061 AA01 BA04 CA21 CB12
Claims (3)
ストを塗布して保護膜を形成するに際して、ソルダーレ
ジスト面に抜き枠のラインを樹脂モールド部の端部の周
囲に形成した構造の半導体パッケージ及びその製造法1. A semiconductor package having a structure in which a blank frame line is formed around an end of a resin mold portion on a surface of a solder resist when a solder resist is applied on a printed circuit board to form a protective film. Law
い空間線幅０．１〜１ｍｍで、１〜３本を有する構造で
あることを特徴とする請求項１の半導体パッケージの製
造法2. The method of manufacturing a semiconductor package according to claim 1, wherein the line of the blank frame has a space line width without solder resist of 0.1 to 1 mm and has 1 to 3 lines.
ソルダーレジスト面と接触するモールド樹脂の成形金型
面の内部に収まることを特徴とする請求項１の半導体パ
ケージの製造法3. A line of a blank frame on the solder resist surface is:
2. The method of manufacturing a semiconductor package according to claim 1, wherein the mold is set in a mold surface of a mold resin which comes into contact with a solder resist surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30283299A JP2001094018A (en) | 1999-09-20 | 1999-09-20 | Semiconductor package and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30283299A JP2001094018A (en) | 1999-09-20 | 1999-09-20 | Semiconductor package and production method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001094018A true JP2001094018A (en) | 2001-04-06 |
Family
ID=17913641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30283299A Pending JP2001094018A (en) | 1999-09-20 | 1999-09-20 | Semiconductor package and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001094018A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009150820A1 (en) * | 2008-06-11 | 2009-12-17 | パナソニック株式会社 | Semiconductor device and method for manufacturing the same |
| JP2010067850A (en) * | 2008-09-11 | 2010-03-25 | Sanyo Electric Co Ltd | Circuit device |
| JP2018074061A (en) * | 2016-11-01 | 2018-05-10 | 株式会社デンソー | Electronic device |
-
1999
- 1999-09-20 JP JP30283299A patent/JP2001094018A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009150820A1 (en) * | 2008-06-11 | 2009-12-17 | パナソニック株式会社 | Semiconductor device and method for manufacturing the same |
| JP2010067850A (en) * | 2008-09-11 | 2010-03-25 | Sanyo Electric Co Ltd | Circuit device |
| JP2018074061A (en) * | 2016-11-01 | 2018-05-10 | 株式会社デンソー | Electronic device |
| WO2018083997A1 (en) * | 2016-11-01 | 2018-05-11 | 株式会社デンソー | Electronic device |
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