JP2001093281A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an access speed for a memory cell can be increased and increase in current consumption can be suppressed. SOLUTION: A memory cell array 12 comprises plural main word lines MW, plural sub-word lines SW corresponding to each main word line, and sub-word lines SW in the direction of column, and is divided into plural sub-arrays 13A-13H. The plural main word lines MW is divided into two groups of main word line groups G1 and G2. A main word decoder 14 selects one main word line MW out of the main word line groups G1, G2, plural sub-word decoders 16A-16H select sub-word lines SW corresponding to one main word line group in sub-arrays 13A-13H. Plural driving circuits 20, 22 drive correspondent sub- word line SW based on a selected result of the main word decoder 14 and the sub-word decoders 16A-16H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to access to a memory cell array.

[0002]

2. Description of the Related Art FIG. 12 shows a DRAM as a conventional semiconductor memory device. The DRAM 100 includes a memory cell array 102, a main word decoder 104, a plurality of sub-word decoders 106, and a sense amplifier 108 for amplifying data read from the memory cell array 102. The memory cell array 102 includes a plurality of main word lines MW extending in the row (longitudinal) direction, a plurality of sub-word lines SW arranged along each main word line MW corresponding to each main word line MW, and a column ( And a plurality of bit lines BL extending in the (lateral) direction. Memory cell array 1
Numeral 02 is divided into a plurality (for example, eight) of sub-arrays 103 perpendicular to the main word line MW, including a plurality of sub-word lines SW in the column direction. Each sub word line SW
The memory cells C are connected between the respective bit lines BL. The main word decoder 104 is connected to a plurality of main word lines MW, and selects one of the main word lines MW when accessing a memory cell and sets the voltage level thereof to H. Each sub-word decoder 10
6 is provided corresponding to each sub-array 103, and outputs an H-level signal when accessing the memory cell C. Also, an AND circuit 1 corresponding to each sub-word line SW is provided.
10 are provided. One input terminal of each AND circuit 110 is connected to the main word line MW, and the other input terminal is connected to the output line of each sub-word decoder 106. When both the signal level of the main word line MW and the output signal level of each sub-word decoder 106 are at H level, each AND circuit 110 outputs an H-level signal to drive the corresponding sub-word line SW. Sense amplifier 108
Amplifies data transferred from the plurality of memory cells C connected to the selected sub-word line SW via the bit line BL.

In DRAM 100 configured as described above, an address signal is decoded into a selection signal by main word decoder 104, and any one of main word lines MW is selected. Also, the output signals of all the sub-word decoders 106 attain the H level based on the address signal, and the A signal connected to the selected main word line MW
The output signal of the ND circuit 110 becomes H level,
The sub word line SW corresponding to the D circuit 110 is driven. As a result, the memory cell C connected to the selected sub-word line SW is activated. At the time of reading data, data is transferred from the memory cell C to the sense amplifier 108 via the bit line BL, and the data amplified by the sense amplifier 108 is transferred to an output circuit via a column gate (not shown), and output from the output circuit. Is done. When writing data, write data is transferred to the memory cell C via the bit line BL.

[0004]

However, FIG.
In the DRAM 100 shown in FIG.
02, the memory cells that can be accessed at one time are 1
It is limited to the memory cells C connected to the plurality of sub-word lines SW corresponding to the main word line MW. For example, the main word decoder M
When Wi is selected, a plurality of sub-word lines SW corresponding to the main word line MWi are driven, and only the memory cells C connected to the driven sub-word line SW are accessed. Then, writing or reading of data to or from the memory cell C is performed, and at this time, the bit line BL is charged and discharged. Therefore, a plurality of sub-word lines SWi1, SWi2 corresponding to the main word line MWi and a plurality of sub-word lines SWj1, Sj corresponding to the main word line MWj.
In order to access the memory cell C connected to Wj2, it is necessary to access a plurality of times (in this case, twice), and there is a problem that the access time becomes long. Most of the current consumption of the DRAM 100 is the charge / discharge current of the bit line BL when accessing the memory cell.
If the access is performed a plurality of times in order to access a desired memory cell, the current consumption of the DRAM 100 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to increase the degree of freedom of access to a memory cell, thereby increasing the speed of access to the memory cell. It is another object of the present invention to provide a semiconductor memory device capable of suppressing an increase in current consumption.

[0006]

According to a first aspect of the present invention, a memory cell array is divided into a plurality of subarrays, and a plurality of subword lines are provided for each subarray.
In a semiconductor memory device in which a plurality of sub word lines are connected to a plurality of main word lines, a plurality of main word lines are selected, and a sub word line corresponding to one of the selected main word lines is selected in each sub array. The gist is that it was done.

According to the first aspect of the present invention, a plurality of main word lines are selected, and a sub word line corresponding to one of the selected main word lines in each sub array is selected. Therefore, when accessing a desired memory cell connected to a sub-word line corresponding to a plurality of different main word lines, the degree of freedom of access to the memory cell is improved, and the number of accesses to the memory cell array can be reduced. Thus, the access can be speeded up. Further, when accessing a desired memory cell, the number of accesses can be reduced, so that an increase in current consumption can be suppressed.

According to a second aspect of the present invention, there is provided a semiconductor memory device in which a memory cell array is divided into a plurality of sub arrays, a plurality of sub word lines are provided for each sub array, and the plurality of sub word lines are connected to a plurality of main word lines. , A plurality of main word lines are grouped into a plurality of main word line groups, and a main word decoder for selecting any one main word line in each main word line group; and a main word decoder provided for each of the sub-arrays; A plurality of sub-word decoders for selecting a sub-word line corresponding to any one of the plurality of main word line groups in each of the sub-arrays; and a selection of the main word decoder provided for each of the sub-word lines. Based on the result and the selection result of the sub-word decoder corresponding to the sub-array including the sub-word line And summarized in that and a plurality of drive circuits for driving a corresponding word line.

According to the second aspect of the present invention, one main word line is selected in a plurality of main word line groups, and a sub word line corresponding to any one of the main word line groups is selected in each sub array. . Then, the sub-word line is driven based on the selection result of the main word decoder and the selection result of the sub-word decoder. for that reason,
When accessing a desired memory cell connected to a sub-word line corresponding to a plurality of different main word lines, the degree of freedom in accessing the memory cell is improved, and the number of accesses to the memory cell array can be reduced. Access can be speeded up. Further, when accessing a desired memory cell, the number of accesses can be reduced, so that an increase in current consumption can be suppressed.

According to a third aspect of the present invention, there is provided a semiconductor memory device in which a memory cell array is divided into a plurality of sub arrays, a plurality of sub word lines are provided for each sub array, and the plurality of sub word lines are connected to a plurality of main word lines. , A plurality of sub-word lines arranged along a main word line are grouped, and a plurality of sub-word line groups are connected to each of the main word lines, and any one of the plurality of main word lines is connected. A main word decoder for selecting one;
A plurality of sub-word decoders provided corresponding to each of the sub-arrays and selecting any one of the plurality of sub-word lines corresponding to each of the main word lines in each of the sub-arrays; And a plurality of driving circuits for driving a corresponding sub-word line based on a selection result of the main word decoder and a selection result of a sub-word decoder corresponding to a sub-array including the sub-word line. .

According to the third aspect of the present invention, one main word line is selected, and one of a plurality of sub word lines corresponding to the main word line is selected in each sub array. Then, the sub-word line is driven based on the selection result of the main word decoder and the selection result of the sub-word decoder. Therefore, when accessing a desired memory cell connected to a plurality of different sub-word line groups, the degree of freedom of access to the memory cell is improved, and the number of accesses to the memory cell array can be reduced.
Access can be speeded up. Further, when accessing a desired memory cell, the number of accesses can be reduced, so that an increase in current consumption can be suppressed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a DRAM 10 as a semiconductor memory device of the present embodiment. The DRAM 10 includes a memory cell array 12, a main word decoder 14, and a plurality (eight in this embodiment) of sub word decoders 16A to 16H.
And a sense amplifier 18 for amplifying data read from the memory cell array 12.

The memory cell array 12 includes a plurality of main word lines MW extending in the row (longitudinal) direction, and a plurality of sub word lines SW arranged along each main word line MW corresponding to each main word line MW. , And a plurality of bit lines BL extending in the column (horizontal) direction. Each sub word line SW
The memory cells C are connected between the respective bit lines BL. Although not shown, the memory cell array 12 includes an inversion side bit line BL bar paired with each bit line BL, and a memory cell is connected between each sub word line SW and each bit line BL bar.

The memory cell array 12 includes a plurality of (for example, eight) sub arrays 13A to 13H including a plurality of sub word lines SW in the column direction and perpendicular to the main word line MW.
Is divided into Further, the plurality of main word lines MW are grouped into a plurality of (two in the present embodiment) main word line groups G1 and G2 having the same number, and the memory cell array 12 includes these main word line groups G1 and G2. ,
Arrays 12A and 12B are defined including G2.

The main word decoder 14 includes a plurality of decoding sections 14A, 14A, corresponding to the plurality of main word line groups G1, G2.
A plurality of main word lines MW constituting the main word line groups G1 and G2 are connected to each of the decoding units 14A and 14B. Each decoding unit 14A, 14B
Decodes an address signal into a selection signal when accessing the memory cell array 12, and selects one of the main word lines MW in each of the main word line groups G1 and G2.
And the voltage level thereof is set to H.

Each of the sub-word decoders 16A to 16H is provided corresponding to each of the sub-arrays 13A to 13H. Each of the sub-word decoders 16A to 16H is connected to the memory cell array 1
2, the address signal is decoded into a selection signal, and one of the two output lines 17a and 17b extending in the column direction is set to the H level, whereby any one of the plurality of main word line groups G1 and G2 is set. The sub word line SW corresponding to one main word line group is selected.

An AND circuit 20 as a driving circuit corresponding to each sub-word line SW in the array 12A.
And an AND circuit 22 as a drive circuit is provided corresponding to each sub-word line SW in the array 12B. One input terminal of each AND circuit 20 is connected to the main word line MW of the main word line group G1 corresponding to each sub word line SW, and the other input terminal is connected to the output line 17a of the sub word decoders 16A to 16H. I have. One input terminal of each AND circuit 22 is connected to the main word line MW of the main word line group G2 corresponding to each sub word line SW, and the other input terminal is connected to the output line 17b of the sub word decoders 16A to 16H. I have. Each A
When both the voltage level of the main word line MW and the voltage level of the output line 17a of each of the sub-word decoders 16A to 16H are at the H level, the ND circuit 20 outputs an H-level signal to drive the corresponding sub-word line SW. When both the voltage level of the main word line MW and the voltage level of the output line 17b of each of the sub-word decoders 16A to 16H are at the H level, each AND circuit 22 outputs an H-level signal to drive the corresponding sub-word line SW. .

The sense amplifier 18 receives a bit line B from a plurality of memory cells C connected to the driven sub-word line SW.
Amplify the data transferred via L. In the DRAM 10 configured as described above, the address signal is decoded into a selection signal by each of the decoding units 14A and 14B of the main word decoder 14, and each of the main word line groups G1 and G1,
In G2, one main word line MW is selected. Further, based on the address signal, only the voltage level of one of the output lines 17a and 17b of each of the sub-word decoders 16A to 16H becomes H level. Therefore, in each of the sub-arrays 13A to 13H,
The output signals of the ND circuits 20 and 22 become H level, and the sub word line SW corresponding to the AND circuit is selectively driven. As a result, the memory cell C connected to the selected sub-word line SW is activated.

At the time of reading data, the sense amplifier 1 is connected to the memory cell C via the corresponding bit line BL.
The data amplified by the sense amplifier 18 is transferred to an output circuit via a column gate (not shown) and output from the output circuit. At the time of data writing, write data is transferred to the corresponding memory cell C via the bit line BL.

The access of the memory cell will be specifically described. Now, each of the decoding units 14A, 14A,
14B, the address signal is decoded into a selection signal, and each of the main word line groups G1 and G2 is
One main word line MW, for example, main word line MW
i and MWj are selected.

Further, based on the address signal, only one of the output lines 17a and 17b of each of the sub-word decoders 16A to 16H attains the H level.
For example, in the sub-word decoder 16A, the output line 17a is at H level, in the sub-word decoder 16B, the output line 17b is at H level, in the sub-word decoder 16G, the output line 17b is at H level, and in the sub-word decoder 16H, the output line 17a is at H level. .

Therefore, in the sub-array 13A, the output signal of the AND circuit 20 connected to the main word line MWi is H
Level, and the sub-word line SW corresponding to the AND circuit 20 is driven. In the sub-array 13B, the output signal of the AND circuit 22 connected to the main word line MWj becomes H level, and the sub-word line SW corresponding to the AND circuit 22 is driven. In the sub-array 13G, the output signal of the AND circuit 22 connected to the main word line MWj becomes H level, and the sub-word line SW corresponding to the AND circuit 22 is driven. In the sub-array 13H, the output signal of the AND circuit 20 connected to the main word line MWi becomes H level, and the sub-word line SW corresponding to the AND circuit 20 is driven.

As a result, the memory cell C connected to the selected sub-word line SW is activated. When reading data, data is transferred from the memory cell C to the sense amplifier 108 via the bit line BL,
The data amplified at 8 is transferred to an output circuit via a column gate (not shown) and output from the output circuit. When writing data, write data is transferred to the memory cell C via the bit line BL.

As described above, in the memory cell array 10, when accessing a desired memory cell connected to a plurality of sub-word lines SW corresponding to a plurality of different main word lines MW, the number of accesses to the memory cell array 10 is reduced by one. , The number of accesses is reduced as compared with the conventional DRAM 100 (see FIG. 12), and the access can be speeded up. Most of the current consumed by the DRAM 10 is the charge / discharge current of the bit line BL when accessing the memory cell C. In this way, the number of accesses to the memory cell array 10 decreases in order to access a desired memory cell. Therefore, an increase in current consumption of the DRAM 10 is suppressed.

Next, the DRAM 1 configured as described above
An example in which 0 is applied for recording image data will be described with reference to FIGS. In the image processing, an operation of extracting a part of the entire screen of the display as a block is performed. FIG. 2 shows a block 26, which comprises eight pixel columns 26.
A to 26H, and each pixel column 26A to 26H includes eight pixels. FIG. 3 shows an example in which the block 26 is stored in the DRAM 10. In FIG. 3, for simplicity, DR
The output lines, bit lines and memory cells of the sub-word decoders 16A to 16H in the AM 10 are omitted, and only one main word line MW and a sub-word line SW corresponding to the main word line MW are shown.

In FIG. 3, one main word line MW
The data of each of the pixel columns 26A to 26H of the block 26 is stored in the memory cells connected to the plurality of sub-word lines SW corresponding to. In this example, the data of the rightmost pixel column 26A is stored in the subarray 13A, the data of the left pixel column 26B is stored in the subarray 13B, and so on.
The data of the leftmost pixel column 26H is stored in the sub-array 13H. For the sake of simplicity, assuming that the data of one pixel is a luminance signal of 8 bits (256 gradations), a memory cell of 64 bits (8 bits × 8 pixels) is connected to one sub-word line SW and one main word The word line MW is connected to memory cells of 512 bits (64 bits × 8 subarrays).

When all memory cells connected to the main word line MW shown in FIG. 3 are accessed, all data in the block 26 in FIG. 2 can be read and written. However, as shown in FIG. 4, data of eight pixel columns straddling a plurality of blocks 26 and 27 adjacent to each other cannot be read / written only by the memory cells connected to one main word line MW.

As shown in FIG. 4, when data of adjacent blocks 26 and 27 are stored in the memory cell array 12, the data of the block 26 is stored in the array 12A and the data of the block 27 is stored in the array 12B.

The data of each pixel column 26A to 26H of the block 26 is stored in each of the sub-arrays 13 of the array 12A as described above.
A to 13H. Block 27 to array 12B
Is stored in the subarray 13A, the data in the leftmost pixel column 27B is stored in the subarray 13B, and so on, and the data in the leftmost pixel column 27H is stored in the subarray 13B. 13H. By storing the data of the blocks 26 and 27 in the arrays 12A and 12B in this manner, the data of the eight pixel columns straddling the blocks 26 and 27 indicated by oblique lines in FIG. The data is stored in the memory cell connected to the SW. Therefore, one main word line is selected in each of the arrays 12A and 12B by the main word decoder 14, the array 12A is selected by the sub word decoders 16A to 16E, and the array 12 is selected by the sub word decoders 16F to 16H.
By selecting B, data of desired eight pixel columns can be read and written by one access to the memory cell array 12.

According to the DRAM 10 configured as described above, the following effects can be obtained. A plurality of main word line groups G
1 and G2, one main word line MW is selected, and in each of the sub-arrays 13A to 13H, a sub-word line SW corresponding to any one of the main word line groups G1 and G2 is selected. Therefore, when accessing a desired memory cell connected to the sub-word line SW corresponding to a plurality of different main word lines MW, the degree of freedom of memory cell access is improved, and the memory cell array 12
Can be reduced, and the access speed can be increased.

Most of the current consumption of the DRAM 10 is the charge / discharge current of the bit line BL when accessing the memory cell C. In order to access a desired memory cell as described above, the access to the memory cell array 10 is performed. Since the number of times can be reduced, an increase in current consumption of the DRAM 10 can be suppressed.

[Second Embodiment] Next, the present invention is applied to a DRAM.
A second embodiment of the present invention will be described with reference to FIGS. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals. In FIG. 6, for simplification, the bit lines and the memory cells in the DRAM 30 are omitted, and only the main word lines and the sub word lines are shown.

FIG. 6 shows a DRAM 30 as a semiconductor memory device of the present embodiment. The DRAM 30 includes a memory cell array 32, a main word decoder 34, and a plurality (eight in the present embodiment) of sub word decoders 36A to 36H.
And a sense amplifier 18 for amplifying data read from the memory cell array 32.

The memory cell array 32 includes a plurality of main word lines MW0, MW1, MW2,
.., A plurality of sub-word lines SW arranged along the main word line, and a plurality of bit lines extending in the column (lateral) direction. Note that a plurality of sub-word lines SWk (k = 0, 1, 2,...) Arranged along the main word line
..) as a group, and each main word line MW0, MW1,
Multiple (corresponding to MW2,..., Three in this embodiment)
Of sub word lines are provided. That is, for the main word line MW1, the sub word line groups SW1, SW
2 and 3 are provided.
For main word line MW2, main word line MW1
, And another sub-word line group (not shown) is provided in the same manner as the sub-word line groups SW1, SW2, SW3. Since there is no main word line adjacent to the main word line MW0 to the left of the main word line MW0, two sub word line groups of sub word line groups SW0 and SW1 are provided. Note that each main word line MW
Of the three sub-word line groups arranged corresponding to 0, MW1, MW2,..., The sub-word line groups at both ends are also used for main word lines adjacent to each other. That is, the sub word line group SW1 is connected to the main word line MW
0 and MW1, and the sub word line group SW3 is also used for the main word lines MW1 and MW2.

A memory cell is connected between each sub-word line SW and each bit line (not shown). The memory cell array 32 includes a plurality of sub-word lines SW in the column direction and a plurality (for example, 8
) Sub-arrays 33A to 33H.

The main word decoder 34 is connected to a plurality of main word lines MW0, MW1, MW2 and the like. The main word decoder 34 decodes an address signal into a selection signal when accessing the memory cell array 32, selects any one main word line, and sets its voltage level to H.

Each of the sub-word decoders 36A to 36H is provided corresponding to each of the sub-arrays 33A to 33H. Each of the sub-word decoders 36A to 36H is a memory cell array 3
2, the address signal is decoded into a selection signal at the time of access, and four output lines 37a, 37b,
One of the voltage levels 37c and 37d is set to H level.

A logic circuit 40 as a drive circuit is provided corresponding to a sub word line group adjacent to the right side of each main word line MW0, MW1, etc., and each main word line MW
, MW2,..., A logic circuit 50 as a drive circuit is provided corresponding to the sub-word line group adjacent to the left side.

Each logic circuit 40 includes an OR circuit 42 and an AND circuit 44. Two input terminals of the OR circuit 42 are connected to output lines 37b and 37d of each of the sub-word decoders. The OR circuit 42 outputs an H level signal when at least one of the output lines 37b and 37d has a voltage level of H. One input terminal of the AND circuit 44 is connected to a main word line corresponding to each sub word line, and the other input terminal is connected to an output terminal of the OR circuit 42. Therefore, when both the voltage level of the main word line and the voltage level of the output signal of the OR circuit 42 are at the H level, the AND circuit 44 outputs a signal at the H level to drive the corresponding sub-word line SW.

Each logic circuit 50 has two AND circuits 52,
54 and an OR circuit 56. One input terminal of the AND circuit 52 is connected to one main word line corresponding to each sub word line, and the other input terminal is connected to the output line 37c of each sub word decoder. AND circuit 5
2 outputs an H level signal when both the voltage level of the main word line and the voltage level of the output line 37c are H level. One input terminal of the AND circuit 54 is connected to the other main word line corresponding to each sub-word line, and the other input terminal is connected to the output line 37a of each sub-word decoder. AND circuit 54 outputs an H level signal when both the voltage level of the main word line and the voltage level of output line 37a are at the H level. Two input terminals of the OR circuit 56 are connected to output terminals of both AND circuits 52 and 54. Therefore, the OR circuit 56 is connected to the AND circuit 5
2, 54 of at least one output signal is at H level.
At this time, an H level signal is output to drive the corresponding sub word line SW.

In the DRAM 30 configured as described above, the address signal is decoded into a selection signal by the main word decoder 34, and one main word line is selected. Further, any one of the output lines 37a to 37d of each of the sub-word decoders 36A to 36H is determined based on the address signal.
Only the voltage levels of the two output lines become H level. Therefore, in each of the sub-arrays 33A to 33H, the output signal of one of the logic circuits 40 and 50 becomes H level, and the sub-word line SW corresponding to the logic circuit is selectively driven.
As a result, the memory cells connected to the selected sub-word line SW are activated.

Next, the access of the memory cell array 32 will be specifically described. Now, the address signal is decoded into a selection signal by the main word decoder 34, and one main word line MW, for example, the main word line MW1 is selected. Further, based on the address signal, only the voltage level of any one of the output lines 37a to 37d of each of the sub-word decoders 36A to 36H becomes H level. For example, in the sub-word decoder 36A, the output line 37a is at H level, in the sub-word decoder 36B, the output line 37a is at H level, in the sub-word decoder 36G, the output line 37b is at H level, and in the sub-word decoder 36H, the output line 37b is at H level. .

Therefore, in the sub-arrays 33A and 33B, the output signal of the logic circuit 50 connected to the main word line MW1 becomes H level, and the sub-word line SW1 corresponding to the logic circuit 50 is driven. Subarray 33G, 33
In H, the logic circuit 40 connected to the main word line MW1
Becomes an H level, and the sub-word line SW2 corresponding to the logic circuit 40 is driven.

As a result, the memory cell C connected to the selected sub-word line SW is activated. When reading data, data is transferred from the memory cell C to the sense amplifier 108 via the bit line BL,
The data amplified at 8 is transferred to an output circuit via a column gate (not shown) and output from the output circuit. When writing data, write data is transferred to the memory cell C via the bit line BL.

When accessing memory cell array 32, the address signal is decoded by main word decoder 34 into a selection signal, and one main word line M
W, for example, the main word line MW1 is selected. At this time, for example, the output line 37d of the sub-word decoder 36A is at the H level, the output line 37d of the sub-word decoder 36B is at the H level, the output line 37c of the sub-word decoder 36G is at the H level, and the output line 37c of the sub-word decoder 36H is at the H level. Level.

Then, in the sub-arrays 33A and 33B, the output signal of the logic circuit 40 connected to the main word line MW1 becomes H level, and the sub-word line SW2 corresponding to the logic circuit 40 is driven. Subarray 33G, 33
In H, the logic circuit 50 connected to the main word line MW1
Becomes an H level, and the sub-word line SW3 corresponding to the logic circuit 50 is driven.

As described above, in the memory cell array 30, desired memory cells connected to a plurality of different sub-word line groups SW0, SW1, etc. arranged corresponding to the respective main word lines MW0, MW1, etc., are accessed. In this case, the degree of freedom of memory cell access is improved and the memory cell array 3
0 is one, and the conventional DRAM 100
The number of accesses is reduced as compared with (see FIG. 12), and the access can be speeded up. Most of the current consumption of the DRAM 30 is the charge / discharge current of the bit line at the time of accessing the memory cell. However, since the number of accesses to the memory cell array 30 for accessing a desired memory cell is reduced, An increase in current consumption of the DRAM 30 can be suppressed.

When one main word line MW, for example, main word line MW1 is selected at the time of accessing memory cell array 32, each of sub arrays 33A to 33H is controlled based on the decoding result of sub word decoders 36A to 36H. Any sub word line of sub word lines SW1 to SW3 corresponding to main word line MW1 can be selected. Therefore, when the DRAM 30 configured as described above is applied to recording of image data, image processing can be suitably performed.

As shown in FIG. 8, data of blocks 60, 61, 62 and 63 adjacent to each other in the horizontal direction are stored in the memory cell array 32. Blocks 60, 61,
Reference numerals 62 and 63 denote a group of eight pixels arranged in a row of eight pixels, similarly to the block 26. In this case, for example, the data of the block 60 is stored in the memory cell connected to the sub-word line group SW1, the data of the block 61 is stored in the memory cell connected to the sub-word line group SW2,
The data of the block 62 is stored in a memory cell connected to the sub-word line group SW3, and the data of the block 63 is stored in a memory cell connected to the sub-word line group SW4.

By storing the data of each of the blocks 60 to 63 in each of the sub-word line groups SW1 to SW3, a block 65 composed of eight pixel columns extending over the blocks 60 and 61 as shown by oblique lines in FIG. And the data of the block 66 extending over the blocks 61 and 62 can be read / written from / to the desired memory cell by one access to the memory cell array 32.

In the DRAM 30 of the present embodiment, 1
Since a plurality of sub word line groups are provided for one main word line, the number of main word lines can be reduced and the wiring ratio can be improved by setting the number of sub word lines in the memory cell array to a predetermined value. At the same time, wiring design can be shortened.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. Note that the same elements as those described in FIG. 7 are denoted by the same reference numerals to avoid redundant description. In addition, the second
The description will focus on the differences from the embodiment.

This embodiment is different from the DRAM 3 of the second embodiment.
A drive circuit having the same function as the logic circuits 40 and 50 at 0 is realized by a transistor. The gate circuit 70 as a drive circuit corresponds to the logic circuit 40, and the gate circuit 72 as a drive circuit is the logic circuit 5
It corresponds to 0.

First, in order to select the sub-word line SW1, the voltage level of the output line 37a of each sub-word decoder is set to H, and the voltage level of the main word line MW1 is raised to H.

When the output line 37a rises, the transistors 77, 81, 85, 89 out of the 16 transistors
Becomes "H", and only the transistor 81 connected to the main word line MW1 transmits "H" information of the main word line MW1 to the second sub word line SW1 from the left. The transistors 77 and 85 are connected to the ground line (zero volt), and the transistor 89 is connected to the inactive main word line MW2 (M
(All the main word lines other than W1 are not raised), so that the remaining three sub word lines SW0, S
W2 and SW3 are fixed at zero volts.

Next, in order to select the sub-word line SW2, the voltage level of the output line 37b of the sub-word decoder is set to H, and the voltage level of the main word line MW1 is raised to H.

When the output line 37b rises, the transistors 75, 79, 83, 87 out of the 16 transistors
Of the main word line MW1, and only the transistor 83 connected to the main word line MW1 transmits the "H" information of the main word line MW1 to the sub word line SW2. Since the transistors 79 and 87 are connected to the ground line and the transistor 75 is connected to the non-rising main word line MW0, the remaining three sub-word lines SW0, SW1 and SW3 are fixed to zero volts.

Next, in order to select the sub-word line SW2, the voltage level of the output line 37d of the sub-word decoder is set to H and the voltage level of the main word line MW1 is raised to H.

When the output line 37d rises, the transistors 74, 78, 82, 86 out of the 16 transistors
Of the main word line MW1, and only the transistor 82 connected to the main word line MW1 transmits the "H" information of the main word line MW1 to the sub word line SW2. Since the transistors 78 and 86 are connected to the ground line and the transistor 74 is connected to the inactive main word line MW0, the remaining three sub-word lines SW0, SW1 and SW3 are fixed to zero volt.

Next, in order to select the sub-word line SW3, the voltage level of the output line 37c of the sub-word decoder is set to H, and the voltage level of the main word line MW1 is raised to H.

When the output line 37c rises, the transistors 76, 80, 84, 88 out of the 16 transistors
Of the main word line MW1, and only the transistor 88 connected to the main word line MW1 transmits the "H" information of the main word line MW1 to the sub word line SW3. Since the transistors 76 and 84 are connected to the ground line and the transistor 80 is connected to the inactive main word line MW0, the remaining three sub-word lines SW0, SW1 and SW2 are fixed to zero volts.

Since the present embodiment is configured as described above, the gate circuits 70 and 72 for selecting and driving the sub-word lines SW0, SW1, SW2, etc., in addition to the functions and effects similar to those of the second embodiment. Is composed of transistors, the area occupied by the circuit can be reduced.
It is possible to reduce the size and integration of the AM.

The embodiment is not limited to the above, but may be modified as follows. When performing image processing, data of a block of a desired pixel may not only extend over blocks adjacent in the horizontal direction (horizontal direction), but may also extend over blocks adjacent in the vertical direction (vertical direction). Also, as shown in the first to third embodiments, block data may be stored. In this case, it is necessary to access the memory cell array twice. However, compared to accessing the memory cell array four times in the conventional DRAM 100, the number of accesses to the memory cell array is reduced by half, and the access is speeded up. And an increase in current consumption of the DRAM can be suppressed.

As shown in FIG. 10, when performing image processing, data of a desired block 90 may straddle blocks B1 and B2 adjacent in the left-right (horizontal) direction and blocks B3 and B4 adjacent vertically. . As shown in FIG. 11, as a DRAM 91 for storing data of such a block 90, a memory cell array 92 includes four arrays 92A to 92D for storing data of blocks B1, B2, B3, and B4 in a row direction. Divided into Then, the data of the block B1 shown in FIG.
, The data of block B2 is stored in array 92B, the data of block B3 is stored in array 92C, and the data of block B4 is stored in array 92D. The main word decoder 93 includes arrays 92A to 92A.
D is configured by four decoding units corresponding to D, and when accessing the memory cell array 92, an address signal is decoded into a selection signal, and one of the main word lines in each of the arrays 92A to 92D is selected. I have. In this way, data in an arbitrary block 90 can be read and written by one access to the memory cell array 92.

In the first to third embodiments, the pixel block is divided in the vertical direction and the pixel data is stored in the memory cell array. However, the pixel block is divided in the horizontal direction and the pixel data is stored in the memory cell array. Data may be stored in a memory cell array.

In the first to third embodiments, the DRA
M, SRAM, flash memory, Fe
(Ferroelectric) It can be embodied in various memories such as a RAM.

In the first embodiment, the configuration of the second embodiment may be adopted. That is, a plurality of main word lines of the memory cell array are divided into a plurality of main word line groups, and a plurality of sub word lines arranged along the main word lines are grouped into one group. May be configured as a memory cell array configured to connect the sub-word line groups.

Next, other technical ideas that can be grasped from the above embodiments will be described below. The semiconductor memory device according to claim 2, wherein the main word decoder includes a plurality of decoder units corresponding to a plurality of main word line groups.

The semiconductor memory device according to claim 3, wherein a part of the plurality of sub-word line groups provided corresponding to each of the main word lines is connected to a main word line adjacent to each other. A semiconductor memory device that is also used.

[0071]

As described above in detail, according to any one of the first to third aspects of the present invention, it is possible to speed up access to a memory cell and suppress an increase in current consumption. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a semiconductor memory device according to a first embodiment.

FIG. 2 is an explanatory diagram showing a pixel block.

FIG. 3 is an explanatory diagram showing a method of storing pixel column data in a semiconductor memory device.

FIG. 4 is an explanatory diagram showing a data access method in a pair of adjacent pixel blocks.

FIG. 5 is an explanatory diagram showing an access method corresponding to a pixel column corresponding to FIG. 4;

FIG. 6 is a schematic configuration diagram illustrating a semiconductor memory device according to a second embodiment.

FIG. 7 is a circuit diagram illustrating a logic circuit.

FIG. 8 is an explanatory diagram showing a data access method in a pair of adjacent pixel blocks.

FIG. 9 is a schematic view showing a semiconductor memory device according to a third embodiment.

FIG. 10 is an explanatory diagram showing a plurality of pixel blocks adjacent to each other.

FIG. 11 is a schematic configuration diagram showing a semiconductor memory device of another embodiment.

FIG. 12 is a schematic configuration diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

12, 32, 92 ... memory cell array, 13A to 13
H, 33A to 33H ... subarray, 14, 34, 93 ...
Main word decoder, 16A-16H, 36A-36H ...
Sub word decoders, 40, 50... Logic circuits as drive circuits, 70, 72... Gate circuits as drive circuits, BL
... bit lines, G1, G2 ... main word line groups, MW, M
Wi, MWj: Main word line, SW: Sub word line.

Claims (3)

[Claims] In a semiconductor memory device in which a memory cell array is divided into a plurality of sub-arrays, a plurality of sub-word lines are provided for each sub-array, and the plurality of sub-word lines are connected to a plurality of main word lines, And a sub-word line corresponding to one of the selected main word lines in each sub-array. 2. A semiconductor memory device in which a memory cell array is divided into a plurality of sub-arrays, a plurality of sub-word lines are provided for each sub-array, and the plurality of sub-word lines are connected to a plurality of main word lines. Lines are grouped into a plurality of main word line groups, and any one of the main word line groups
A main word decoder for selecting one main word line; and a plurality of sub-words provided corresponding to each of the sub-arrays and selecting a sub-word line corresponding to any one of the plurality of main word line groups in each of the sub-arrays. A word decoder; and a corresponding sub-word line provided corresponding to each of the sub-word lines, based on a selection result of the main word decoder and a sub-word decoder corresponding to a sub-array including the sub-word line. A semiconductor memory device including a plurality of drive circuits. 3. A semiconductor memory device in which a memory cell array is divided into a plurality of sub-arrays, a plurality of sub-word lines are provided for each sub-array, and the plurality of sub-word lines are connected to a plurality of main word lines. A plurality of sub-word lines arranged as one group, and a plurality of sub-word line groups are connected corresponding to the respective main word lines; and a main word decoder for selecting any one of the plurality of main word lines A plurality of sub-word decoders provided corresponding to each of the sub-arrays and selecting any one of the plurality of sub-word lines corresponding to each of the main word lines in each of the sub-arrays; And a sub-word corresponding to a sub-array including the selection result of the main word decoder and the sub-word line. The semiconductor memory device comprising a plurality of drive circuits for driving the sub-word line corresponding based on the selection result of Dodekoda.